-
Notifications
You must be signed in to change notification settings - Fork 0
/
FSMContador.syr
383 lines (310 loc) · 14.9 KB
/
FSMContador.syr
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: FSMContador.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "FSMContador.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "FSMContador"
Output Format : NGC
Target Device : xc3s500e-4-fg320
---- Source Options
Top Module Name : FSMContador
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "FSMContador.v" in library work
Module <FSMContador> compiled
No errors in compilation
Analysis of file <"FSMContador.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <FSMContador> in library <work> with parameters.
S0 = "00"
S1 = "01"
S2 = "10"
S3 = "11"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <FSMContador>.
S0 = 2'b00
S1 = 2'b01
S2 = 2'b10
S3 = 2'b11
Module <FSMContador> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <FSMContador>.
Related source file is "FSMContador.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <E_Presente> of Case statement line 58 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <E_Presente> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
Found finite state machine <FSM_0> for signal <E_Presente>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 6 |
| Inputs | 2 |
| Outputs | 3 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <FSMContador> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <E_Presente/FSM> on signal <E_Presente[1:2]> with gray encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 11
11 | 10
-------------------
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <FSMContador> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block FSMContador, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 2
Flip-Flops : 2
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FSMContador.ngr
Top Level Output File Name : FSMContador
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 4
# LUT2 : 3
# LUT4 : 1
# FlipFlops/Latches : 2
# FDC : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 6
# IBUF : 3
# OBUF : 3
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-4
Number of Slices: 2 out of 4656 0%
Number of Slice Flip Flops: 2 out of 9312 0%
Number of 4 input LUTs: 4 out of 9312 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 232 3%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 2 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset | IBUF | 2 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 2.240ns (Maximum Frequency: 446.429MHz)
Minimum input arrival time before clock: 2.825ns
Maximum output required time after clock: 5.795ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.240ns (frequency: 446.429MHz)
Total number of paths / destination ports: 3 / 2
-------------------------------------------------------------------------
Delay: 2.240ns (Levels of Logic = 1)
Source: E_Presente_FSM_FFd2 (FF)
Destination: E_Presente_FSM_FFd2 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: E_Presente_FSM_FFd2 to E_Presente_FSM_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 5 0.591 0.637 E_Presente_FSM_FFd2 (E_Presente_FSM_FFd2)
LUT4:I3->O 1 0.704 0.000 E_Presente_FSM_FFd2-In1 (E_Presente_FSM_FFd2-In)
FDC:D 0.308 E_Presente_FSM_FFd2
----------------------------------------
Total 2.240ns (1.603ns logic, 0.637ns route)
(71.6% logic, 28.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Offset: 2.825ns (Levels of Logic = 2)
Source: Z (PAD)
Destination: E_Presente_FSM_FFd2 (FF)
Destination Clock: clk rising
Data Path: Z to E_Presente_FSM_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.218 0.595 Z_IBUF (Z_IBUF)
LUT4:I0->O 1 0.704 0.000 E_Presente_FSM_FFd2-In1 (E_Presente_FSM_FFd2-In)
FDC:D 0.308 E_Presente_FSM_FFd2
----------------------------------------
Total 2.825ns (2.230ns logic, 0.595ns route)
(78.9% logic, 21.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Offset: 5.795ns (Levels of Logic = 2)
Source: E_Presente_FSM_FFd2 (FF)
Destination: ENA (PAD)
Source Clock: clk rising
Data Path: E_Presente_FSM_FFd2 to ENA
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 5 0.591 0.808 E_Presente_FSM_FFd2 (E_Presente_FSM_FFd2)
LUT2:I0->O 1 0.704 0.420 E_Presente_FSM_Out21 (FIN_OBUF)
OBUF:I->O 3.272 FIN_OBUF (FIN)
----------------------------------------
Total 5.795ns (4.567ns logic, 1.228ns route)
(78.8% logic, 21.2% route)
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.13 secs
-->
Total memory usage is 255180 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)