/
zcu102.dts
257 lines (256 loc) · 8.72 KB
/
zcu102.dts
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/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
L22: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <10000000>;
L5: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L16>;
reg = <0>;
riscv,isa = "rv64imac";
status = "okay";
timebase-frequency = <10000000>;
tlb-split;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
L8: cpu@1 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L16>;
reg = <1>;
riscv,isa = "rv64imac";
status = "okay";
timebase-frequency = <10000000>;
tlb-split;
L6: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
L11: cpu@2 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L16>;
reg = <2>;
riscv,isa = "rv64imac";
status = "okay";
timebase-frequency = <10000000>;
tlb-split;
L9: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
L14: cpu@3 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L16>;
reg = <3>;
riscv,isa = "rv64imac";
status = "okay";
timebase-frequency = <10000000>;
tlb-split;
L12: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L16: memory@100000000 {
device_type = "memory";
reg = <0x1 0x0 0x0 0x80000000>;
};
L21: soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7 &L6 3 &L6 7 &L9 3 &L9 7 &L12 3 &L12 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
L2: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L3 65535 &L6 65535 &L9 65535 &L12 65535>;
reg = <0x0 0x0 0x0 0x1000>;
reg-names = "control";
};
L19: error-device@3000 {
compatible = "sifive,error0";
reg = <0x0 0x3000 0x0 0x1000>;
reg-names = "mem";
};
L15: external-interrupts {
interrupt-parent = <&L0>;
interrupts = <1 2>;
};
L0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 11 &L3 9 &L6 11 &L6 9 &L9 11 &L9 9 &L12 11 &L12 9>;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <3>;
riscv,ndev = <2>;
};
L17: mmio-port-axi4@60000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x0 0x60000000 0x20000000>;
};
L18: rom@10000 {
compatible = "sifive,rom0";
reg = <0x0 0x10000 0x0 0x10000>;
reg-names = "mem";
};
serial@60000000 {
compatible = "sifive,uart0";
reg = <0x00 0x60000000 0x00 0x1000>;
reg-names = "control";
};
};
amba_pl: amba_pl@0 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges ;
zynq_soc_i_hier_dma_axi_dma_arm: dma@60010000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;
//compatible = "xlnx,axi-dma-1.00.a";
#interrupt-cells = <1>;
interrupt-parent = <&L0>;
interrupts = <1 2>;
reg = <0x0 0x60010000 0x0 0x1000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
dma-channel@60010000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <1>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
dma-channel@60010030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <2>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
axi_ethernet_buf: ethernet@48000000 {
axistream-connected = <&zynq_soc_i_hier_dma_axi_dma_arm>;
axistream-control-connected = <&zynq_soc_i_hier_dma_axi_dma_arm>;
clock-frequency = <100000000>;
//clocks = <&clk_bus_0>;
compatible = "xlnx,dummy-ethernet-1.00.a";
device_type = "network";
//interrupt-parent = <&MBCORE_microblaze_0_axi_intc>;
interrupts = <4 2>;
phy-handle = <&phy0>; // see line 1660 of xilinx_axienet_main.c
phy-mode = "sgmii";
//reg = <0x40c00000 0x40000>;
xlnx,avb = <0x0>;
xlnx,enable-lvds = <0x0>;
xlnx,mcast-extend = <0x0>;
xlnx,phy-type = <0x5>;
xlnx,phyaddr = <0x1>;
xlnx,rxcsum = <0x0>;
xlnx,rxmem = <0x1000>;
xlnx,rxvlan-strp = <0x0>;
xlnx,rxvlan-tag = <0x0>;
xlnx,rxvlan-tran = <0x0>;
xlnx,simulation = <0x0>;
xlnx,stats = <0x1>;
xlnx,temac-addr-width = <0xc>;
xlnx,txcsum = <0x0>;
xlnx,txmem = <0x1000>;
xlnx,txvlan-strp = <0x0>;
xlnx,txvlan-tag = <0x0>;
xlnx,txvlan-tran = <0x0>;
xlnx,type = <0x1>;
local-mac-address = [00 0a 35 43 00 00];
axi_ethernet_buf_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
device_type = "ethernet-phy";
reg = <2>;
compatible = "Xilinx PCS/PMA PHY";
};
};
};
};
};