-
Notifications
You must be signed in to change notification settings - Fork 0
/
sigma_delta_adc.py
76 lines (60 loc) · 1.87 KB
/
sigma_delta_adc.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
from sys import maxsize
from nmigen import *
from nmigen.sim import *
import math
class SigmaDelta_ADC(Elaboratable):
def __init__(self, k=15):
if (k<=1):
raise ValueError("k must be greater than 1")
self.comparator = Signal()
self.feedback = Signal()
self.output = Signal( math.ceil(math.log2(k)) )
self.new_output = Signal()
self.k = k
def elaborate(self, platform):
m = Module()
counter = Signal(shape=range(self.k))
accumulator = Signal(shape=self.output.shape())
m.d.sync += [
self.feedback.eq(self.comparator),
counter.eq(counter+1),
accumulator.eq(self.comparator + accumulator),
self.new_output.eq(0)
]
with m.If(counter==0):
m.d.sync += [
accumulator.eq(0),
self.output.eq(accumulator),
self.new_output.eq(1),
]
return m
if __name__=="__main__":
k = 15
dut = SigmaDelta_ADC(k=k)
sim = Simulator(dut)
sim.add_clock(10e-9) #100MHz
def clock():
while True:
yield
def circuit():
integrator = 0.9
input = 0.8
f = 5e4
t = 0
yield dut.output.eq(k) # Drive high at the start to set gtkwave range
yield
while True:
#input = 0.5*(math.sin(2*math.pi*f*(t/100e6))+1)
t += 1
fb = yield dut.feedback
if fb==1:
integrator += 0.05*(1-integrator)
else:
integrator = integrator - 0.05*integrator
yield dut.comparator.eq(input>integrator)
# print(integrator)
yield
sim.add_sync_process(clock)
sim.add_sync_process(circuit)
with sim.write_vcd("S-D_ADC_waves.vcd"):
sim.run_until(5e-5)