clk: mxs: use xtal_ref as parent for SSP2

This patch is a workaround for experienced bit errors on SSP2
of i.MX28, where the SPI received data is always wrong in two
bits. For example for a 16-bit SPI read command where a
response is expected as 0xAA 0x55, the returned data is
0xAB 0x54.

The discussion about this problem can be found here:

https://community.freescale.com/thread/310434

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>

drivers/clk/mxs/clk-imx28.c

@@ -53,6 +53,7 @@ static void __iomem *clkctrl;
 #define BP_ENET_SLEEP		31
 #define BP_CLKSEQ_BYPASS_SAIF0	0
 #define BP_CLKSEQ_BYPASS_SSP0	3
+#define BP_CLKSEQ_BYPASS_SSP2	5
 #define BP_FRAC0_IO1FRAC	16
 #define BP_FRAC0_IO0FRAC	24
 
@@ -115,6 +116,12 @@ static void __init clk_misc_init(void)
 	 */
 	writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
 
+	/*
+	 * Source SSP2 clock from ref_xtal rather than ref_io
+	 * to prevent bit errors.
+	 */
+	writel_relaxed(0x1 << BP_CLKSEQ_BYPASS_SSP2, CLKSEQ + SET);
+
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
 	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.