i965: Rename *_OPCODE_FROM_DOUBLE to SHADER_OPCODE_FROM_DOUBLE

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Igalia · Jan 19, 2017 · 57e2a2d · 57e2a2d
1 parent b57dbd8
commit 57e2a2d
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Showing 10 changed files with 15 additions and 17 deletions.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1098,14 +1098,13 @@ enum opcode {
    VEC4_OPCODE_MOV_BYTES,
    VEC4_OPCODE_PACK_BYTES,
    VEC4_OPCODE_UNPACK_UNIFORM,
-   VEC4_OPCODE_FROM_DOUBLE,
+   SHADER_OPCODE_FROM_DOUBLE,
    FS_OPCODE_FROM_DOUBLE_INDIRECT,
    VEC4_OPCODE_TO_DOUBLE,
    VEC4_OPCODE_PICK_LOW_32BIT,
    VEC4_OPCODE_PICK_HIGH_32BIT,
    VEC4_OPCODE_SET_LOW_32BIT,
    VEC4_OPCODE_SET_HIGH_32BIT,
-   FS_OPCODE_FROM_DOUBLE,
 
    FS_OPCODE_DDX_COARSE,
    FS_OPCODE_DDX_FINE,

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4697,7 +4697,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
    case BRW_OPCODE_MAD:
    case BRW_OPCODE_LRP:
    case FS_OPCODE_PACK:
-   case FS_OPCODE_FROM_DOUBLE:
+   case SHADER_OPCODE_FROM_DOUBLE:
       return get_fpu_lowered_simd_width(devinfo, inst);
 
    case BRW_OPCODE_CMP: {

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -2112,7 +2112,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
          brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
          break;
 
-      case FS_OPCODE_FROM_DOUBLE:
+      case SHADER_OPCODE_FROM_DOUBLE:
          assert(src[0].type == BRW_REGISTER_TYPE_DF);
          assert(type_sz(dst.type) == 4);
          assert(dst.hstride == BRW_HORIZONTAL_STRIDE_2);

diff --git a/src/mesa/drivers/dri/i965/brw_fs_lower_d2x.cpp b/src/mesa/drivers/dri/i965/brw_fs_lower_d2x.cpp
@@ -62,7 +62,7 @@ fs_visitor::lower_d2x()
        */
       fs_reg temp = ibld.vgrf(inst->src[0].type, 1);
       fs_reg strided_temp = subscript(temp, inst->dst.type, 0);
-      ibld.emit(FS_OPCODE_FROM_DOUBLE, strided_temp, inst->src[0]);
+      ibld.emit(SHADER_OPCODE_FROM_DOUBLE, strided_temp, inst->src[0]);
       ibld.MOV(dst, strided_temp);
 
       inst->remove(block);

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -322,8 +322,7 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
       return "pack_bytes";
    case VEC4_OPCODE_UNPACK_UNIFORM:
       return "unpack_uniform";
-   case FS_OPCODE_FROM_DOUBLE:
-   case VEC4_OPCODE_FROM_DOUBLE:
+   case SHADER_OPCODE_FROM_DOUBLE:
       return "double_to_single";
    case VEC4_OPCODE_TO_DOUBLE:
       return "single_to_double";

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -259,7 +259,7 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
 {
    switch (opcode) {
    case SHADER_OPCODE_GEN4_SCRATCH_READ:
-   case VEC4_OPCODE_FROM_DOUBLE:
+   case SHADER_OPCODE_FROM_DOUBLE:
    case VEC4_OPCODE_TO_DOUBLE:
    case VEC4_OPCODE_PICK_LOW_32BIT:
    case VEC4_OPCODE_PICK_HIGH_32BIT:
@@ -520,7 +520,7 @@ vec4_visitor::opt_reduce_swizzle()
          break;
 
       case VEC4_OPCODE_TO_DOUBLE:
-      case VEC4_OPCODE_FROM_DOUBLE:
+      case SHADER_OPCODE_FROM_DOUBLE:
       case VEC4_OPCODE_PICK_LOW_32BIT:
       case VEC4_OPCODE_PICK_HIGH_32BIT:
       case VEC4_OPCODE_SET_LOW_32BIT:
@@ -2231,12 +2231,12 @@ vec4_visitor::lower_simd_width()
          linst->group = channel_offset;
          linst->size_written = size_written;
 
-         /* When splitting VEC4_OPCODE_FROM_DOUBLE on Ivybridge, the second part
+         /* When splitting SHADER_OPCODE_FROM_DOUBLE on Ivybridge, the second part
           * should use in a temporal register. Later we will move the values
           * to the second half of the original destination, so we get all the
           * results in the same register. We use d2f_pass to detect this case.
           */
-         bool d2f_pass = (inst->opcode == VEC4_OPCODE_FROM_DOUBLE && n > 0);
+         bool d2f_pass = (inst->opcode == SHADER_OPCODE_FROM_DOUBLE && n > 0);
          /* Compute split dst region */
          dst_reg dst;
          if (needs_temp || d2f_pass || inst_df_dst_null) {
@@ -2273,7 +2273,7 @@ vec4_visitor::lower_simd_width()
          if (inst_df_dst_null) {
             unsigned num_regs = DIV_ROUND_UP(lowered_width, type_sz(BRW_REGISTER_TYPE_F));
             d2f_dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)), BRW_REGISTER_TYPE_F);
-            vec4_instruction *d2f = new(mem_ctx) vec4_instruction(VEC4_OPCODE_FROM_DOUBLE, d2f_dst, src_reg(dst));
+            vec4_instruction *d2f = new(mem_ctx) vec4_instruction(SHADER_OPCODE_FROM_DOUBLE, d2f_dst, src_reg(dst));
             d2f->group = channel_offset;
             d2f->exec_size = lowered_width;
             d2f->size_written = lowered_width * type_sz(d2f_dst.type);
@@ -2328,7 +2328,7 @@ static bool
 is_align1_df(vec4_instruction *inst)
 {
    switch (inst->opcode) {
-   case VEC4_OPCODE_FROM_DOUBLE:
+   case SHADER_OPCODE_FROM_DOUBLE:
    case VEC4_OPCODE_TO_DOUBLE:
    case VEC4_OPCODE_PICK_LOW_32BIT:
    case VEC4_OPCODE_PICK_HIGH_32BIT:

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -293,7 +293,7 @@ static bool
 is_align1_opcode(unsigned opcode)
 {
    switch (opcode) {
-   case VEC4_OPCODE_FROM_DOUBLE:
+   case SHADER_OPCODE_FROM_DOUBLE:
    case VEC4_OPCODE_TO_DOUBLE:
    case VEC4_OPCODE_PICK_LOW_32BIT:
    case VEC4_OPCODE_PICK_HIGH_32BIT:

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1941,7 +1941,7 @@ generate_code(struct brw_codegen *p,
          break;
       }
 
-      case VEC4_OPCODE_FROM_DOUBLE: {
+      case SHADER_OPCODE_FROM_DOUBLE: {
          assert(type_sz(src[0].type) == 8);
          assert(type_sz(dst.type) == 4);
 

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1189,7 +1189,7 @@ vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src,
 
    dst_reg temp2 = dst_reg(this, glsl_type::dvec4_type);
    temp2 = retype(temp2, single_type);
-   emit(VEC4_OPCODE_FROM_DOUBLE, temp2, src_reg(temp))
+   emit(SHADER_OPCODE_FROM_DOUBLE, temp2, src_reg(temp))
       ->size_written = 2 * REG_SIZE;
 
    vec4_instruction *inst = emit(MOV(dst, src_reg(temp2)));

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -456,7 +456,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
           * dst we see a 32-bit destination and emit a scratch write that
           * allocates a single spill register.
           */
-         if (inst->opcode == VEC4_OPCODE_FROM_DOUBLE)
+         if (inst->opcode == SHADER_OPCODE_FROM_DOUBLE)
             no_spill[inst->dst.nr] = true;
 
          /* We can't spill registers that mix 32-bit and 64-bit access (that