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FspsUpd.h
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FspsUpd.h
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/** @file
@copyright
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#include <FspUpd.h>
#pragma pack(1)
#include <ConfigBlock/CpuConfigFspData.h>
///
/// Azalia Header structure
///
typedef struct {
UINT16 VendorId; ///< Codec Vendor ID
UINT16 DeviceId; ///< Codec Device ID
UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
} AZALIA_HEADER;
///
/// Audio Azalia Verb Table structure
///
typedef struct {
AZALIA_HEADER Header; ///< AZALIA PCH header
UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
} AUDIO_AZALIA_VERB_TABLE;
///
/// Refer to the definition of PCH_INT_PIN
///
typedef enum {
SiPchNoInt, ///< No Interrupt Pin
SiPchIntA,
SiPchIntB,
SiPchIntC,
SiPchIntD
} SI_PCH_INT_PIN;
///
/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
///
typedef struct {
UINT8 Device; ///< Device number
UINT8 Function; ///< Device function
UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
UINT8 Irq; ///< IRQ to be set for device.
} SI_PCH_DEVICE_INTERRUPT_CONFIG;
#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
/** Fsp S Configuration
**/
typedef struct {
/** Offset 0x0020 - Logo Pointer
Points to PEI Display Logo Image
**/
UINT32 LogoPtr;
/** Offset 0x0024 - Logo Size
Size of PEI Display Logo Image
**/
UINT32 LogoSize;
/** Offset 0x0028 - Graphics Configuration Ptr
Points to VBT
**/
UINT32 GraphicsConfigPtr;
/** Offset 0x002C - Enable Device 4
Enable/disable Device 4
$EN_DIS
**/
UINT8 Device4Enable;
/** Offset 0x002D - Enable Intel HD Audio (Azalia)
Enable/disable Azalia controller.
$EN_DIS
**/
UINT8 PchHdaEnable;
/** Offset 0x002E - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
/** Offset 0x002F - Select HDAudio IoBuffer Ownership
Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 /
I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link
owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4
of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports
own all the I/O buffers.
0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports
**/
UINT8 PchHdaIoBufferOwnership;
/** Offset 0x0030 - Enable CIO2 Controller
Enable/disable SKYCAM CIO2 Controller.
$EN_DIS
**/
UINT8 PchCio2Enable;
/** Offset 0x0031 - Enable eMMC Controller
Enable/disable eMMC Controller.
$EN_DIS
**/
UINT8 ScsEmmcEnabled;
/** Offset 0x0032 - Enable eMMC HS400 Mode
Enable eMMC HS400 Mode.
$EN_DIS
**/
UINT8 ScsEmmcHs400Enabled;
/** Offset 0x0033 - Enable SdCard Controller
Enable/disable SD Card Controller.
$EN_DIS
**/
UINT8 ScsSdCardEnabled;
/** Offset 0x0034 - Enable PCH ISH Controller
Enable/disable ISH Controller.
$EN_DIS
**/
UINT8 PchIshEnable;
/** Offset 0x0035 - Show SPI controller
Enable/disable to show SPI controller.
$EN_DIS
**/
UINT8 ShowSpiController;
/** Offset 0x0036 - Flash Configuration Lock Down
Enable/disable flash lock down. If platform decides to skip this programming, it
must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
$EN_DIS
**/
UINT8 SpiFlashCfgLockDown;
/** Offset 0x0037
**/
UINT8 UnusedUpdSpace0;
/** Offset 0x0038 - MicrocodeRegionBase
Memory Base of Microcode Updates
**/
UINT32 MicrocodeRegionBase;
/** Offset 0x003C - MicrocodeRegionSize
Size of Microcode Updates
**/
UINT32 MicrocodeRegionSize;
/** Offset 0x0040 - Turbo Mode
Enable/Disable Turbo mode. 0: disable, 1: enable
$EN_DIS
**/
UINT8 TurboMode;
/** Offset 0x0041 - Enable SATA SALP Support
Enable/disable SATA Aggressive Link Power Management.
$EN_DIS
**/
UINT8 SataSalpSupport;
/** Offset 0x0042 - Enable SATA ports
Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
and so on.
**/
UINT8 SataPortsEnable[8];
/** Offset 0x004A - Enable SATA DEVSLP Feature
Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
port, byte0 for port0, byte1 for port1, and so on.
**/
UINT8 SataPortsDevSlp[8];
/** Offset 0x0052 - Enable USB2 ports
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on.
**/
UINT8 PortUsb20Enable[16];
/** Offset 0x0062 - Enable USB3 ports
Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on.
**/
UINT8 PortUsb30Enable[10];
/** Offset 0x006C - Enable xDCI controller
Enable/disable to xDCI controller.
$EN_DIS
**/
UINT8 XdciEnable;
/** Offset 0x006D - Enable XHCI SSIC Enable
Enable/disable XHCI SSIC port.
$EN_DIS
**/
UINT8 SsicPortEnable;
/** Offset 0x006E
**/
UINT8 UnusedUpdSpace1;
/** Offset 0x006F - Number of DevIntConfig Entry
Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
must not be NULL.
**/
UINT8 NumOfDevIntConfig;
/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
**/
UINT32 DevIntConfigPtr;
/** Offset 0x0074 - Enable SerialIo Device Mode
0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable
SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode
respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
**/
UINT8 SerialIoDevMode[11];
/** Offset 0x007F - PIRQx to IRQx Map Config
PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
8259 PCI mode.
**/
UINT8 PxRcConfig[8];
/** Offset 0x0087 - Select GPIO IRQ Route
GPIO IRQ Select. The valid value is 14 or 15.
**/
UINT8 GpioIrqRoute;
/** Offset 0x0088 - Select SciIrqSelect
SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
**/
UINT8 SciIrqSelect;
/** Offset 0x0089 - Select TcoIrqSelect
TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
**/
UINT8 TcoIrqSelect;
/** Offset 0x008A - Enable/Disable Tco IRQ
Enable/disable TCO IRQ
$EN_DIS
**/
UINT8 TcoIrqEnable;
/** Offset 0x008B - PCH HDA Verb Table Entry Number
Number of Entries in Verb Table.
**/
UINT8 PchHdaVerbTableEntryNum;
/** Offset 0x008C - PCH HDA Verb Table Pointer
Pointer to Array of pointers to Verb Table.
**/
UINT32 PchHdaVerbTablePtr;
/** Offset 0x0090
**/
UINT8 UnusedUpdSpace2;
/** Offset 0x0091 - Enable SATA
Enable/disable SATA controller.
$EN_DIS
**/
UINT8 SataEnable;
/** Offset 0x0092 - SATA Mode
Select SATA controller working mode.
0:AHCI, 1:RAID
**/
UINT8 SataMode;
/** Offset 0x0093 - USB Per Port HS Preemphasis Bias
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
**/
UINT8 Usb2AfePetxiset[16];
/** Offset 0x00A3 - USB Per Port HS Transmitter Bias
USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
**/
UINT8 Usb2AfeTxiset[16];
/** Offset 0x00B3 - USB Per Port HS Transmitter Emphasis
USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
**/
UINT8 Usb2AfePredeemp[16];
/** Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis
USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
One byte for each port.
**/
UINT8 Usb2AfePehalfbit[16];
/** Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDeEmphEnable[10];
/** Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
<b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
**/
UINT8 Usb3HsioTxDeEmph[10];
/** Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmpEnable[10];
/** Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment
USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
= 00h</b>. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmp[10];
/** Offset 0x00FB - Enable LAN
Enable/disable LAN controller.
$EN_DIS
**/
UINT8 PchLanEnable;
/** Offset 0x00FC - Delay USB PDO Programming
Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0:
disable, 1: enable
$EN_DIS
**/
UINT8 DelayUsbPdoProgramming;
/** Offset 0x00FD
**/
UINT8 UnusedUpdSpace3[23];
/** Offset 0x0114 - Enable PCIE RP CLKREQ Support
Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for
each port, byte0 for port1, byte1 for port2, and so on.
**/
UINT8 PcieRpClkReqSupport[24];
/** Offset 0x012C - Configure CLKREQ Number
Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can
be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
**/
UINT8 PcieRpClkReqNumber[24];
/** Offset 0x0144
**/
UINT8 UnusedUpdSpace4[5];
/** Offset 0x0149 - HECI3 state
The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
0: disable, 1: enable
$EN_DIS
**/
UINT8 Heci3Enabled;
/** Offset 0x014A
**/
UINT8 UnusedUpdSpace5[9];
/** Offset 0x0153 - AMT Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
$EN_DIS
**/
UINT8 AmtEnabled;
/** Offset 0x0154 - WatchDog Timer Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
$EN_DIS
**/
UINT8 WatchDog;
/** Offset 0x0155 - ASF Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
$EN_DIS
**/
UINT8 AsfEnabled;
/** Offset 0x0156 - Manageability Mode set by Mebx
Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
$EN_DIS
**/
UINT8 ManageabilityMode;
/** Offset 0x0157 - PET Progress
Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
PET Events.
$EN_DIS
**/
UINT8 FwProgress;
/** Offset 0x0158 - OS Timer
16 bits Value, Set OS watchdog timer.
$EN_DIS
**/
UINT16 WatchDogTimerOs;
/** Offset 0x015A - BIOS Timer
16 bits Value, Set BIOS watchdog timer.
$EN_DIS
**/
UINT16 WatchDogTimerBios;
/** Offset 0x015C - SOL Switch
Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
$EN_DIS
**/
UINT8 AmtSolEnabled;
/** Offset 0x015D - Configure CLKSRC Number
Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid
clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for
port1, byte1 for port2, and so on.
**/
UINT8 PcieRpClkSrcNumber[24];
/** Offset 0x0175 - Force Disable clock
Disables clock even if link is inactive default value is 0
**/
UINT8 PcieRpForceClkDisableWhenRpDisable[24];
/** Offset 0x018D
**/
UINT8 UnusedUpdSpace6[115];
/** Offset 0x0200 - Subsystem Vendor ID for SA devices
Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086
**/
UINT16 DefaultSvid;
/** Offset 0x0202 - Subsystem Device ID for SA devices
Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015
**/
UINT16 DefaultSid;
/** Offset 0x0204 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
/** Offset 0x0205 - DMI ASPM
0=Disable, 2(Default)=L1
0:Disable, 2:L1
**/
UINT8 DmiAspm;
/** Offset 0x0206 - PCIe Physical Slot Number per root port
Physical Slot Number per root port
**/
UINT16 PegPhysicalSlotNumber[3];
/** Offset 0x020C - PCIe DeEmphasis control per root port
0: -6dB, 1(Default): -3.5dB
0:-6dB, 1:-3.5dB
**/
UINT8 PegDeEmphasis[3];
/** Offset 0x020F - PCIe Slot Power Limit value per root port
Slot power limit value per root port
**/
UINT8 PegSlotPowerLimitValue[3];
/** Offset 0x0212 - PCIe Slot Power Limit scale per root port
Slot power limit scale per root port
0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
**/
UINT8 PegSlotPowerLimitScale[3];
/** Offset 0x0215 - Enable/Disable PavpEnable
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
$EN_DIS
**/
UINT8 PavpEnable;
/** Offset 0x0216 - CdClock Frequency selection
0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz
0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
**/
UINT8 CdClock;
/** Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit
Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
/** Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM)
Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM)
$EN_DIS
**/
UINT8 SaImguEnable;
/** Offset 0x0219 - Enable or disable GMM device
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 GmmEnable;
/** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table
0=Disable/Clear, 1=Enable/Set
$EN_DIS
**/
UINT8 X2ApicOptOut;
/** Offset 0x021B
**/
UINT8 UnusedUpdSpace7[1];
/** Offset 0x021C - Base addresses for VT-d function MMIO access
Base addresses for VT-d MMIO access per VT-d engine
**/
UINT32 VtdBaseAddress[2];
/** Offset 0x0224 - Program GT Chicken bits
Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]
**/
UINT8 ProgramGtChickenBits;
/** Offset 0x0225
**/
UINT8 UnusedUpdSpace8[18];
/** Offset 0x0237 - SaPostMemProductionRsvd
Reserved for SA Post-Mem Production
$EN_DIS
**/
UINT8 SaPostMemProductionRsvd[15];
/** Offset 0x0246
**/
UINT8 UnusedUpdSpace9[8];
/** Offset 0x024E - Power State 3 enable/disable
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
For all VR Indexes
**/
UINT8 Psi3Enable[5];
/** Offset 0x0253 - Power State 4 enable/disable
PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
all VR Indexes
**/
UINT8 Psi4Enable[5];
/** Offset 0x0258 - Imon slope correction
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
**/
UINT8 ImonSlope[5];
/** Offset 0x025D - Imon offset correction
PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
**/
UINT8 ImonOffset[5];
/** Offset 0x0262 - Enable/Disable BIOS configuration of VR
Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
**/
UINT8 VrConfigEnable[5];
/** Offset 0x0267 - Thermal Design Current enable/disable
PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
Enable.For all VR Indexes
**/
UINT8 TdcEnable[5];
/** Offset 0x026C - HECI3 state
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
, 8 - 8ms , 10 - 10ms.For all VR Indexe
**/
UINT8 TdcTimeWindow[5];
/** Offset 0x0271 - Thermal Design Current Lock
PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
all VR Indexes
**/
UINT8 TdcLock[5];
/** Offset 0x0276 - Platform Psys slope correction
PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
1/100 increment values. Range is 0-200. 125 = 1.25
**/
UINT8 PsysSlope;
/** Offset 0x0277 - Platform Psys offset correction
PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
Range 0-255. Value of 100 = 100/4 = 25 offset
**/
UINT8 PsysOffset;
/** Offset 0x0278 - Acoustic Noise Mitigation feature
Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
$EN_DIS
**/
UINT8 AcousticNoiseMitigation;
/** Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableIa;
/** Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain
Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForIa;
/** Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain
Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForGt;
/** Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain
Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForSa;
/** Offset 0x027D
**/
UINT8 UnusedUpdSpace10[9];
/** Offset 0x0286 - Thermal Design Current current limit
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
**/
UINT16 TdcPowerLimit[5];
/** Offset 0x0290 - CPU VR Power Delivery Design
Used to communicate the power delivery design capability of the board. This value
is an enum of the available power delivery segments that are defined in the Platform
Design Guide.
**/
UINT32 VrPowerDeliveryDesign;
/** Offset 0x0294
**/
UINT8 UnusedUpdSpace11[4];
/** Offset 0x0298 - AcLoadline
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
**/
UINT16 AcLoadline[5];
/** Offset 0x02A2 - DcLoadline
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
**/
UINT16 DcLoadline[5];
/** Offset 0x02AC - Power State 1 Threshold current
PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is
0-128A. Default Value = 20A.
**/
UINT16 Psi1Threshold[5];
/** Offset 0x02B6 - Power State 2 Threshold current
PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is
0-128A. Default Value = 5A.
**/
UINT16 Psi2Threshold[5];
/** Offset 0x02C0 - Power State 3 Threshold current
PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is
0-128A. Default Value = 1A.
**/
UINT16 Psi3Threshold[5];
/** Offset 0x02CA - Icc Max limit
PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
**/
UINT16 IccMax[5];
/** Offset 0x02D4 - VR Voltage Limit
PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
**/
UINT16 VrVoltageLimit[5];
/** Offset 0x02DE
**/
UINT8 UnusedUpdSpace12;
/** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableGt;
/** Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableSa;
/** Offset 0x02E1
**/
UINT8 UnusedUpdSpace13;
/** Offset 0x02E2 - Enable VR specific mailbox command
VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
command sent for PS4 exit issue. 11b - Reserved.
$EN_DIS
**/
UINT8 SendVrMbxCmd;
/** Offset 0x02E3 - Select VR specific mailbox command to send
VR specific mailbox commands. <b>000b - no VR specific command sent.</b> 001b -
VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific
command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue.
**/
UINT8 SendVrMbxCmd1;
/** Offset 0x02E4 - CpuS3ResumeMtrrData
Pointer to CPU S3 Resume MTRR Data
**/
UINT32 CpuS3ResumeMtrrData;
/** Offset 0x02E8 - Cpu Configuration
Cpu Configuration data.
**/
CPU_CONFIG_FSP_DATA CpuConfig;
/** Offset 0x02F0 - MicrocodePatchAddress
Pointer to microcode patch that is suitable for this processor.
0:Disable, 1:Enable
**/
UINT64 MicrocodePatchAddress;
/** Offset 0x02F8 - CpuS3ResumeMtrrDataSize
Size of S3 resume MTRR data.
**/
UINT16 CpuS3ResumeMtrrDataSize;
/** Offset 0x02FA
**/
UINT8 UnusedUpdSpace14;
/** Offset 0x02FB - Enable SkyCam PortA Termination override
Enable/disable PortA Termination override.
$EN_DIS
**/
UINT8 PchSkyCamPortATermOvrEnable;
/** Offset 0x02FC - Enable SkyCam PortB Termination override
Enable/disable PortB Termination override.
$EN_DIS
**/
UINT8 PchSkyCamPortBTermOvrEnable;
/** Offset 0x02FD - Enable SkyCam PortC Termination override
Enable/disable PortC Termination override.
$EN_DIS
**/
UINT8 PchSkyCamPortCTermOvrEnable;
/** Offset 0x02FE - Enable SkyCam PortD Termination override
Enable/disable PortD Termination override.
$EN_DIS
**/
UINT8 PchSkyCamPortDTermOvrEnable;
/** Offset 0x02FF - Enable SkyCam PortA Clk Trim
Enable/disable PortA Clk Trim.
$EN_DIS
**/
UINT8 PchSkyCamPortATrimEnable;
/** Offset 0x0300 - Enable SkyCam PortB Clk Trim
Enable/disable PortB Clk Trim.
$EN_DIS
**/
UINT8 PchSkyCamPortBTrimEnable;
/** Offset 0x0301 - Enable SkyCam PortC Clk Trim
Enable/disable PortC Clk Trim.
$EN_DIS
**/
UINT8 PchSkyCamPortCTrimEnable;
/** Offset 0x0302 - Enable SkyCam PortD Clk Trim
Enable/disable PortD Clk Trim.
$EN_DIS
**/
UINT8 PchSkyCamPortDTrimEnable;
/** Offset 0x0303 - Enable SkyCam PortA Ctle
Enable/disable PortA Ctle.
$EN_DIS
**/
UINT8 PchSkyCamPortACtleEnable;
/** Offset 0x0304 - Enable SkyCam PortB Ctle
Enable/disable PortB Ctle.
$EN_DIS
**/
UINT8 PchSkyCamPortBCtleEnable;
/** Offset 0x0305 - Enable SkyCam PortCD Ctle
Enable/disable PortCD Ctle.
$EN_DIS
**/
UINT8 PchSkyCamPortCDCtleEnable;
/** Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value
Enable/disable PortA Ctle Cap Value.
**/
UINT8 PchSkyCamPortACtleCapValue;
/** Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value
Enable/disable PortB Ctle Cap Value.
**/
UINT8 PchSkyCamPortBCtleCapValue;
/** Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value
Enable/disable PortCD Ctle Cap Value.
**/
UINT8 PchSkyCamPortCDCtleCapValue;
/** Offset 0x0309 - Enable SkyCam PortA Ctle Res Value
Enable/disable PortA Ctle Res Value.
**/
UINT8 PchSkyCamPortACtleResValue;
/** Offset 0x030A - Enable SkyCam PortB Ctle Res Value
Enable/disable PortB Ctle Res Value.
**/
UINT8 PchSkyCamPortBCtleResValue;
/** Offset 0x030B - Enable SkyCam PortCD Ctle Res Value
Enable/disable PortCD Ctle Res Value.
**/
UINT8 PchSkyCamPortCDCtleResValue;
/** Offset 0x030C - Enable SkyCam PortA Clk Trim Value
Enable/disable PortA Clk Trim Value.
**/
UINT8 PchSkyCamPortAClkTrimValue;
/** Offset 0x030D - Enable SkyCam PortB Clk Trim Value
Enable/disable PortB Clk Trim Value.
**/
UINT8 PchSkyCamPortBClkTrimValue;
/** Offset 0x030E - Enable SkyCam PortC Clk Trim Value
Enable/disable PortC Clk Trim Value.
**/
UINT8 PchSkyCamPortCClkTrimValue;
/** Offset 0x030F - Enable SkyCam PortD Clk Trim Value
Enable/disable PortD Clk Trim Value.
**/
UINT8 PchSkyCamPortDClkTrimValue;
/** Offset 0x0310 - Enable SkyCam Port A Data Trim Value
Enable/disable Port A Data Trim Value.
**/
UINT16 PchSkyCamPortADataTrimValue;
/** Offset 0x0312 - Enable SkyCam Port B Data Trim Value
Enable/disable Port B Data Trim Value.
**/
UINT16 PchSkyCamPortBDataTrimValue;
/** Offset 0x0314 - Enable SkyCam C/D Data Trim Value
Enable/disable C/D Data Trim Value.
**/
UINT16 PchSkyCamPortCDDataTrimValue;
/** Offset 0x0316 - Enable DMI ASPM
ASPM on PCH side of the DMI Link.
$EN_DIS
**/
UINT8 PchDmiAspm;
/** Offset 0x0317 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
/** Offset 0x0318 - PCH Flash Protection Ranges Write Enble
Write or erase is blocked by hardware.
**/
UINT8 PchWriteProtectionEnable[5];
/** Offset 0x031D - PCH Flash Protection Ranges Read Enble
Read is blocked by hardware.
**/
UINT8 PchReadProtectionEnable[5];
/** Offset 0x0322 - PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
/** Offset 0x032C - PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
/** Offset 0x0336 - Enable Pme
Enable Azalia wake-on-ring.
$EN_DIS
**/
UINT8 PchHdaPme;
/** Offset 0x0337 - IO Buffer Voltage
I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
**/
UINT8 PchHdaIoBufferVoltage;
/** Offset 0x0338 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1.
**/
UINT8 PchHdaVcType;
/** Offset 0x0339 - HD Audio Link Frequency
HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz.
**/
UINT8 PchHdaLinkFrequency;
/** Offset 0x033A - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
**/
UINT8 PchHdaIDispLinkFrequency;
/** Offset 0x033B - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
**/
UINT8 PchHdaIDispLinkTmode;
/** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system
0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
driver or SST driver supported).
$EN_DIS
**/
UINT8 PchHdaDspUaaCompliance;
/** Offset 0x033D - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS