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41 Open 62 Closed
41 Open 62 Closed
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Issues list

wrong file headers in a public code
#108 opened Jul 12, 2024 by ndhaller
ADL-N Headers have wrong address in headers
#107 opened Jul 8, 2024 by Sean-StarLabs
Meteor Lake Client FSP
#106 opened May 28, 2024 by macpijan
Meteor Lake is missing header files
#103 opened Mar 7, 2024 by felixsinger
Missing important FSP Hob structs header files for EagleStreamFspBinPkg
#102 opened Feb 8, 2024 by johnnylinwiwynn
13
UP3 Tigerlake Based Circuit Board: CRC For DIMM Fails. So Fast Boot Never Occurs!
#101 opened Feb 5, 2024 by sshivsh
14
ApolloLake FSP MR10 problem (PreMemSa)
#86 opened Aug 11, 2022 by xabar
FSP spec: debug registers
#85 opened May 30, 2022 by ArthurHeymans
1
SMBIOS memory information missing on Denverton
#81 opened Feb 28, 2022 by mothacehe
1
Missing Documentation: TGL DdrMemoryDown
#79 opened Jan 11, 2022 by c0d3z3r0
SMBIOS Cache Information Hob - Coffeelake
#75 opened Nov 15, 2021 by leorsa
FSP Package for Jasperlake boards not available
#74 opened Nov 11, 2021 by MrChromebox
3
FSP Package for Geminilake boards not available
#73 opened Nov 11, 2021 by MrChromebox
1
Need to display BMC IP address in EDK II Server BIOS
#72 opened Nov 10, 2021 by jdhanasekar
FSP display incorrect FSP spec revision (Elkhart Lake FSP)
#70 opened Jul 26, 2021 by swong23
Apollo Lake MR9 FSP will set SMI Lock no matter what value I passed from bootloader
#69 opened Jul 16, 2021 by seattlezhu
7
TigerLake FSP problems with Tiger Lake UP3 RVP
#63 opened Feb 11, 2021 by miczyg1
9
KabylakeFspBinPkg may violate TCG PTP specification
#62 opened Jan 5, 2021 by benjamindoron
x86_64 firmware support: Use fixed size struct elements to support cross arch firmwares
#59 opened Dec 9, 2020 by PatrickRudolph
1
Intermittent failure on APL platform with message "HeciInitialize HECIMBAR 0XD3708000"
#58 opened Oct 20, 2020 by shehamb
2
ApolloLakeFspBinPkg[MR6] FSP-M PrimaryVideoAdaptor UPD possible values are wrong
#57 opened Oct 9, 2020 by Th3Fanbus
ApolloLakeFspBinPkg[MR6] configures PCIe Root Port's DCTL[MPS]
#56 opened Oct 9, 2020 by n-huber
ApolloLakeFspBinPkg[MR6] broken MPS with PcieRpHotPlug = 1
#55 opened Oct 9, 2020 by n-huber
Kaby Lake: FSP memory init return erros
#54 opened Jul 9, 2020 by miczyg1
FSP DRAM configuration for memory with only single channel
#52 opened Jul 6, 2020 by shehamb
4
ProTip! Updated in the last three days: updated:>2024-07-10.