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main.stanza
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main.stanza
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; Generated by JITX {JITX-VERSION}
#use-added-syntax(jitx)
defpackage main :
import core
import jitx
import jitx/commands
import ocdb/utils/generic-components
import helpers
; Define the shape/size of the board
val board-shape = RoundedRectangle(30.0, 18.5, 0.25)
; Module to run as a design
pcb-module my-design :
; define some pins/ports
port gnd
port power-5v
port signal
; Create a 10k resistor component
res-strap(power-5v, signal, 10.0e3)
; Write the board version on silkscreen
inst version-label : ocdb/artwork/board-text/version-silkscreen("Version 0.0")
place(version-label) at loc(0.0, height(board-shape) / 2.0 - 1.0) on Bottom
; Set the design name - a directory with this name will be generated under the "designs" directory
; the board - a Board object
; [optional] rules - the PCB design rules (if not givn default rules will be used)
; [optional] vendors - Strings or AuthorizedVendors (if not give default vendors will be used)
; [optional] quantity - Minimum stock quantity the vendor should carry (if not give default quantity will be used)
setup-design(
"jitx-design",
ocdb/utils/defaults/default-board(ocdb/manufacturers/stackups/jlcpcb-jlc2313, board-shape)
)
; Set the schematic sheet size
set-paper(ANSI-A)
; Set the top level module (the module to be compile into a schematic and PCB)
set-main-module(my-design)
; Use any helper function from helpers.stanza here
; run-check-on-design(my-design)
; View the results
view-design-explorer()
view-bom(BOM-STD)
view-board()
view-schematic()