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hieth.c
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hieth.c
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/clk.h>
#include <linux/circ_buf.h>
#include <linux/hikapi.h>
#include <linux/netdevice.h>
#include "hieth.h"
#include "mdio.h"
#include "hieth_dbg.h"
/*----------------------------Global variable-------------------------------*/
struct hieth_phy_param_s hieth_phy_param[HIETH_MAX_PORT];
/*----------------------------Local variable-------------------------------*/
static struct net_device *hieth_devs_save[HIETH_MAX_PORT] = { NULL, NULL };
static struct hieth_netdev_priv hieth_priv;
/* real port count */
static int hieth_real_port_cnt;
/* default, eth enable */
static bool hieth_disable;
/* autoeee, enabled by dts */
static bool hieth_enable_autoeee;
static int __init hieth_noeth(char *str)
{
hieth_disable = true;
return 0;
}
early_param("noeth", hieth_noeth);
#include "pm.c"
static int hieth_hw_set_macaddress(struct hieth_netdev_priv *priv,
unsigned char *mac)
{
u32 reg;
if (priv->port == HIETH_PORT_1) {
reg = hieth_readl(priv->glb_base, HIETH_GLB_DN_HOSTMAC_ENA);
reg |= HIETH_GLB_DN_HOSTMAC_ENA_BIT;
hieth_writel(priv->glb_base, reg, HIETH_GLB_DN_HOSTMAC_ENA);
}
reg = mac[1] | (mac[0] << 8);
if (priv->port == HIETH_PORT_0)
hieth_writel(priv->glb_base, reg, HIETH_GLB_HOSTMAC_H16);
else
hieth_writel(priv->glb_base, reg, HIETH_GLB_DN_HOSTMAC_H16);
reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
if (priv->port == HIETH_PORT_0)
hieth_writel(priv->glb_base, reg, HIETH_GLB_HOSTMAC_L32);
else
hieth_writel(priv->glb_base, reg, HIETH_GLB_DN_HOSTMAC_L32);
return 0;
}
static void hieth_irq_enable(struct hieth_netdev_priv *priv, int irqs)
{
u32 val;
local_lock(priv);
val = hieth_readl(priv->glb_base, HIETH_GLB_IRQ_ENA);
hieth_writel(priv->glb_base, val | irqs, HIETH_GLB_IRQ_ENA);
local_unlock(priv);
}
static void hieth_irq_disable(struct hieth_netdev_priv *priv, int irqs)
{
u32 val;
local_lock(priv);
val = hieth_readl(priv->glb_base, HIETH_GLB_IRQ_ENA);
hieth_writel(priv->glb_base, val & (~irqs), HIETH_GLB_IRQ_ENA);
local_unlock(priv);
}
static void hieth_clear_irqstatus(struct hieth_netdev_priv *priv, int irqs)
{
local_lock(priv);
hieth_writel(priv->glb_base, irqs, HIETH_GLB_IRQ_RAW);
local_unlock(priv);
}
static int hieth_port_reset(struct hieth_netdev_priv *priv)
{
u32 rst_bit = 0;
u32 val;
if (hieth_real_port_cnt == 1)
rst_bit = HIETH_GLB_SOFT_RESET_ALL;
else {
if (priv->port == HIETH_PORT_0) {
rst_bit |= HIETH_GLB_SOFT_RESET_P0;
} else if (priv->port == HIETH_PORT_1) {
rst_bit |= HIETH_GLB_SOFT_RESET_P1;
} else {
BUG();
}
}
val = hieth_readl(priv->glb_base, HIETH_GLB_SOFT_RESET);
val |= rst_bit;
hieth_writel(priv->glb_base, val, HIETH_GLB_SOFT_RESET);
usleep_range(1000, 10000);
val &= ~rst_bit;
hieth_writel(priv->glb_base, val, HIETH_GLB_SOFT_RESET);
usleep_range(1000, 10000);
val |= rst_bit;
hieth_writel(priv->glb_base, val, HIETH_GLB_SOFT_RESET);
usleep_range(1000, 10000);
val &= ~rst_bit;
hieth_writel(priv->glb_base, val, HIETH_GLB_SOFT_RESET);
return 0;
}
static void hieth_port_init(struct hieth_netdev_priv *priv)
{
u32 val;
int phy_intf = (priv->phy_mode == PHY_INTERFACE_MODE_MII ?
HIETH_P_MAC_PORTSEL_MII : HIETH_P_MAC_PORTSEL_RMII);
/* set little endian */
val = hieth_readl(priv->glb_base, HIETH_GLB_ENDIAN_MOD);
val |= HIETH_GLB_ENDIAN_MOD_IN;
val |= HIETH_GLB_ENDIAN_MOD_OUT;
hieth_writel(priv->glb_base, val, HIETH_GLB_ENDIAN_MOD);
/* set stat ctrl to cpuset, and MII or RMII mode */
hieth_writel(priv->port_base, phy_intf | HIETH_P_MAC_PORTSEL_STAT_CPU,
HIETH_P_MAC_PORTSEL);
/*clear all interrupt status */
hieth_clear_irqstatus(priv, UD_BIT_NAME(HIETH_GLB_IRQ_ENA_BIT));
/*disable interrupts */
hieth_irq_disable(priv, UD_BIT_NAME(HIETH_GLB_IRQ_ENA_BIT) |
UD_BIT_NAME(HIETH_GLB_IRQ_ENA_IEN));
/* disable vlan, enable UpEther<->CPU */
val = hieth_readl(priv->glb_base, HIETH_GLB_FWCTRL);
val &= ~HIETH_GLB_FWCTRL_VLAN_ENABLE;
val |= UD_BIT_NAME(HIETH_GLB_FWCTRL_FW2CPU_ENA);
val &= ~(UD_BIT_NAME(HIETH_GLB_FWCTRL_FWALL2CPU));
hieth_writel(priv->glb_base, val, HIETH_GLB_FWCTRL);
val = hieth_readl(priv->glb_base, HIETH_GLB_MACTCTRL);
val |= UD_BIT_NAME(HIETH_GLB_MACTCTRL_BROAD2CPU);
val |= UD_BIT_NAME(HIETH_GLB_MACTCTRL_MACT_ENA);
hieth_writel(priv->glb_base, val, HIETH_GLB_MACTCTRL);
/* set pre count limit */
val = hieth_readl(priv->port_base, HIETH_P_MAC_TX_IPGCTRL);
val &= ~HIETH_P_MAC_TX_IPGCTRL_PRE_CNT_LMT_MSK;
val |= 0;
hieth_writel(priv->port_base, val, HIETH_P_MAC_TX_IPGCTRL);
/* set max receive length */
val = hieth_readl(priv->port_base, HIETH_P_MAC_SET);
val &= ~HIETH_P_MAC_SET_LEN_MAX_MSK;
val |= HIETH_P_MAC_SET_LEN_MAX(HIETH_MAX_RCV_LEN);
hieth_writel(priv->port_base, val, HIETH_P_MAC_SET);
}
static void hieth_set_hwq_depth(struct hieth_netdev_priv *priv)
{
u32 val;
val = hieth_readl(priv->port_base, HIETH_P_GLB_QLEN_SET);
val &= ~HIETH_P_GLB_QLEN_SET_TXQ_DEP_MSK;
val |= HIETH_P_GLB_QLEN_SET_TXQ_DEP(priv->depth.hw_xmitq);
val &= ~HIETH_P_GLB_QLEN_SET_RXQ_DEP_MSK;
val |= HIETH_P_GLB_QLEN_SET_RXQ_DEP(HIETH_MAX_QUEUE_DEPTH -
priv->depth.hw_xmitq);
hieth_writel(priv->port_base, val, HIETH_P_GLB_QLEN_SET);
}
static inline int hieth_hw_xmitq_ready(struct hieth_netdev_priv *priv)
{
int ret;
ret = hieth_readl(priv->port_base, HIETH_P_GLB_RO_QUEUE_STAT);
ret &= HIETH_P_GLB_RO_QUEUE_STAT_XMITQ_RDY_MSK;
return ret;
}
static int hieth_xmit_release_skb(struct hieth_netdev_priv *priv)
{
u32 val;
int ret = 0;
struct sk_buff *skb;
u32 tx_comp = 0;
struct net_device *ndev = hieth_devs_save[priv->port];
local_lock(priv);
val = hieth_readl(priv->port_base, HIETH_P_GLB_RO_QUEUE_STAT) &
HIETH_P_GLB_RO_QUEUE_STAT_XMITQ_CNT_INUSE_MSK;
while (val < priv->tx_hw_cnt) {
skb = skb_dequeue(&priv->tx_hw);
if (!skb) {
pr_err("hw_xmitq_cnt_inuse=%d, tx_hw_cnt=%d\n",
val, priv->tx_hw_cnt);
BUG();
ret = -1;
goto error_exit;
}
dev_kfree_skb_any(skb);
priv->tx_hw_cnt--;
tx_comp++;
val = hieth_readl(priv->port_base, HIETH_P_GLB_RO_QUEUE_STAT) &
HIETH_P_GLB_RO_QUEUE_STAT_XMITQ_CNT_INUSE_MSK;
}
if (tx_comp)
netif_wake_queue(ndev);
error_exit:
local_unlock(priv);
return ret;
}
static void hieth_xmit_real_send(struct hieth_netdev_priv *priv,
struct sk_buff *skb)
{
u32 val;
local_lock(priv);
/* for recalc CRC, 4 bytes more is needed */
hieth_writel(priv->port_base, virt_to_phys(skb->data),
HIETH_P_GLB_EQ_ADDR);
val = hieth_readl(priv->port_base, HIETH_P_GLB_EQFRM_LEN);
val &= ~HIETH_P_GLB_EQFRM_TXINQ_LEN_MSK;
val |= skb->len + 4;
hieth_writel(priv->port_base, skb->len + 4, HIETH_P_GLB_EQFRM_LEN);
skb_queue_tail(&priv->tx_hw, skb);
priv->tx_hw_cnt++;
local_unlock(priv);
}
static __maybe_unused struct sk_buff *hieth_platdev_alloc_skb(struct hieth_netdev_priv *priv)
{
struct sk_buff *skb;
int i;
skb = priv->rx_pool.sk_pool[priv->rx_pool.next_free_skb++];
if (priv->rx_pool.next_free_skb == CONFIG_HIETH_MAX_RX_POOLS)
priv->rx_pool.next_free_skb = 0;
/*current skb is used by kernel or other process,find another skb*/
if (skb_shared(skb) || (atomic_read(&(skb_shinfo(skb)->dataref)) > 1)) {
for (i = 0; i < CONFIG_HIETH_MAX_RX_POOLS; i++) {
skb = priv->rx_pool.sk_pool[priv->
rx_pool.next_free_skb++];
if (priv->rx_pool.next_free_skb ==
CONFIG_HIETH_MAX_RX_POOLS)
priv->rx_pool.next_free_skb = 0;
if ((skb_shared(skb) == 0) &&
(atomic_read(&(skb_shinfo(skb)->dataref)) <= 1))
break;
}
if (i == CONFIG_HIETH_MAX_RX_POOLS) {
priv->stat.rx_pool_dry_times++;
pr_debug("%ld: no free skb\n",
priv->stat.rx_pool_dry_times);
skb = dev_alloc_skb(SKB_SIZE);
return skb;
}
}
memset(skb, 0, offsetof(struct sk_buff, tail));
skb->data = skb->head;
skb_reset_tail_pointer(skb);
WARN(skb->end != (skb->tail + SKB_DATA_ALIGN(SKB_SIZE + NET_SKB_PAD)),
"head=%p, tail=%x, end=%x\n", skb->head, (unsigned int)skb->tail,
(unsigned int)skb->end);
skb->end = skb->tail + SKB_DATA_ALIGN(SKB_SIZE + NET_SKB_PAD);
skb_reserve(skb, NET_SKB_PAD);
skb->len = 0;
skb->data_len = 0;
skb->cloned = 0;
atomic_inc(&skb->users);
return skb;
}
static int hieth_feed_hw(struct hieth_netdev_priv *priv)
{
struct sk_buff *skb;
int cnt = 0;
int rx_head_len;
/* if skb occupied too much, then do not alloc any more. */
rx_head_len = skb_queue_len(&priv->rx_head);
if (rx_head_len > HIETH_MAX_RX_HEAD_LEN)
return 0;
local_lock(priv);
while (hieth_readl(priv->port_base, HIETH_P_GLB_RO_QUEUE_STAT) &
HIETH_P_GLB_RO_QUEUE_STAT_RECVQ_RDY_MSK) {
skb = dev_alloc_skb(SKB_SIZE);
if (!skb)
break;
dma_map_single(priv->dev, skb->data, HIETH_MAX_FRAME_SIZE,
DMA_FROM_DEVICE);
hieth_writel(priv->port_base, virt_to_phys(skb->data + 2),
HIETH_P_GLB_IQ_ADDR);
skb_queue_tail(&priv->rx_hw, skb);
cnt++;
}
local_unlock(priv);
return cnt;
}
int hieth_recv_budget(struct hieth_netdev_priv *priv, int budget)
{
struct sk_buff *skb;
uint32_t rlen;
int cnt = 0;
local_lock(priv);
while ((hieth_readl(priv->glb_base, HIETH_GLB_IRQ_RAW) &
(UD_BIT_NAME(HIETH_GLB_IRQ_INT_RX_RDY)))) {
if (budget > 0 && cnt >= budget)
break;
rlen = hieth_readl(priv->port_base, HIETH_P_GLB_RO_IQFRM_DES);
rlen &= HIETH_P_GLB_RO_IQFRM_DES_FDIN_LEN_MSK;
rlen -= 4; /* remove FCS 4Bytes */
/* hw set rx pkg finish */
hieth_writel(priv->glb_base,
UD_BIT_NAME(HIETH_GLB_IRQ_INT_RX_RDY),
HIETH_GLB_IRQ_RAW);
skb = skb_dequeue(&priv->rx_hw);
if (!skb) {
pr_err("chip told us to receive pkg,"
"but no more can be received!\n");
BUG();
break;
}
dma_map_single(priv->dev, skb->data, HIETH_MAX_FRAME_SIZE,
DMA_FROM_DEVICE);
skb_reserve(skb, 2);
skb_put(skb, rlen);
skb_queue_tail(&priv->rx_head, skb);
cnt++;
}
local_unlock(priv);
/* fill hardware receive queue again */
hieth_feed_hw(priv);
return cnt;
}
static void hieth_adjust_link(struct net_device *dev)
{
int stat = 0;
struct hieth_netdev_priv *priv = netdev_priv(dev);
stat |= (priv->phy->link) ? HIETH_P_MAC_PORTSET_LINKED : 0;
stat |= (priv->phy->duplex == DUPLEX_FULL) ?
HIETH_P_MAC_PORTSET_DUP_FULL : 0;
stat |= (priv->phy->speed == SPEED_100) ?
HIETH_P_MAC_PORTSET_SPD_100M : 0;
/* The following expression
* "(stat | priv->link_stat) & HIETH_P_MAC_PORTSET_LINKED"
* means we only consider three link status change as valid:
* 1) down -> up;
* 2) up -> down;
* 3) up -> up; (maybe the link speed and duplex changed)
* We will ignore the "down -> down" condition.
*/
if ((stat != priv->link_stat) &&
((stat | priv->link_stat) & HIETH_P_MAC_PORTSET_LINKED)) {
hieth_writel(priv->port_base, stat, HIETH_P_MAC_PORTSET);
phy_print_status(priv->phy);
priv->link_stat = stat;
if (hieth_enable_autoeee)
hieth_autoeee_init(priv, stat);
}
}
static int hieth_init_skb_buffers(struct hieth_netdev_priv *priv)
{
int i;
struct sk_buff *skb;
for (i = 0; i < CONFIG_HIETH_MAX_RX_POOLS; i++) {
skb = dev_alloc_skb(SKB_SIZE);
if (!skb)
break;
priv->rx_pool.sk_pool[i] = skb;
}
if (i < CONFIG_HIETH_MAX_RX_POOLS) {
pr_err("no mem\n");
for (i--; i > 0; i--)
dev_kfree_skb_any(priv->rx_pool.sk_pool[i]);
return -ENOMEM;
}
priv->rx_pool.next_free_skb = 0;
priv->stat.rx_pool_dry_times = 0;
return 0;
}
static void hieth_destroy_skb_buffers(struct hieth_netdev_priv *priv)
{
int i;
for (i = 0; i < CONFIG_HIETH_MAX_RX_POOLS; i++)
dev_kfree_skb_any(priv->rx_pool.sk_pool[i]);
priv->rx_pool.next_free_skb = 0;
priv->stat.rx_pool_dry_times = 0;
}
static void hieth_net_isr_proc(struct net_device *ndev, int ints)
{
struct hieth_netdev_priv *priv = netdev_priv(ndev);
if ((ints & UD_BIT_NAME(HIETH_GLB_IRQ_INT_MULTI_RXRDY)) ||
(ints & UD_BIT_NAME(HIETH_GLB_IRQ_INT_TXQUE_RDY))) {
hieth_clear_irqstatus(priv, UD_BIT_NAME(HIETH_GLB_IRQ_INT_TXQUE_RDY));
hieth_irq_disable(priv,
UD_BIT_NAME(HIETH_GLB_IRQ_INT_MULTI_RXRDY));
hieth_irq_disable(priv,
UD_BIT_NAME(HIETH_GLB_IRQ_INT_TXQUE_RDY));
napi_schedule(&priv->napi);
}
}
static irqreturn_t hieth_net_isr(int irq, void *dev_id)
{
int ints;
struct net_device *dev = (struct net_device *)dev_id;
struct hieth_netdev_priv *priv = netdev_priv(dev);
/*mask the all interrupt */
hieth_irq_disable(priv, HIETH_GLB_IRQ_ENA_IEN_A);
ints = hieth_readl(priv->glb_base, HIETH_GLB_IRQ_STAT);
if ((HIETH_PORT_0 == priv->port) &&
likely(ints & HIETH_GLB_IRQ_ENA_BIT_U)) {
hieth_net_isr_proc(dev, (ints & HIETH_GLB_IRQ_ENA_BIT_U));
hieth_clear_irqstatus(priv, (ints & HIETH_GLB_IRQ_ENA_BIT_U));
ints &= ~HIETH_GLB_IRQ_ENA_BIT_U;
}
if ((HIETH_PORT_1 == priv->port) &&
likely(ints & HIETH_GLB_IRQ_ENA_BIT_D)) {
hieth_net_isr_proc(dev, (ints & HIETH_GLB_IRQ_ENA_BIT_D));
hieth_clear_irqstatus(priv, (ints & HIETH_GLB_IRQ_ENA_BIT_D));
ints &= ~HIETH_GLB_IRQ_ENA_BIT_D;
}
/*unmask the all interrupt */
hieth_irq_enable(priv, HIETH_GLB_IRQ_ENA_IEN_A);
return IRQ_HANDLED;
}
static void hieth_monitor_func(unsigned long arg)
{
struct net_device *dev = (struct net_device *)arg;
struct hieth_netdev_priv *priv = netdev_priv(dev);
if (!priv || !netif_running(dev)) {
pr_debug("network driver is stopped.\n");
return;
}
hieth_feed_hw(priv);
hieth_xmit_release_skb(priv);
priv->monitor.expires =
jiffies + msecs_to_jiffies(HIETH_MONITOR_TIMER);
add_timer(&priv->monitor);
}
static int hieth_net_open(struct net_device *dev)
{
int ret = 0;
struct cpumask cpumask;
struct hieth_netdev_priv *priv = netdev_priv(dev);
ret = request_irq(dev->irq, hieth_net_isr, IRQF_SHARED,
dev->name, dev);
if (ret) {
pr_err("request_irq %d failed!\n", dev->irq);
return ret;
}
/* set irq affinity */
if ((num_online_cpus() > 1) && cpu_online(HIETH_IRQ_AFFINITY_CPU)) {
cpumask_clear(&cpumask);
cpumask_set_cpu(HIETH_IRQ_AFFINITY_CPU, &cpumask);
irq_set_affinity(dev->irq, &cpumask);
}
if (!is_valid_ether_addr(dev->dev_addr))
random_ether_addr(dev->dev_addr);
hieth_hw_set_macaddress(priv, dev->dev_addr);
/* setup hardware */
hieth_set_hwq_depth(priv);
hieth_clear_irqstatus(priv, UD_BIT_NAME(HIETH_GLB_IRQ_ENA_BIT));
netif_carrier_off(dev);
hieth_feed_hw(priv);
netif_wake_queue(dev);
napi_enable(&priv->napi);
priv->link_stat = 0;
if (priv->phy)
phy_start(priv->phy);
hieth_irq_enable(priv, UD_BIT_NAME(HIETH_GLB_IRQ_INT_MULTI_RXRDY) |
UD_BIT_NAME(HIETH_GLB_IRQ_ENA_IEN) |
HIETH_GLB_IRQ_ENA_IEN_A);
priv->monitor.expires =
jiffies + msecs_to_jiffies(HIETH_MONITOR_TIMER);
add_timer(&priv->monitor);
return 0;
}
static int hieth_net_close(struct net_device *dev)
{
struct hieth_netdev_priv *priv = netdev_priv(dev);
hieth_irq_disable(priv, UD_BIT_NAME(HIETH_GLB_IRQ_INT_MULTI_RXRDY));
napi_disable(&priv->napi);
netif_stop_queue(dev);
if (priv->phy)
phy_stop(priv->phy);
del_timer_sync(&priv->monitor);
/* reset and init port */
hieth_port_reset(priv);
skb_queue_purge(&priv->rx_head);
skb_queue_purge(&priv->rx_hw);
skb_queue_purge(&priv->tx_hw);
priv->tx_hw_cnt = 0;
free_irq(dev->irq, dev);
return 0;
}
static void hieth_net_timeout(struct net_device *dev)
{
pr_err("tx timeout\n");
}
#if defined(CONFIG_ARCH_HI3798MV2X)
#define HIETH_COPY_WHEN_XMIT
#endif
#ifdef HIETH_COPY_WHEN_XMIT
static struct sk_buff *hieth_skb_copy(const struct sk_buff *skb, gfp_t gfp_mask)
{
unsigned int size = skb->len + ETH_FCS_LEN;
struct sk_buff *n = __alloc_skb(size, gfp_mask, 0, NUMA_NO_NODE);
if (!n)
return NULL;
/* Set the tail pointer and length */
skb_put(n, skb->len);
if (skb_copy_bits(skb, 0, n->data, skb->len))
BUG();
return n;
}
#endif
static int hieth_net_hard_start_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct hieth_netdev_priv *priv = netdev_priv(dev);
#ifdef HIETH_COPY_WHEN_XMIT
bool tx_buff_not_aligned = false;
#endif
if (!hieth_hw_xmitq_ready(priv)) {
priv->stats.tx_dropped++;
netif_stop_queue(dev);
hieth_irq_enable(priv,
UD_BIT_NAME(HIETH_GLB_IRQ_INT_TXQUE_RDY));
return NETDEV_TX_BUSY;
}
#ifdef HIETH_COPY_WHEN_XMIT
tx_buff_not_aligned = (unsigned long)(skb->data) & GENMASK(5, 2);
if (tx_buff_not_aligned) {
struct sk_buff *new_skb = NULL;
new_skb = hieth_skb_copy(skb, GFP_ATOMIC);
if (new_skb) {
dev_kfree_skb_any(skb);
skb = new_skb;
}
}
#endif
dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE);
hieth_xmit_real_send(priv, skb);
dev->trans_start = jiffies;
priv->stats.tx_packets++;
priv->stats.tx_bytes += skb->len;
return NETDEV_TX_OK;
}
static struct net_device_stats *hieth_net_get_stats(struct net_device *dev)
{
struct hieth_netdev_priv *priv = netdev_priv(dev);
return &priv->stats;
}
static int hieth_net_set_mac_address(struct net_device *dev, void *p)
{
struct hieth_netdev_priv *priv = netdev_priv(dev);
struct sockaddr *addr = p;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
eth_commit_mac_addr_change(dev, p);
dev->addr_assign_type &= ~NET_ADDR_RANDOM;
hieth_hw_set_macaddress(priv, dev->dev_addr);
return 0;
}
static inline void hieth_enable_mac_addr_filter(struct hieth_netdev_priv *priv,
unsigned int reg_n, int enable)
{
u32 val;
val = hieth_readl(priv->glb_base, GLB_MAC_H16(priv->port, reg_n));
if (enable)
val |= UD_BIT_NAME(HIETH_GLB_MACFLT_ENA);
else
val &= ~(UD_BIT_NAME(HIETH_GLB_MACFLT_ENA));
hieth_writel(priv->glb_base, val, GLB_MAC_H16(priv->port, reg_n));
}
static void hieth_set_mac_addr(struct hieth_netdev_priv *priv, u8 addr[6],
unsigned int high, unsigned int low)
{
u32 val;
u32 data;
val = hieth_readl(priv->glb_base, high);
val |= UD_BIT_NAME(HIETH_GLB_MACFLT_ENA);
hieth_writel(priv->glb_base, val, high);
val &= ~HIETH_GLB_MACFLT_HI16;
val |= ((addr[0] << 8) | addr[1]);
hieth_writel(priv->glb_base, val, high);
data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
hieth_writel(priv->glb_base, data, low);
val |= UD_BIT_NAME(HIETH_GLB_MACFLT_FW2CPU);
hieth_writel(priv->glb_base, val, high);
}
static inline void hieth_set_mac_addr_filter(struct hieth_netdev_priv *priv,
unsigned char *addr,
unsigned int reg_n)
{
hieth_set_mac_addr(priv, addr, GLB_MAC_H16(priv->port, reg_n),
GLB_MAC_L32(priv->port, reg_n));
}
static void hieth_net_set_rx_mode(struct net_device *dev)
{
u32 val;
struct hieth_netdev_priv *priv = netdev_priv(dev);
local_lock(priv);
multicast_dump_netdev_flags(dev->flags);
val = hieth_readl(priv->glb_base, HIETH_GLB_FWCTRL);
if (dev->flags & IFF_PROMISC) {
val |= ((priv->port == HIETH_PORT_0) ?
HIETH_GLB_FWCTRL_FWALL2CPU_U :
HIETH_GLB_FWCTRL_FWALL2CPU_D);
hieth_writel(priv->glb_base, val, HIETH_GLB_FWCTRL);
} else {
val &= ~((priv->port == HIETH_PORT_0) ?
HIETH_GLB_FWCTRL_FWALL2CPU_U :
HIETH_GLB_FWCTRL_FWALL2CPU_D);
hieth_writel(priv->glb_base, val, HIETH_GLB_FWCTRL);
val = hieth_readl(priv->glb_base, HIETH_GLB_MACTCTRL);
if ((netdev_mc_count(dev) > HIETH_MAX_MULTICAST_ADDRESSES) ||
(dev->flags & IFF_ALLMULTI)) {
val |= UD_BIT_NAME(HIETH_GLB_MACTCTRL_MULTI2CPU);
} else {
int reg = HIETH_MAX_UNICAST_ADDRESSES;
int i, nr = 0;
struct netdev_hw_addr *ha;
for (i = reg; i < HIETH_MAX_MAC_FILTER_NUM; i++)
hieth_enable_mac_addr_filter(priv, i, 0);
netdev_for_each_mc_addr(ha, dev) {
hieth_set_mac_addr_filter(priv, ha->addr, reg);
multicast_dump_macaddr(nr++, ha->addr);
reg++;
}
val &= ~(UD_BIT_NAME(HIETH_GLB_MACTCTRL_MULTI2CPU));
}
/* Handle multiple unicast addresses (perfect filtering)*/
if (netdev_uc_count(dev) > HIETH_MAX_UNICAST_ADDRESSES) {
val |= UD_BIT_NAME(HIETH_GLB_MACTCTRL_UNI2CPU);
} else {
int reg = 0;
int i;
struct netdev_hw_addr *ha;
for (i = reg; i < HIETH_MAX_UNICAST_ADDRESSES; i++)
hieth_enable_mac_addr_filter(priv, i, 0);
netdev_for_each_uc_addr(ha, dev) {
hieth_set_mac_addr_filter(priv, ha->addr, reg);
reg++;
}
val &= ~(UD_BIT_NAME(HIETH_GLB_MACTCTRL_UNI2CPU));
}
hieth_writel(priv->glb_base, val, HIETH_GLB_MACTCTRL);
}
local_unlock(priv);
}
static int hieth_net_ioctl(struct net_device *net_dev,
struct ifreq *ifreq, int cmd)
{
struct hieth_netdev_priv *priv = netdev_priv(net_dev);
struct hieth_pm_config pm_config;
switch (cmd) {
case SIOCSETPM:
if (copy_from_user(&pm_config, ifreq->ifr_data,
sizeof(pm_config)))
return -EFAULT;
return hieth_pmt_config(&pm_config);
default:
if (!netif_running(net_dev))
return -EINVAL;
if (!priv->phy)
return -EINVAL;
return phy_mii_ioctl(priv->phy, ifreq, cmd);
}
return 0;
}
static void hieth_ethtools_get_drvinfo(struct net_device *net_dev,
struct ethtool_drvinfo *info)
{
strcpy(info->driver, "hieth driver");
strcpy(info->version, "v300");
strcpy(info->bus_info, "platform");
}
static u32 hieth_ethtools_get_link(struct net_device *net_dev)
{
struct hieth_netdev_priv *priv = netdev_priv(net_dev);
return ((priv->phy->link) ? HIETH_P_MAC_PORTSET_LINKED : 0);
}
static int hieth_ethtools_get_settings(struct net_device *net_dev,
struct ethtool_cmd *cmd)
{
struct hieth_netdev_priv *priv = netdev_priv(net_dev);
if (priv->phy)
return phy_ethtool_gset(priv->phy, cmd);
return -EINVAL;
}
static int hieth_ethtools_set_settings(struct net_device *net_dev,
struct ethtool_cmd *cmd)
{
struct hieth_netdev_priv *priv = netdev_priv(net_dev);
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if (priv->phy)
return phy_ethtool_sset(priv->phy, cmd);
return -EINVAL;
}
static void hieth_get_mac_wol(struct net_device *dev,
struct ethtool_wolinfo *wol)
{
wol->supported = WAKE_UCAST | WAKE_MAGIC;
wol->wolopts = 0;
}
static void hieth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
wol->supported = 0;
wol->wolopts = 0;
if (dev->phydev)
phy_ethtool_get_wol(dev->phydev, wol);
if (!wol->supported)
hieth_get_mac_wol(dev, wol);
}
static int hieth_set_mac_wol(struct net_device *dev,
struct ethtool_wolinfo *wol)
{
struct hieth_netdev_priv *priv = netdev_priv(dev);
int err = 0;
struct hieth_pm_config mac_pm_config = { 0 };
mac_pm_config.index = BIT(priv->port);
if (wol->wolopts & WAKE_UCAST)
mac_pm_config.uc_pkts_enable = 1;
if (wol->wolopts & WAKE_MAGIC)
mac_pm_config.magic_pkts_enable = 1;
hieth_pmt_config(&mac_pm_config);
return err;
}
static int hieth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct hieth_netdev_priv *priv = netdev_priv(dev);
int err = 0;
if (dev->phydev)
err = phy_ethtool_set_wol(dev->phydev, wol);
if (err == -EOPNOTSUPP)
err = hieth_set_mac_wol(dev, wol);
if (!err)
priv->mac_wol_enabled = true;
return err;
}
static struct ethtool_ops hieth_ethtools_ops = {
.get_drvinfo = hieth_ethtools_get_drvinfo,
.get_link = hieth_ethtools_get_link,
.get_settings = hieth_ethtools_get_settings,
.set_settings = hieth_ethtools_set_settings,
.get_wol = hieth_get_wol,
.set_wol = hieth_set_wol,
};
static const struct net_device_ops hieth_netdev_ops = {
.ndo_open = hieth_net_open,
.ndo_stop = hieth_net_close,
.ndo_start_xmit = hieth_net_hard_start_xmit,
.ndo_tx_timeout = hieth_net_timeout,
.ndo_do_ioctl = hieth_net_ioctl,
.ndo_set_mac_address = hieth_net_set_mac_address,
.ndo_set_rx_mode = hieth_net_set_rx_mode,
.ndo_change_mtu = eth_change_mtu,
.ndo_get_stats = hieth_net_get_stats,
};
void hieth_clean_rx(struct hieth_netdev_priv *priv, unsigned int *workdone, int budget)
{
unsigned int nr_recv = 0;
struct sk_buff *skb;
struct net_device *dev = hieth_devs_save[priv->port];
int ret = 0;
hieth_recv_budget(priv, budget);
while ((skb = skb_dequeue(&priv->rx_head)) != NULL) {
skb->protocol = eth_type_trans(skb, dev);
if (HIETH_INVALID_RXPKG_LEN(skb->len)) {
pr_err("pkg len error");
priv->stats.rx_errors++;
priv->stats.rx_length_errors++;
dev_kfree_skb_any(skb);
continue;
}
priv->stats.rx_packets++;
priv->stats.rx_bytes += skb->len;
dev->last_rx = jiffies;
skb->dev = dev;
ret = netif_receive_skb(skb);
if (ret) {
priv->stats.rx_dropped++;
}
nr_recv++;
}
if (workdone)
*workdone = nr_recv;
}
static int hieth_poll(struct napi_struct *napi, int budget)
{
struct hieth_netdev_priv *priv = NULL;
unsigned int work_done = 0;
priv= container_of(napi, struct hieth_netdev_priv, napi);
hieth_xmit_release_skb(priv);
hieth_clean_rx(priv, &work_done, budget);
if (work_done < budget) {
napi_complete(napi);
hieth_irq_enable(priv, UD_BIT_NAME(HIETH_GLB_IRQ_INT_MULTI_RXRDY));
}
return work_done;
}
static int hieth_platdev_probe_port(struct platform_device *pdev,
struct hieth_netdev_priv *com_priv,
int port)
{
int ret = -1;
struct net_device *netdev = NULL;
struct device *dev = &pdev->dev;
struct hieth_netdev_priv *priv;
if ((HIETH_PORT_0 != port) && (HIETH_PORT_1 != port)) {
pr_err("port error!\n");
ret = -ENODEV;