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Add BRAM to tilegrid fuzzer, expand ROI to include BRAM
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@JohnDMcMaster
JohnDMcMaster committed Dec 22, 2017
1 parent 99a968c commit 61ab6bd
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Showing 5 changed files with 164 additions and 25 deletions.
6 changes: 3 additions & 3 deletions database/artix7/settings.sh
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
export XRAY_ROI_FRAMES="0x00020500:0x000208ff"
export XRAY_ROI_GRID_X1="29"
export XRAY_ROI="SLICE_X4Y100:SLICE_X27Y149"
export XRAY_ROI_FRAMES="0x00820000:0x000208ff"
export XRAY_ROI_GRID_X1="14"
export XRAY_ROI_GRID_X2="47"
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="52"
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70 changes: 56 additions & 14 deletions fuzzers/005-tilegrid/generate.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,13 @@
tiles.append(line.split())

for arg in sys.argv[1:]:
# arg ex: design_SLICE_X8Y100.delta
with open(arg) as f:
# ex: -bit_000203a1_000_00
line = f.read().strip()
# Slice off design_
site = arg[7:-6]
# -bit_000203a1_000_00 => 000203a1
frame = int(line[5:5+8], 16)
site_baseaddr[site] = "0x%08x" % (frame & ~0x7f)

Expand All @@ -42,6 +46,7 @@
"grid_y": grid_y
}

# If given, add sites to the tile
if len(record) > 4:
for i in range(4, len(record), 2):
site_type, site_name = record[i:i+2]
Expand Down Expand Up @@ -71,6 +76,18 @@
database["segments"][segment_name]["words"] = 1
database["tiles"][tile_name]["segment"] = segment_name

if tile_type in ["BRAM_L", "BRAM_R"]:
segment_name = "SEG_" + tile_name
segtype = tile_type.lower()
database["segments"][segment_name] = dict()
database["segments"][segment_name]["tiles"] = [tile_name]
database["segments"][segment_name]["type"] = segtype
database["segments"][segment_name]["frames"] = 128
database["segments"][segment_name]["words"] = 10
if framebaseaddr is not None:
database["segments"][segment_name]["baseaddr"] = [framebaseaddr, 0]
database["tiles"][tile_name]["segment"] = segment_name


#######################################
# Pupulate segment base addresses
Expand All @@ -83,21 +100,46 @@

for segment_name in start_segments:
framebase, wordbase = database["segments"][segment_name]["baseaddr"]
clbtile = [tile for tile in database["segments"][segment_name]["tiles"] if tile.startswith("CLBL")][0]
grid_x = database["tiles"][clbtile]["grid_x"]
grid_y = database["tiles"][clbtile]["grid_y"]

for i in range(49):
while True:
grid_y -= 1
clbtile = tiles_by_grid[(grid_x, grid_y)]
if clbtile.startswith("CLBL"): break

wordbase += 2
if wordbase == 50: wordbase += 1

segname = database["tiles"][clbtile]["segment"]
database["segments"][segname]["baseaddr"] = [framebase, wordbase]
tiles = [tile for tile in database["segments"][segment_name]["tiles"] if tile.startswith("CLBL")]
if tiles:
tile = tiles[0]
grid_x = database["tiles"][tile]["grid_x"]
grid_y = database["tiles"][tile]["grid_y"]

# Populate remaining tiles
for i in range(49):
while True:
grid_y -= 1
tile = tiles_by_grid[(grid_x, grid_y)]
if tile.startswith("CLBL"): break

wordbase += 2
# Skip HCLK
if wordbase == 50: wordbase += 1

segname = database["tiles"][tile]["segment"]
database["segments"][segname]["baseaddr"] = [framebase, wordbase]

tiles = [tile for tile in database["segments"][segment_name]["tiles"] if tile.startswith("BRAM_L")]
if tiles:
tile = tiles[0]
grid_x = database["tiles"][tile]["grid_x"]
grid_y = database["tiles"][tile]["grid_y"]

# Populate remaining tiles
for i in range(9):
while True:
grid_y -= 1
tile = tiles_by_grid[(grid_x, grid_y)]
if tile.startswith("BRAM"): break

wordbase += 10
# Skip HCLK
if wordbase == 50: wordbase += 1

segname = database["tiles"][tile]["segment"]
database["segments"][segname]["baseaddr"] = [framebase, wordbase]


#######################################
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40 changes: 38 additions & 2 deletions fuzzers/005-tilegrid/generate.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,10 @@ set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter
set selected_luts {}
set lut_index 0

set brams [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ RAMBFIFO36E1*}]
set selected_brams {}
set bram_index 0

if 0 {
set grid_min_x -1
set grid_max_x -1
Expand Down Expand Up @@ -50,13 +54,35 @@ foreach lut $luts {

# 50 per column => 50, 100, 150, etc
if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
set cell [get_cells roi/is[$lut_index].lut]
set cell [get_cells roi/luts[$lut_index].lut]
set_property LOC [get_sites -of_objects $lut] $cell
set lut_index [expr $lut_index + 1]
lappend selected_luts $lut
}
}

# Like above
# TODO: can combine this and above?
foreach bram $brams {
set tile [get_tile -of_objects $bram]
set grid_x [get_property GRID_POINT_X $tile]
set grid_y [get_property GRID_POINT_Y $tile]

if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}

if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}

# 10 per column
if [regexp "Y(0|[0-9]*0)/" $bram] {
set cell [get_cells roi/brams[$bram_index].bram]
set_property LOC [get_sites -of_objects $bram] $cell
set bram_index [expr $bram_index + 1]
lappend selected_brams $bram
}
}

place_design
route_design

Expand Down Expand Up @@ -88,12 +114,22 @@ close $fp

# Toggle one bit in each selected LUT to generate base addresses
for {set i 0} {$i < $lut_index} {incr i} {
set cell [get_cells roi/is[$i].lut]
set cell [get_cells roi/luts[$i].lut]
set orig_init [get_property INIT $cell]
# Flip a bit by changing MSB 0 => 1
set new_init [regsub "h8" $orig_init "h0"]
set_property INIT $new_init $cell
write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
set_property INIT $orig_init $cell
}
# Same for BRAM
for {set i 0} {$i < $bram_index} {incr i} {
set cell [get_cells roi/brams[$i].bram]
set orig_init [get_property INIT_00 $cell]
# Flip a bit by changing MSB 0 => 1
set new_init [regsub "h8" $orig_init "h0"]
set_property INIT_00 $new_init $cell
write_bitstream -force design_[get_sites -of_objects [lindex $selected_brams $i]].bit
set_property INIT_00 $orig_init $cell
}

46 changes: 40 additions & 6 deletions fuzzers/005-tilegrid/top.v
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Original file line number Diff line number Diff line change
@@ -1,9 +1,11 @@
//Need at least one LUT per frame base address we want
`define N 100
//Good rule of thumb is to set entries to the max per smallest segment column
`define LUT_N 100
`define BRAM_N 10

module top(input clk, stb, di, output do);
localparam integer DIN_N = 6;
localparam integer DOUT_N = `N;
localparam integer DIN_N = 8;
localparam integer DOUT_N = `LUT_N + `BRAM_N;

reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
Expand All @@ -22,17 +24,19 @@ module top(input clk, stb, di, output do);

assign do = dout_shr[DOUT_N-1];

roi roi (
roi #(.DOUT_N(DOUT_N)) roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule

module roi(input clk, input [5:0] din, output [`N-1:0] dout);
module roi(input clk, input [7:0] din, output [DOUT_N-1:0] dout);
parameter integer DOUT_N = 1;

genvar i;
generate
for (i = 0; i < `N; i = i+1) begin:is
for (i = 0; i < `LUT_N; i = i+1) begin:luts
LUT6 #(
.INIT(64'h8000_0000_0000_0001 + (i << 16))
) lut (
Expand All @@ -45,5 +49,35 @@ module roi(input clk, input [5:0] din, output [`N-1:0] dout);
.O(dout[i])
);
end

for (i = 0; i < `BRAM_N; i = i + 1) begin:brams
(* KEEP, DONT_TOUCH *)
RAMB36E1 #(
.INIT_00(256'h8000000000000000000000000000000000000000000000000000000000000000)
) bram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[i + `LUT_N]),
.DOBDO(),
.DOPADOP(),
.DOPBDOP()
);
end
endgenerate
endmodule
27 changes: 27 additions & 0 deletions minitests/bram/top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,19 @@ module top(input clk, stb, di, output do);
);
endmodule

//HCK test
module roi_(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT({256{1'b1}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT({256{1'b1}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
//HCK
ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT({256{1'b1}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT({256{1'b1}}))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
endmodule

/*
One BRAM per tile
*/
Expand All @@ -43,6 +56,20 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b1), .INIT({256{1'b0}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b1), .INIT({256{1'b0}}))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b1), .INIT({256{1'b0}}))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b1), .INIT({256{1'b0}}))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b1), .INIT({256{1'b0}}))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b1), .INIT({256{1'b0}}))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b1), .INIT({256{1'b0}}))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b1), .INIT({256{1'b0}}))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule

/*
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