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rk3528.dtsi
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rk3528.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rk3528-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3528-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rk3528.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/display/rockchip-tve.h>
/ {
compatible = "rockchip,rk3528";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &sfc;
};
clocks {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "xin24m";
};
mclkin_sai0: mclkin-sai0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "i2s0_mclkin";
};
mclkin_sai1: mclkin-sai1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "i2s1_mclkin";
};
mclkout_sai0: mclkout-sai0@ff340014 {
compatible = "rockchip,clk-out";
reg = <0 0xff340014 0 0x4>;
clocks = <&cru MCLK_SAI_I2S0>;
#clock-cells = <0>;
clock-output-names = "mclk_sai0_to_io";
rockchip,bit-shift = <1>;
rockchip,bit-set-to-disable;
};
mclkout_sai1: mclkout-sai1@ff320004 {
compatible = "rockchip,clk-out";
reg = <0 0xff320004 0 0x4>;
clocks = <&cru MCLK_SAI_I2S1>;
#clock-cells = <0>;
clock-output-names = "mclk_sai1_to_io";
rockchip,bit-shift = <14>;
rockchip,bit-set-to-disable;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <147>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP1>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP1>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP0: cpu-sleep0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <120>;
exit-latency-us = <250>;
min-residency-us = <900>;
status = "disabled";
};
CPU_SLEEP1: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <120>;
exit-latency-us = <250>;
min-residency-us = <900>;
status = "okay";
};
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
mbist-vmin = <825000 925000 975000>;
nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&cpu_mbist_vmin>;
nvmem-cell-names = "leakage", "opp-info", "mbist-vmin";
rockchip,video-4k-freq = <1200000>;
rockchip,pvtm-voltage-sel = <
0 1320 0
1321 1350 1
1351 1375 2
1376 1405 3
1406 1435 4
1436 1470 5
1471 1505 6
1506 1540 7
1541 1575 8
1576 1610 9
1611 1640 10
1641 9999 11
>;
rockchip,pvtm-pvtpll;
rockchip,pvtm-offset = <0x18>;
rockchip,pvtm-sample-time = <1100>;
rockchip,pvtm-freq = <1608000>;
rockchip,pvtm-volt = <900000>;
rockchip,pvtm-ref-temp = <40>;
rockchip,pvtm-temp-prop = <0 0>;
rockchip,pvtm-thermal-zone = "soc-thermal";
rockchip,grf = <&grf>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <825000 825000 1100000>;
opp-microvolt-L0 = <875000 875000 1100000>;
opp-microvolt-L1 = <875000 875000 1100000>;
opp-microvolt-L2 = <875000 875000 1100000>;
opp-microvolt-L3 = <875000 875000 1100000>;
opp-microvolt-L4 = <875000 875000 1100000>;
opp-microvolt-L5 = <850000 850000 1100000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <825000 825000 1100000>;
opp-microvolt-L0 = <875000 875000 1100000>;
opp-microvolt-L1 = <875000 875000 1100000>;
opp-microvolt-L2 = <875000 875000 1100000>;
opp-microvolt-L3 = <875000 875000 1100000>;
opp-microvolt-L4 = <875000 875000 1100000>;
opp-microvolt-L5 = <850000 850000 1100000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <825000 825000 1100000>;
opp-microvolt-L0 = <875000 875000 1100000>;
opp-microvolt-L1 = <875000 875000 1100000>;
opp-microvolt-L2 = <875000 875000 1100000>;
opp-microvolt-L3 = <875000 875000 1100000>;
opp-microvolt-L4 = <875000 875000 1100000>;
opp-microvolt-L5 = <850000 850000 1100000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <825000 825000 1100000>;
opp-microvolt-L0 = <875000 875000 1100000>;
opp-microvolt-L1 = <875000 875000 1100000>;
opp-microvolt-L2 = <875000 875000 1100000>;
opp-microvolt-L3 = <875000 875000 1100000>;
opp-microvolt-L4 = <875000 875000 1100000>;
opp-microvolt-L5 = <850000 850000 1100000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <825000 825000 1100000>;
opp-microvolt-L0 = <900000 900000 1100000>;
opp-microvolt-L1 = <887500 887500 1100000>;
opp-microvolt-L2 = <875000 875000 1100000>;
opp-microvolt-L3 = <875000 875000 1100000>;
opp-microvolt-L4 = <875000 875000 1100000>;
opp-microvolt-L5 = <862500 862500 1100000>;
opp-microvolt-L6 = <850000 850000 1100000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <962500 962500 1100000>;
opp-microvolt-L1 = <950000 950000 1100000>;
opp-microvolt-L2 = <950000 950000 1100000>;
opp-microvolt-L3 = <937500 937500 1100000>;
opp-microvolt-L4 = <925000 925000 1100000>;
opp-microvolt-L5 = <912500 912500 1100000>;
opp-microvolt-L6 = <900000 900000 1100000>;
opp-microvolt-L7 = <887500 887000 1100000>;
opp-microvolt-L8 = <875000 875000 1100000>;
opp-microvolt-L9 = <862500 862500 1100000>;
opp-microvolt-L10 = <850000 850000 1100000>;
opp-microvolt-L11 = <850000 850000 1100000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1012500 1012500 1100000>;
opp-microvolt-L2 = <1000000 1000000 1100000>;
opp-microvolt-L3 = <987500 987500 1100000>;
opp-microvolt-L4 = <975000 975000 1100000>;
opp-microvolt-L5 = <962500 962500 1100000>;
opp-microvolt-L6 = <950000 950000 1100000>;
opp-microvolt-L7 = <937500 937500 1100000>;
opp-microvolt-L8 = <925000 925000 1100000>;
opp-microvolt-L9 = <912500 912500 1100000>;
opp-microvolt-L10 = <900000 900000 1100000>;
opp-microvolt-L11 = <887500 887500 1100000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500 1062500 1100000>;
opp-microvolt-L1 = <1050000 1050000 1100000>;
opp-microvolt-L2 = <1037500 1037500 1100000>;
opp-microvolt-L3 = <1025000 1025000 1100000>;
opp-microvolt-L4 = <1012500 1012500 1100000>;
opp-microvolt-L5 = <1000000 1000000 1100000>;
opp-microvolt-L6 = <987500 987500 1100000>;
opp-microvolt-L7 = <975000 975000 1100000>;
opp-microvolt-L8 = <962500 962500 1100000>;
opp-microvolt-L9 = <950000 950000 1100000>;
opp-microvolt-L10 = <937500 937500 1100000>;
opp-microvolt-L11 = <925000 925000 1100000>;
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1100000 1100000 1100000>;
opp-microvolt-L1 = <1087500 1087500 1100000>;
opp-microvolt-L2 = <1075000 1075000 1100000>;
opp-microvolt-L3 = <1062500 1062500 1100000>;
opp-microvolt-L4 = <1050000 1050000 1100000>;
opp-microvolt-L5 = <1037500 1037500 1100000>;
opp-microvolt-L6 = <1025000 1025000 1100000>;
opp-microvolt-L7 = <1012500 1012500 1100000>;
opp-microvolt-L8 = <1000000 1000000 1100000>;
opp-microvolt-L9 = <987500 987500 1100000>;
opp-microvolt-L10 = <975000 975000 1100000>;
opp-microvolt-L11 = <962500 962500 1100000>;
clock-latency-ns = <40000>;
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
nvmem-cell-names = "id", "cpu-version", "cpu-code";
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
status = "disabled";
};
dmc: dmc {
compatible = "rockchip,rk3528-dmc";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete";
devfreq-events = <&dfi>;
clocks = <&scmi_clk SCMI_CLK_DDR>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
upthreshold = <40>;
downdifferential = <20>;
system-status-level = <
/* system status freq level */
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH
>;
auto-min-freq = <324000>;
auto-freq-en = <0>;
status = "disabled";
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
mbist-vmin = <850000 900000>;
nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&logic_mbist_vmin>;
nvmem-cell-names = "leakage", "opp-info", "mbist-vmin";
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
rockchip,leakage-voltage-sel = <
1 10 0
11 14 1
15 22 2
23 28 3
29 254 4
>;
opp-920000000 {
opp-hz = /bits/ 64 <920000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <875000 875000 1000000>;
opp-microvolt-L1 = <850000 850000 1000000>;
opp-microvolt-L2 = <850000 850000 1000000>;
opp-microvolt-L3 = <850000 850000 1000000>;
opp-microvolt-L4 = <850000 850000 1000000>;
};
opp-1184000000 {
opp-hz = /bits/ 64 <1184000000>;
opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <950000 950000 1000000>;
opp-microvolt-L1 = <925000 925000 1000000>;
opp-microvolt-L2 = <900000 900000 1000000>;
opp-microvolt-L3 = <875000 875000 1000000>;
opp-microvolt-L4 = <862500 862500 1000000>;
status = "disabled";
};
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
arm,smc-id = <0x82000010>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPU>;
assigned-clock-rates = <1200000000>;
};
};
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <5>;
rockchip,resetgroup-count = <5>;
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rkvtunnel: rkvtunnel {
compatible = "rockchip,video-tunnel";
status = "disabled";
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk3528";
status = "disabled";
rockchip,sleep-debug-en = <0>;
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMPD
)
>;
rockchip,wakeup-config = <
(0
| RKPM_CPU0_WKUP_EN
| RKPM_GPIO_WKUP_EN
)
>;
};
rockchip_system_monitor: rockchip-system-monitor {
compatible = "rockchip,system-monitor";
rockchip,thermal-zone = "soc-thermal";
rockchip,polling-delay = <200>; /* milliseconds */
rockchip,temp-hysteresis = <5000>; /* millicelsius */
rockchip,offline-cpu-temp = <105000>; /* millicelsius */
rockchip,temp-offline-cpus = "2-3";
};
secure_otp: secure-otp {
compatible = "rockchip,secure-otp";
rockchip,otp-size = <32>;
status = "disabled";
};
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <638>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point-0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point-1 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit: soc-crit {
temperature = <120000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map1 {
trip = <&target>;
cooling-device =
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi_shmem: scmi-shmem@10f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x0010f000 0x0 0x100>;
};
sram: sram@fe480000 {
compatible = "mmio-sram";
reg = <0x0 0xfe480000 0x0 0xc000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xfe480000 0xc000>;
/* start address and size should be 4k algin */
rkvdec_sram: rkvdec-sram@0 {
reg = <0x0 0xc000>;
};
};
pcie2x1: pcie@fe4f0000 {
compatible = "rockchip,rk3528-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
<&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
<&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
<&cru PCLK_PCIE_PHY>;
clock-names = "aclk", "hclk_slv",
"hclk_dbi", "pclk_cru",
"aux", "pclk",
"pipe";
device_type = "pci";
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
<0 0 0 2 &pcie2x1_intc 1>,
<0 0 0 3 &pcie2x1_intc 2>,
<0 0 0 4 &pcie2x1_intc 3>;
linux,pci-domain = <0>;
num-ib-windows = <8>;
num-ob-windows = <8>;
num-viewport = <4>;
max-link-speed = <2>;
num-lanes = <1>;
phys = <&combphy_pu PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
ranges = <0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
reg = <0x0 0xfe4f0000 0x0 0x10000>,
<0x1 0x40000000 0x0 0x400000>,
<0x0 0xfc000000 0x0 0x100000>;
reg-names = "pcie-apb", "pcie-dbi", "config";
resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
<&cru SRST_PRESETN_CRU_PCIE>;
reset-names = "pcie", "periph", "preset_cru";
status = "disabled";
pcie2x1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
};
};
usbdrd30: usbdrd {
compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
<&cru ACLK_USB3OTG>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usbdrd_dwc3: dwc3@fe500000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe500000 0x0 0x400000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
resets = <&cru SRST_ARESETN_USB3OTG>;
reset-names = "usb3-otg";
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
quirk-skip-phy-init;
status = "disabled";
};
};
gic: interrupt-controller@fed01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfed01000 0 0x1000>,
<0x0 0xfed02000 0 0x2000>,
<0x0 0xfed04000 0 0x2000>,
<0x0 0xfed06000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
usb_host0_ehci: usb@ff100000 {
compatible = "generic-ehci";
reg = <0x0 0xff100000 0x0 0x40000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST>,
<&cru HCLK_USBHOST_ARB>,
<&usb2phy>;
clock-names = "usbhost", "arbiter", "utmi";
phys = <&u2phy_host>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host0_ohci: usb@ff140000 {
compatible = "generic-ohci";
reg = <0x0 0xff140000 0x0 0x40000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST>,
<&cru HCLK_USBHOST_ARB>,
<&usb2phy>;
clock-names = "usbhost", "arbiter", "utmi";
phys = <&u2phy_host>;
phy-names = "usb2-phy";
status = "disabled";
};
debug: debug@ff190000 {
compatible = "rockchip,debug";
reg = <0x0 0xff190000 0x0 0x1000>,
<0x0 0xff192000 0x0 0x1000>,
<0x0 0xff194000 0x0 0x1000>,
<0x0 0xff196000 0x0 0x1000>;
};
qos_crypto_a: qos@ff200000 {
compatible = "syscon";
reg = <0x0 0xff200000 0x0 0x20>;
};
qos_crypto_p: qos@ff200080 {
compatible = "syscon";
reg = <0x0 0xff200080 0x0 0x20>;
};
qos_dcf: qos@ff200100 {
compatible = "syscon";
reg = <0x0 0xff200100 0x0 0x20>;
};
qos_dft2apb: qos@ff200200 {
compatible = "syscon";
reg = <0x0 0xff200200 0x0 0x20>;
};
qos_dma2ddr: qos@ff200280 {
compatible = "syscon";
reg = <0x0 0xff200280 0x0 0x20>;
};
qos_dmac: qos@ff200300 {
compatible = "syscon";
reg = <0x0 0xff200300 0x0 0x20>;
};
qos_keyreader: qos@ff200380 {
compatible = "syscon";
reg = <0x0 0xff200380 0x0 0x20>;
};
qos_cpu: qos@ff210000 {
compatible = "syscon";
reg = <0x0 0xff210000 0x0 0x20>;
};
qos_debug: qos@ff210080 {
compatible = "syscon";
reg = <0x0 0xff210080 0x0 0x20>;
};
qos_gpu_m0: qos@ff220000 {
compatible = "syscon";
reg = <0x0 0xff220000 0x0 0x20>;
};
qos_gpu_m1: qos@ff220080 {
compatible = "syscon";
reg = <0x0 0xff220080 0x0 0x20>;
};
qos_pmu_mcu: qos@ff240000 {
compatible = "syscon";
reg = <0x0 0xff240000 0x0 0x20>;
};
qos_rkvdec: qos@ff250000 {
compatible = "syscon";
reg = <0x0 0xff250000 0x0 0x20>;
};
qos_rkvenc: qos@ff260000 {
compatible = "syscon";
reg = <0x0 0xff260000 0x0 0x20>;
};
qos_gmac0: qos@ff270000 {
compatible = "syscon";
reg = <0x0 0xff270000 0x0 0x20>;
};
qos_hdcp: qos@ff270080 {
compatible = "syscon";
reg = <0x0 0xff270080 0x0 0x20>;
};
qos_jpegdec: qos@ff270100 {
compatible = "syscon";
reg = <0x0 0xff270100 0x0 0x20>;
};
qos_rga2_m0ro: qos@ff270200 {
compatible = "syscon";
reg = <0x0 0xff270200 0x0 0x20>;
};
qos_rga2_m0wo: qos@ff270280 {
compatible = "syscon";
reg = <0x0 0xff270280 0x0 0x20>;
};
qos_sdmmc0: qos@ff270300 {
compatible = "syscon";
reg = <0x0 0xff270300 0x0 0x20>;
};
qos_usb2host: qos@ff270380 {
compatible = "syscon";
reg = <0x0 0xff270380 0x0 0x20>;
};
qos_vdpp: qos@ff270480 {
compatible = "syscon";
reg = <0x0 0xff270480 0x0 0x20>;
};
qos_vop: qos@ff270500 {
compatible = "syscon";
reg = <0x0 0xff270500 0x0 0x20>;
};
qos_emmc: qos@ff280000 {
compatible = "syscon";
reg = <0x0 0xff280000 0x0 0x20>;
};
qos_fspi: qos@ff280080 {
compatible = "syscon";
reg = <0x0 0xff280080 0x0 0x20>;
};
qos_gmac1: qos@ff280100 {
compatible = "syscon";
reg = <0x0 0xff280100 0x0 0x20>;
};
qos_pcie: qos@ff280180 {
compatible = "syscon";
reg = <0x0 0xff280180 0x0 0x20>;
};
qos_sdio0: qos@ff280200 {
compatible = "syscon";
reg = <0x0 0xff280200 0x0 0x20>;
};
qos_sdio1: qos@ff280280 {
compatible = "syscon";
reg = <0x0 0xff280280 0x0 0x20>;
};
qos_tsp: qos@ff280300 {
compatible = "syscon";
reg = <0x0 0xff280300 0x0 0x20>;
};
qos_usb3otg: qos@ff280380 {
compatible = "syscon";
reg = <0x0 0xff280380 0x0 0x20>;
};
qos_vpu: qos@ff280400 {
compatible = "syscon";
reg = <0x0 0xff280400 0x0 0x20>;
};
/*
* Merge all GRF, each independent GRF offset is shown as bellow:
* CORE_GRF: 0xff300000
* GPU_GRF: 0xff310000
* RKVENC_GRF: 0xff320000
* DDR_GRF: 0xff330000
* VPU_GRF: 0xff340000
* COMBO_PIPE_PHY_GRF: 0xff348000
* RKVDEC_GRF: 0xff350000
* VO_GRF: 0xff360000
* PMU_GRF: 0xff370000
* SYS_GRF: 0xff380000
*/
grf: syscon@ff300000 {
compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd";
reg = <0x0 0xff300000 0x0 0x90000>;
grf_cru: grf-clock-controller {
compatible = "rockchip,rk3528-grf-cru";
#clock-cells = <1>;
};
reboot_mode: reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x70200>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-ums = <BOOT_UMS>;
mode-panic = <BOOT_PANIC>;
mode-watchdog = <BOOT_WATCHDOG>;
};
};
cru: clock-controller@ff4a0000 {
compatible = "rockchip,rk3528-cru";
reg = <0x0 0xff4a0000 0x0 0x30000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru XIN_OSC0_DIV>,
<&cru PLL_GPLL>,
<&cru PLL_PPLL>,
<&cru PLL_CPLL>,
<&cru CLK_MATRIX_250M_SRC>,
<&cru CLK_MATRIX_500M_SRC>,
<&cru CLK_MATRIX_50M_SRC>,
<&cru CLK_MATRIX_100M_SRC>,
<&cru CLK_MATRIX_150M_SRC>,
<&cru CLK_MATRIX_200M_SRC>,
<&cru CLK_MATRIX_300M_SRC>,
<&cru CLK_MATRIX_339M_SRC>,
<&cru CLK_MATRIX_400M_SRC>,
<&cru CLK_MATRIX_600M_SRC>,
<&cru CLK_PPLL_50M_MATRIX>,
<&cru CLK_PPLL_100M_MATRIX>,
<&cru CLK_PPLL_125M_MATRIX>,
<&cru ACLK_BUS_VOPGL_ROOT>,
<&cru ACLK_VO_ROOT>,
<&cru ACLK_VPU_ROOT>,
<&cru ACLK_VPU_L_ROOT>;
assigned-clock-rates =
<32768>,
<1188000000>,
<1000000000>,
<996000000>,
<250000000>,
<500000000>,
<50000000>,
<100000000>,
<150000000>,
<200000000>,
<300000000>,
<340000000>,
<400000000>,
<600000000>,
<50000000>,
<100000000>,
<125000000>,
<500000000>,
<340000000>,
<300000000>,
<200000000>;
};
ioc_grf: syscon@ff540000 {
compatible = "rockchip,rk3528-ioc-grf", "syscon";
reg = <0x0 0xff540000 0x0 0x40000>;
};
pmu: power-management@ff600000 {
compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff600000 0x0 0x2000>;
power: power-controller {
compatible = "rockchip,rk3528-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* These power domains are grouped by VD_GPU */
pd_gpu@RK3528_PD_GPU {
reg = <RK3528_PD_GPU>;
clocks = <&cru ACLK_GPU_MALI>,
<&cru PCLK_GPU_ROOT>;
pm_qos = <&qos_gpu_m0>,
<&qos_gpu_m1>;
};
/* These power domains are grouped by VD_LOGIC */
pd_rkvdec@RK3528_PD_RKVDEC {
reg = <RK3528_PD_RKVDEC>;
};
pd_rkvenc@RK3528_PD_RKVENC {
reg = <RK3528_PD_RKVENC>;
};
pd_vo@RK3528_PD_VO {
reg = <RK3528_PD_VO>;
};
pd_vpu@RK3528_PD_VPU {
reg = <RK3528_PD_VPU>;
};
};
};
mailbox: mailbox@ff630000 {