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efx_jtag_spi_flash_loader.peri.xml
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efx_jtag_spi_flash_loader.peri.xml
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<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="efx_jtag_spi_flash_loader" device_def="T8F81" location="/mnt/data/prog/fpga/efx-jtag-spi-flash-loader" version="2022.2.322.1.8" db_version="20222999" last_change_date="Wed Apr 12 17:52:30 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="1B" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="1C" iostd="1.1 V"/>
<efxpt:iobank name="2A" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2B" iostd="3.3 V LVTTL / LVCMOS"/>
</efxpt:iobank_info>
</efxpt:device_info>
<efxpt:gpio_info device_def="T8F81">
<efxpt:gpio name="ext_clkin" gpio_def="GPIOL_20" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="ext_clkin" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="miso" gpio_def="GPIOL_06" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="miso" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="mosi" gpio_def="GPIOL_04" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="mosi" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="nss" gpio_def="GPIOL_01" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="nss" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="sclk" gpio_def="GPIOL_02" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="sclk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="4"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="pll_inst1" pll_def="PLL_0" ref_clock_name="" ref_clock_freq="33.3333" multiplier="72" pre_divider="3" post_divider="1" reset_name="" locked_name="rstn" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clkin" number="0" out_divider="16"/>
</efxpt:pll>
</efxpt:pll_info>
<efxpt:osc_info/>
<efxpt:jtag_info>
<efxpt:jtag name="jtag_inst1" jtag_def="JTAG_USER1">
<efxpt:gen_pin>
<efxpt:pin name="jtag_inst1_DRCK" type_name="DRCK" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TMS" type_name="TMS" is_bus="false"/>
<efxpt:pin name="jtag_inst1_SHIFT" type_name="SHIFT" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TDI" type_name="TDI" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TCK" type_name="TCK" is_bus="false"/>
<efxpt:pin name="jtag_inst1_SEL" type_name="SEL" is_bus="false"/>
<efxpt:pin name="jtag_inst1_RESET" type_name="RESET" is_bus="false"/>
<efxpt:pin name="jtag_inst1_RUNTEST" type_name="RUNTEST" is_bus="false"/>
<efxpt:pin name="jtag_inst1_CAPTURE" type_name="CAPTURE" is_bus="false"/>
<efxpt:pin name="jtag_inst1_UPDATE" type_name="UPDATE" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TDO" type_name="TDO" is_bus="false"/>
</efxpt:gen_pin>
</efxpt:jtag>
</efxpt:jtag_info>
</efxpt:design_db>