forked from riscv-software-src/opensbi
/
edgeboard.dts
148 lines (147 loc) · 4.87 KB
/
edgeboard.dts
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/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-jsteward-dev";
model = "freechips,rocketchip-jsteward";
L16: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <100000000>;
L7: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <4>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L12>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
riscv,pmpregions = <8>;
status = "okay";
tlb-split;
L5: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
L10: cpu@1 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <4>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L12>;
reg = <0x1>;
riscv,isa = "rv64imafdc";
riscv,pmpregions = <8>;
status = "okay";
tlb-split;
L8: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L12: memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x3ff00000>;
};
L15: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-jsteward-soc", "simple-bus";
ranges;
L3: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L5 3 &L5 7 &L8 3 &L8 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L4: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
debug-attach = "jtag";
interrupts-extended = <&L5 65535 &L8 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L1: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
};
L11: external-interrupts {
interrupt-parent = <&L2>;
interrupts = <1>;
};
L2: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L5 11 &L5 9 &L8 11 &L8 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <1>;
riscv,ndev = <1>;
};
L13: mmio-port-axi4@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
reg = <0x0 0x0>;
ranges;
axi_intc: interrupt-controller@e0000000 {
#interrupt-cells = <1>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller;
xlnx,kind-of-intr = <0x0>;
xlnx,num-intr-inputs = <0x1>;
interrupt-parent = <&L2>;
interrupts = <1>;
reg = <0xe0000000 0x1000>;
interrupt-names = "irq";
};
axi_uart0: serial@e0010000 {
clock-frequency = <100000000>;
compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550";
current-speed = <115200>;
device_type = "serial";
interrupt-parent = <&axi_intc>;
interrupts = <1>;
reg = <0xe0010000 0x10000>;
reg-offset = <0x1000>;
reg-shift = <2>;
};
};
L0: subsystem_pbus_clock {
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "subsystem_pbus_clock";
compatible = "fixed-clock";
};
};
chosen {
stdout-path = "/soc/mmio-port-axi4@e0000000/serial@e0010000:115200";
};
};