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/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-jsteward";
L15: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <100000000>;
L7: cpu@0 {
clock-frequency = <100000000>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <8>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L11>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
riscv,pmpregions = <8>;
status = "okay";
tlb-split;
L5: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L11: memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x3ff00000>;
};
L14: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L3: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L5 3 &L5 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L4: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
debug-attach = "jtag";
interrupts-extended = <&L5 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L1: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L5 11 &L5 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <4>;
};
L8: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x2000>;
reg-names = "mem";
};
clk100: subsystem_pbus_clock {
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "subsystem_pbus_clock";
compatible = "fixed-clock";
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-pre-reloc;
};
axi_uart0: serial@e0000000 {
clock-frequency = <100000000>;
compatible = "ns16550a";
current-speed = <115200>;
device_type = "serial";
interrupt-parent = <&plic>;
interrupts = <1>;
reg = <0xe0000000 0x10000>;
reg-offset = <0x1000>;
reg-shift = <2>;
};
axi_uart1: serial@e1000000 {
clock-frequency = <100000000>;
compatible = "ns16550a";
current-speed = <115200>;
device_type = "serial";
interrupt-parent = <&plic>;
interrupts = <2>;
reg = <0xe1000000 0x10000>;
reg-offset = <0x1000>;
reg-shift = <2>;
};
sdhci0: mmc@ff170000 {
u-boot,dm-pre-reloc;
compatible = "arasan,sdhci-8.9a";
reg = <0xff170000 0x1000>;
clocks = <&clk200 &clk200>;
clock-names = "clk_xin", "clk_ahb";
interrupt-parent = <&plic>;
interrupts = <4>;
disable-adma;
no-1-8-v;
disable-wp;
};
};
chosen {
bootargs = "earlycon=sbi root=/dev/mmcblk0p2 rootwait";
stdout-path = "/soc/serial@e0000000:115200";
};
};
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