/
sunxi_host0_2_v4p1.c
executable file
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sunxi_host0_2_v4p1.c
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/** @file
*
* Copyright (c) 2007-2014, Allwinner Technology Co., Ltd. All rights reserved.
* http://www.allwinnertech.com
*
* tangmanliang <tangmanliang@allwinnertech.com>
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "mmc_def.h"
#include "mmc.h"
#include "sunxi_mmc.h"
#include "sunxi_host0_2_v4p1.h"
#include <ccmu.h>
#undef readl
#define readl(a) *(volatile uint *)(ulong)(a)
#undef writel
#define writel(v, c) *(volatile uint *)(ulong)(c) = (v)
#define BIT(x) (1<<(x))
/* Struct for Intrrrupt Information */
#define SDXC_RespErr BIT(1) //0x2
#define SDXC_CmdDone BIT(2) //0x4
#define SDXC_DataOver BIT(3) //0x8
#define SDXC_TxDataReq BIT(4) //0x10
#define SDXC_RxDataReq BIT(5) //0x20
#define SDXC_RespCRCErr BIT(6) //0x40
#define SDXC_DataCRCErr BIT(7) //0x80
#define SDXC_RespTimeout BIT(8) //0x100
#define SDXC_ACKRcv BIT(8) //0x100
#define SDXC_DataTimeout BIT(9) //0x200
#define SDXC_BootStart BIT(9) //0x200
#define SDXC_DataStarve BIT(10) //0x400
#define SDXC_VolChgDone BIT(10) //0x400
#define SDXC_FIFORunErr BIT(11) //0x800
#define SDXC_HardWLocked BIT(12) //0x1000
#define SDXC_StartBitErr BIT(13) //0x2000
#define SDXC_AutoCMDDone BIT(14) //0x4000
#define SDXC_EndBitErr BIT(15) //0x8000
#define SDXC_SDIOInt BIT(16) //0x10000
#define SDXC_CardInsert BIT(30) //0x40000000
#define SDXC_CardRemove BIT(31) //0x80000000
#define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr \
| SDXC_RespTimeout | SDXC_DataTimeout | SDXC_FIFORunErr \
| SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr) //0xbfc2
extern int mmc_clk_io_onoff(int sdc_no, int onoff, int reset_clk);
void mmc_dump_errinfo(struct sunxi_mmc_host* smc_host, struct mmc_cmd *cmd)
{
MMCMSG(smc_host->mmc, "smc %d err, cmd %d, %a%a%a%a%a%a%a%a%a%a%a\n",
smc_host->mmc_no, cmd? cmd->cmdidx: -1,
smc_host->raw_int_bak & SDXC_RespErr ? " RE" : "",
smc_host->raw_int_bak & SDXC_RespCRCErr ? " RCE" : "",
smc_host->raw_int_bak & SDXC_DataCRCErr ? " DCE" : "",
smc_host->raw_int_bak & SDXC_RespTimeout ? " RTO" : "",
smc_host->raw_int_bak & SDXC_DataTimeout ? " DTO" : "",
smc_host->raw_int_bak & SDXC_DataStarve ? " DS" : "",
smc_host->raw_int_bak & SDXC_FIFORunErr ? " FE" : "",
smc_host->raw_int_bak & SDXC_HardWLocked ? " HL" : "",
smc_host->raw_int_bak & SDXC_StartBitErr ? " SBE" : "",
smc_host->raw_int_bak & SDXC_EndBitErr ? " EBE" : "",
smc_host->raw_int_bak ==0 ? " STO" : ""
);
}
int sunxi_clock_get_pll6(void)
{
unsigned int reg_val;
int factor_n, factor_k, pll6;
reg_val = readl(CCMU_PLL_PERIPH0_CTRL_REG);
factor_n = ((reg_val >> 8) & 0x1f) + 1;
factor_k = ((reg_val >> 4) & 0x03) + 1;
pll6 = 24 * factor_n * factor_k/2;
return pll6;
}
static int mmc_update_clk(struct sunxi_mmc_host* mmchost)
{
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
unsigned int cmd;
unsigned timeout = 1000;
writel(readl(®->clkcr)|(0x1<<31), ®->clkcr);
cmd = (1U << 31) | (1 << 21) | (1 << 13);
writel(cmd, ®->cmd);
while((readl(®->cmd)&0x80000000) && --timeout){
mdelay(1);
}
if (!timeout){
MMCINFO("mmc %d update clk failed\n",mmchost->mmc_no);
dumphex32("mmc", (char*)reg, 0x100);
return -1;
}
writel(readl(®->clkcr) & (~(0x1<<31)), ®->clkcr);
writel(readl(®->rint), ®->rint);
return 0;
}
static int mmc_update_phase(struct mmc *mmc)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
if (mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_1)
{
MMCDBG("mmc re-update_phase\n");
return mmc_update_clk(mmchost);
}
return 0;
}
#ifndef FPGA_PLATFORM
static int mmc_set_mclk(struct sunxi_mmc_host* mmchost, u32 clk_hz)
{
unsigned n, m, div, src, sclk_hz = 0;
unsigned rval;
//MMCINFO("%a: mod_clk %d\n", __FUNCTION__, clk_hz);
MMCDBG("%a: mod_clk %d\n", __FUNCTION__, clk_hz);
if (clk_hz <= 4000000) { //400000
src = 0;
sclk_hz = 24000000;
} else {
src = 1;
sclk_hz = sunxi_clock_get_pll6()*2*1000000; /*use 2x pll-per0 clock */
}
div = (2 * sclk_hz + clk_hz) / (2 * clk_hz);
div = (div==0) ? 1 : div;
if (div > 128) {
m = 1;
n = 0;
MMCINFO("%a: source clock is too high, clk %d, src %d!!!\n",
__FUNCTION__, clk_hz, sclk_hz);
} else if (div > 64) {
n = 3;
m = div >> 3;
} else if (div > 32) {
n = 2;
m = div >> 2;
} else if (div > 16) {
n = 1;
m = div >> 1;
} else {
n = 0;
m = div;
}
//rval = (1U << 31) | (src << 24) | (n << 16) | (m - 1);
rval = (src << 24) | (n << 16) | (m - 1);
writel(rval, mmchost->mclkbase);
return 0;
}
static unsigned mmc_get_mclk(struct sunxi_mmc_host* mmchost)
{
unsigned n, m, src, sclk_hz = 0;
unsigned rval = readl(mmchost->mclkbase);
m = rval & 0xf;
n = (rval>>16) & 0x3;
src = (rval>>24) & 0x3;
if (src == 0)
sclk_hz = 24000000;
else if (src == 1)
sclk_hz = sunxi_clock_get_pll6()*2*1000000; /* use 2x pll6 */
else if (src == 2) {
/*todo*/
} else {
MMCINFO("%a: wrong clock source %d\n",__func__, src);
}
return (sclk_hz / (1<<n) / (m+1) );
}
static unsigned mmc_config_delay(struct sunxi_mmc_host* mmchost)
{
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
unsigned rval = 0;
unsigned mode = mmchost->timing_mode;
unsigned spd_md, spd_md_bak, freq;
u8 odly, sdly, dsdly=0;
if (mode == SUNXI_MMC_TIMING_MODE_1)
{
spd_md = mmchost->tm1.cur_spd_md;
freq = mmchost->tm1.cur_freq;
if (mmchost->tm1.odly[spd_md*MAX_CLK_FREQ_NUM+freq] != 0xFF)
odly = mmchost->tm1.odly[spd_md*MAX_CLK_FREQ_NUM+freq];
else
odly = mmchost->tm1.def_odly[spd_md*MAX_CLK_FREQ_NUM+freq];
if (mmchost->tm1.sdly[spd_md*MAX_CLK_FREQ_NUM+freq] != 0xFF)
sdly = mmchost->tm1.sdly[spd_md*MAX_CLK_FREQ_NUM+freq];
else
sdly = mmchost->tm1.def_sdly[spd_md*MAX_CLK_FREQ_NUM+freq];
mmchost->tm1.cur_odly = odly;
mmchost->tm1.cur_sdly = sdly;
MMCDBG("%a: odly: %d sldy: %d\n", __FUNCTION__, odly, sdly);
rval = readl(®->drv_dl);
rval &= (~(0x3<<16));
rval |= (((odly&0x1)<<16) | ((odly&0x1)<<17));
writel(rval, ®->drv_dl);
rval = readl(®->ntsr);
rval &= (~(0x3<<4));
rval |= ((sdly&0x3)<<4);
writel(rval, ®->ntsr);
}
else if (mode == SUNXI_MMC_TIMING_MODE_3)
{
spd_md = mmchost->tm3.cur_spd_md;
freq = mmchost->tm3.cur_freq;
if (mmchost->tm3.odly[spd_md*MAX_CLK_FREQ_NUM+freq] != 0xFF)
odly = mmchost->tm3.odly[spd_md*MAX_CLK_FREQ_NUM+freq];
else
odly = mmchost->tm3.def_odly[spd_md*MAX_CLK_FREQ_NUM+freq];
if (mmchost->tm3.sdly[spd_md*MAX_CLK_FREQ_NUM+freq] != 0xFF)
sdly = mmchost->tm3.sdly[spd_md*MAX_CLK_FREQ_NUM+freq];
else
sdly = mmchost->tm3.def_sdly[spd_md*MAX_CLK_FREQ_NUM+freq];
mmchost->tm3.cur_odly = odly;
mmchost->tm3.cur_sdly = sdly;
MMCDBG("%a: odly: %d sldy: %d\n", __FUNCTION__, odly, sdly);
rval = readl(®->drv_dl);
rval &= (~(0x3<<16));
rval |= (((odly&0x1)<<16) | ((odly&0x1)<<17));
writel(rval, ®->drv_dl);
rval = readl(®->samp_dl);
rval &= (~SDXC_CfgDly);
rval |= ((sdly&SDXC_CfgDly) | SDXC_EnableDly);
writel(rval, ®->samp_dl);
}
else if (mode == SUNXI_MMC_TIMING_MODE_4)
{
spd_md = mmchost->tm4.cur_spd_md;
spd_md_bak = spd_md;
freq = mmchost->tm4.cur_freq;
if (spd_md == HS400)
spd_md = HS200_SDR104; /* use HS200's sdly for HS400's CMD line */
if (mmchost->tm4.sdly[spd_md*MAX_CLK_FREQ_NUM+freq] != 0xFF)
sdly = mmchost->tm4.sdly[spd_md*MAX_CLK_FREQ_NUM+freq];
else
sdly = mmchost->tm4.def_sdly[spd_md*MAX_CLK_FREQ_NUM+freq];
spd_md = spd_md_bak;
if (mmchost->tm4.odly[spd_md*MAX_CLK_FREQ_NUM+freq] != 0xFF)
odly = mmchost->tm4.odly[spd_md*MAX_CLK_FREQ_NUM+freq];
else
odly = mmchost->tm4.def_odly[spd_md*MAX_CLK_FREQ_NUM+freq];
mmchost->tm4.cur_odly = odly;
mmchost->tm4.cur_sdly = sdly;
rval = readl(®->drv_dl);
rval &= (~(0x3<<16));
rval |= (((odly&0x1)<<16) | ((odly&0x1)<<17));
writel(rval, ®->drv_dl);
rval = readl(®->samp_dl);
rval &= (~SDXC_CfgDly);
rval |= ((sdly&SDXC_CfgDly) | SDXC_EnableDly);
writel(rval, ®->samp_dl);
if (spd_md == HS400)
{
if (mmchost->tm4.dsdly[freq] != 0xFF)
dsdly = mmchost->tm4.dsdly[freq];
else
dsdly = mmchost->tm4.def_dsdly[freq];
mmchost->tm4.cur_dsdly = dsdly;
rval = readl(®->ds_dl);
rval &= (~SDXC_CfgDly);
rval |= ((dsdly&SDXC_CfgDly) | SDXC_EnableDly);
#ifdef FPGA_PLATFORM
rval &= (~0x7);
#endif
writel(rval, ®->ds_dl);
}
MMCDBG("%a: spd_md:%d, freq:%d, odly: %d; sdly: %d; dsdly: %d\n", __FUNCTION__, spd_md, freq, odly, sdly, dsdly);
}
return 0;
}
#endif /*FPGA_PLATFORM*/
static int mmc_config_clock_modex(struct sunxi_mmc_host* mmchost, unsigned clk)
{
unsigned rval = 0;
struct mmc *mmc = mmchost->mmc;
unsigned mode = mmchost->timing_mode;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
#ifndef FPGA_PLATFORM
unsigned freq_id;
/* disable mclk */
writel(0x0, mmchost->mclkbase);
MMCDBG("mmc %d mclkbase 0x%x\n", mmchost->mmc_no, readl(mmchost->mclkbase));
/* enable timing mode 1 */
if (mode == SUNXI_MMC_TIMING_MODE_1) {
rval = readl(®->ntsr);
rval |= (1<<31);
writel(rval, ®->ntsr);
MMCDBG("mmc %d rntsr 0x%x\n", mmchost->mmc_no, rval);
} else
writel(0x0, ®->ntsr);
/* configure clock */
if ((mode == SUNXI_MMC_TIMING_MODE_1)) {
if (mmc->speed_mode == HSDDR52_DDR50)
mmchost->mod_clk = clk * 4;
else
mmchost->mod_clk = clk * 2;
} else if (mode == SUNXI_MMC_TIMING_MODE_4) {
if ((mmc->speed_mode == HSDDR52_DDR50)
&& (mmc->bus_width == 8))
mmchost->mod_clk = clk * 4; /* 4xclk: DDR8(HS) */
else
mmchost->mod_clk = clk * 2; /* 2xclk: SDR 1/4/8; DDR4(HS); DDR8(HS400) */
}
mmc_set_mclk(mmchost, mmchost->mod_clk);
/* get mclk */
if ((mode == SUNXI_MMC_TIMING_MODE_1) || (mode == SUNXI_MMC_TIMING_MODE_3)) {
if (mmc->speed_mode == HSDDR52_DDR50)
mmc->clock = mmc_get_mclk(mmchost) / 4;
else
mmc->clock = mmc_get_mclk(mmchost) / 2;
} else if (mode == SUNXI_MMC_TIMING_MODE_4) {
if ((mmc->speed_mode == HSDDR52_DDR50)
&& (mmc->bus_width == 8))
mmc->clock = mmc_get_mclk(mmchost) / 4;
else
mmc->clock = mmc_get_mclk(mmchost) / 2;
}
mmchost->clock = mmc->clock; /* bankup current clock frequency at host */
MMCDBG("get round card clk %d, mod_clk %d\n", mmc->clock, mmchost->mod_clk);
/* re-enable mclk */
writel(readl(mmchost->mclkbase)|(1<<31),mmchost->mclkbase);
//MMCINFO("mmc %d mclkbase 0x%x\n", mmchost->mmc_no, readl(mmchost->mclkbase));
MMCDBG("mmc %d mclkbase 0x%x\n", mmchost->mmc_no, readl(mmchost->mclkbase));
/*
* CLKCREG[7:0]: divider
* CLKCREG[16]: on/off
* CLKCREG[17]: power save
*/
rval = readl(®->clkcr);
rval &= ~(0xFF);
if ((mode == SUNXI_MMC_TIMING_MODE_1)||(mode == SUNXI_MMC_TIMING_MODE_3)) {
if (mmc->speed_mode == HSDDR52_DDR50)
rval |= 0x1;
} else if (mode == SUNXI_MMC_TIMING_MODE_4) {
if ((mmc->speed_mode == HSDDR52_DDR50) && (mmc->bus_width == 8))
rval |= 0x1;
}
writel(rval, ®->clkcr);
if (mmc_update_clk(mmchost))
return -1;
/* configure delay for current frequency and speed mode */
if (clk <= 400000)
freq_id = CLK_400K;
else if (clk <= 26000000)
freq_id = CLK_25M;
else if (clk <= 52000000)
freq_id = CLK_50M;
else if (clk <= 100000000)
freq_id = CLK_100M;
else if (clk <= 150000000)
freq_id = CLK_150M;
else if (clk <= 200000000)
freq_id = CLK_200M;
else
freq_id = CLK_25M;
if (mode == SUNXI_MMC_TIMING_MODE_1) {
mmchost->tm1.cur_spd_md = mmchost->mmc->speed_mode;
mmchost->tm1.cur_freq = freq_id;
} else if (mode == SUNXI_MMC_TIMING_MODE_3) {
mmchost->tm3.cur_spd_md = mmchost->mmc->speed_mode;
mmchost->tm3.cur_freq = freq_id;
} else if (mode == SUNXI_MMC_TIMING_MODE_4) {
mmchost->tm4.cur_spd_md = mmchost->mmc->speed_mode;
mmchost->tm4.cur_freq = freq_id;
}
mmc_config_delay(mmchost);
#else
unsigned div, sclk= 24000000;
unsigned clk_2x = 0;
if (mode == SUNXI_MMC_TIMING_MODE_1)
{
div = (2 * sclk + clk) / (2 * clk);
rval = readl(®->clkcr) & (~0xff);
if (mmc->io_mode == MMC_MODE_DDR_52MHz)
rval |= 0x1;
else
rval |= div >> 1;
writel(rval, ®->clkcr);
rval = readl(®->ntsr);
rval |= (1<<31);
writel(rval, ®->ntsr);
MMCINFO("mmc %d ntsr 0x%x, ckcr 0x%x\n", mmchost->mmc_no,
readl(®->ntsr), readl(®->clkcr));
}
if ((mode == SUNXI_MMC_TIMING_MODE_3) || (mode == SUNXI_MMC_TIMING_MODE_4))
{
if (mode == SUNXI_MMC_TIMING_MODE_3) {
if (mmc->io_mode == MMC_MODE_DDR_52MHz)
clk_2x = clk << 2; //4xclk
else
clk_2x = clk << 1; //2xclk
} else if (mode == SUNXI_MMC_TIMING_MODE_4) {
if (mmc->io_mode == MMC_MODE_DDR_52MHz && mmc->bus_width == 8)
clk_2x = clk << 2; //4xclk: DDR8(HS)
else
clk_2x = clk << 1; //2xclk: SDR 1/4/8; DDR4(HS); DDR8(HS400)
}
div = (2 * sclk + clk_2x) / (2 * clk_2x);
rval = readl(®->clkcr) & (~0xff);
if (mmc->io_mode == MMC_MODE_DDR_52MHz)
rval |= 0x1;
else
rval |= div >> 1;
writel(rval, ®->clkcr);
}
#if 0
{
unsigned freq=0;
/* configure delay for current frequency and speed mode */
if (clk <= 400000)
freq = CLK_400K;
else if (clk <= 26000000)
freq = CLK_25M;
else if (clk <= 52000000)
freq = CLK_50M;
else if (clk <= 100000000)
freq = CLK_100M;
else if (clk <= 150000000)
freq = CLK_150M;
else if (clk <= 200000000)
freq = CLK_200M;
else
freq = CLK_25M;
if (mode == SUNXI_MMC_TIMING_MODE_1) {
mmchost->tm1.cur_spd_md = mmchost->mmc->speed_mode;
mmchost->tm1.cur_freq = freq;
} else if (mode == SUNXI_MMC_TIMING_MODE_3) {
mmchost->tm3.cur_spd_md = mmchost->mmc->speed_mode;;
mmchost->tm3.cur_freq = freq;
} else if (mode == SUNXI_MMC_TIMING_MODE_4) {
mmchost->tm4.cur_spd_md = mmchost->mmc->speed_mode;;
mmchost->tm4.cur_freq = freq;
}
mmc_config_delay(mmchost);
}
#endif
#endif
//dumphex32("ccmu", (char*)SUNXI_CCM_BASE, 0x100);
//dumphex32("gpio", (char*)SUNXI_PIO_BASE, 0x100);
//dumphex32("mmc", (char*)reg, 0x100);
return 0;
}
static int mmc_config_clock(struct sunxi_mmc_host* mmchost, unsigned clk)
{
//struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host* )mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
unsigned rval = 0;
/* disable card clock */
rval = readl(®->clkcr);
rval &= ~(1 << 16);
writel(rval, ®->clkcr);
if(mmc_update_clk(mmchost))
return -1;
if ((mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_1)
|| (mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_3)
|| (mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_4) )
mmc_config_clock_modex(mmchost, clk);
else {
MMCINFO("mmc %d wrong timing mode: 0x%x\n",
mmchost->mmc_no, mmchost->timing_mode);
return -1;
}
/* Re-enable card clock */
rval = readl(®->clkcr);
rval |= (0x1 << 16); //(3 << 16);
writel(rval, ®->clkcr);
if(mmc_update_clk(mmchost)){
MMCINFO("mmc %d re-enable clock failed\n",mmchost->mmc_no);
return -1;
}
return 0;
}
static void mmc_ddr_mode_onoff(struct mmc *mmc, int on)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
u32 rval = 0;
rval = readl(®->gctrl);
rval &= (~(1U << 10));
if (on) {
rval |= (1U << 10);
writel(rval, ®->gctrl);
MMCDBG("set %d rgctrl 0x%x to enable ddr mode\n", mmchost->mmc_no, readl(®->gctrl));
} else {
writel(rval, ®->gctrl);
MMCDBG("set %d rgctrl 0x%x to disable ddr mode\n", mmchost->mmc_no, readl(®->gctrl));
}
}
static void mmc_hs400_mode_onoff(struct mmc *mmc, int on)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
u32 rval = 0;
if (mmchost->mmc_no != 2) {
return ;
}
rval = readl(®->dsbd);
rval &= (~(1 << 31));
if (on) {
rval |= (1 << 31);
writel(rval, ®->dsbd);
MMCDBG("set %d dsbd 0x%x to enable hs400 mode\n", mmchost->mmc_no, readl(®->dsbd));
} else {
writel(rval, ®->dsbd);
MMCDBG("set %d dsbd 0x%x to disable hs400 mode\n", mmchost->mmc_no, readl(®->dsbd));
}
}
static void mmc_set_ddr_mode(struct mmc *mmc)
{
/* set ddr mode */
if (mmc->speed_mode == HSDDR52_DDR50) {
mmc_ddr_mode_onoff(mmc, 1);
mmc_hs400_mode_onoff(mmc, 0);
} else if (mmc->speed_mode == HS400) {
mmc_ddr_mode_onoff(mmc, 0);
mmc_hs400_mode_onoff(mmc, 1);
} else {
mmc_ddr_mode_onoff(mmc, 0);
mmc_hs400_mode_onoff(mmc, 0);
}
}
static int mmc_calibrate_delay_unit(struct sunxi_mmc_host* mmchost)
{
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
unsigned rval = 0;
#ifndef FPGA_PLATFORM
unsigned result = 0;
#endif /*FPGA_PLATFORM*/
MMCINFO("start %a, don't access device...\n", __FUNCTION__);
/* close card clock */
rval = readl(®->clkcr);
rval &= ~(1 << 16);
writel(rval, ®->clkcr);
if(mmc_update_clk(mmchost))
return -1;
/* set card clock to 100MHz */
if ((mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_1)
|| (mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_3)
|| (mmchost->timing_mode == SUNXI_MMC_TIMING_MODE_4) )
mmc_config_clock_modex(mmchost, 100000000);
else {
MMCINFO("%a: mmc %d wrong timing mode: 0x%x\n",
__FUNCTION__, mmchost->mmc_no, mmchost->timing_mode);
return -1;
}
#ifndef FPGA_PLATFORM
/* start carlibrate delay unit */
writel(0xA0, ®->samp_dl);
writel(0x0, ®->samp_dl);
rval = SDXC_StartCal;
writel(rval, ®->samp_dl);
while (!(readl(®->samp_dl) & SDXC_CalDone));
if ((mmchost->mmc_no == 2) || (mmchost->mmc_no == 3)) {
writel(0xA0, ®->ds_dl);
writel(0x0, ®->ds_dl);
rval = SDXC_StartCal;
writel(rval, ®->ds_dl);
while (!(readl(®->ds_dl) & SDXC_CalDone));
}
/* update result */
rval = readl(®->samp_dl);
result = (rval & SDXC_CalDly) >> 8;
MMCDBG("ds_dl result: 0x%x\n", result);
/* 10ns= 10*1000 ps, mod_clk is 5ns */
if (result) {
rval = 5000 / result;
mmchost->tm3.sdly_unit_ps = rval;
mmchost->tm3.dly_calibrate_done = 1;
mmchost->tm4.sdly_unit_ps = rval;
MMCINFO("delay chain cal done, sample: %d(ps)\n", mmchost->tm3.sdly_unit_ps);
} else {
MMCINFO("%a: cal sample delay fail\n", __FUNCTION__);
}
if (mmchost->mmc_no == 2) {
rval = readl(®->ds_dl);
result = (rval & SDXC_CalDly) >> 8;
MMCDBG("ds_dl result: 0x%x\n", result);
if (result) {
rval = 5000 / result;
mmchost->tm4.dsdly_unit_ps = rval;
mmchost->tm4.dly_calibrate_done = 1;
MMCINFO("delay chain cal done, ds: %d(ps)\n", mmchost->tm4.dsdly_unit_ps);
} else {
MMCINFO("%a: cal data strobe delay fail\n", __FUNCTION__);
}
}
#endif /* FPGA_PLATFORM */
return 0;
}
static int mmc_core_init(struct mmc *mmc)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
/* Reset controller */
writel(0x7, ®->gctrl); /*0x40000007*/
while(readl(®->gctrl)&0x7);
/* release eMMC reset signal */
writel(1, ®->hwrst);
writel(0, ®->hwrst);
udelay(1000);
writel(1, ®->hwrst);
udelay(1000);
#if 1
#define SMC_DATA_TIMEOUT 0xffffffU
#define SMC_RESP_TIMEOUT 0xff
#else
#define SMC_DATA_TIMEOUT 0x1ffffU
#define SMC_RESP_TIMEOUT 0x2
#endif
writel((SMC_DATA_TIMEOUT<<8)|SMC_RESP_TIMEOUT, ®->timeout); //Set Data & Response Timeout Value
writel((512<<16)|(1U<<2)|(1U<<0), ®->thldc);
writel(3, ®->csdc);
writel(0xdeb, ®->dbgc);
mmc_calibrate_delay_unit(mmchost);
return 0;
}
static void mmc_set_ios(struct mmc *mmc)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
MMCDBG("mmc %d ios: bus: %d, clock: %d, speed mode: %d\n", \
mmchost->mmc_no,mmc->bus_width, mmc->clock, mmc->speed_mode);
/* change clock */
if (mmc->clock && mmc_config_clock((struct sunxi_mmc_host*)mmc->priv, mmc->clock)) {
MMCINFO("[mmc]: mmc %d update clock failed\n",mmchost->mmc_no);
mmchost->fatal_err = 1;
return;
}
/* for card2, if clock frequency is greater than 100MHz, increase gpio dirver strength */
#if 0
if (mmc->clock >= 100000000) {
writel(0xFFFFFFFF, 0x01c2085C);
writel(0xFFFFFFFF, 0x01c20860);
} else {
writel(0x55555555, 0x01c2085C);
writel(0x55555555, 0x01c20860);
}
#endif
/* Change bus width */
if (mmc->bus_width == 8)
writel(2, ®->width);
else if (mmc->bus_width == 4)
writel(1, ®->width);
else
writel(0, ®->width);
MMCDBG("host bus width register 0x%x\n", readl(®->width));
/* set ddr mode */
#if 0
if (mmc->speed_mode == HSDDR52_DDR50) {
mmc_ddr_mode_onoff(mmc, 1);
mmc_hs400_mode_onoff(mmc, 0);
} else if (mmc->speed_mode == HS400) {
mmc_ddr_mode_onoff(mmc, 0);
mmc_hs400_mode_onoff(mmc, 1);
} else {
mmc_ddr_mode_onoff(mmc, 0);
mmc_hs400_mode_onoff(mmc, 0);
}
#else //modified by Leson 20150728
mmc_set_ddr_mode(mmc);
#endif
}
static int mmc_save_regs(struct sunxi_mmc_host* mmchost)
{
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
struct mmc_reg_v4p1 *reg_bak = (struct mmc_reg_v4p1 *)mmchost->reg_bak;
reg_bak->gctrl = readl(®->gctrl );
reg_bak->clkcr = readl(®->clkcr );
reg_bak->timeout = readl(®->timeout);
reg_bak->width = readl(®->width );
reg_bak->imask = readl(®->imask );
reg_bak->ftrglevel = readl(®->ftrglevel);
reg_bak->dbgc = readl(®->dbgc );
reg_bak->csdc = readl(®->csdc );
reg_bak->ntsr = readl(®->ntsr );
reg_bak->hwrst = readl(®->hwrst );
reg_bak->dmac = readl(®->dmac );
reg_bak->idie = readl(®->idie );
reg_bak->thldc = readl(®->thldc );
reg_bak->dsbd = readl(®->dsbd );
reg_bak->drv_dl = readl(®->drv_dl );
reg_bak->samp_dl = readl(®->samp_dl);
reg_bak->ds_dl = readl(®->ds_dl );
return 0;
}
static int mmc_restore_regs(struct sunxi_mmc_host* mmchost)
{ struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
struct mmc_reg_v4p1 *reg_bak = (struct mmc_reg_v4p1 *)mmchost->reg_bak;
writel(reg_bak->gctrl , ®->gctrl );
writel(reg_bak->clkcr , ®->clkcr );
writel(reg_bak->timeout , ®->timeout);
writel(reg_bak->width , ®->width );
writel(reg_bak->imask , ®->imask );
writel(reg_bak->ftrglevel , ®->ftrglevel);
if (reg_bak->dbgc)
writel(0xdeb, ®->dbgc);
writel(reg_bak->csdc , ®->csdc );
writel(reg_bak->ntsr , ®->ntsr );
writel(reg_bak->hwrst , ®->hwrst );
writel(reg_bak->dmac , ®->dmac );
writel(reg_bak->idie , ®->idie );
writel(reg_bak->thldc , ®->thldc );
writel(reg_bak->dsbd , ®->dsbd );
writel(reg_bak->drv_dl , ®->drv_dl );
writel(reg_bak->samp_dl , ®->samp_dl);
writel(reg_bak->ds_dl , ®->ds_dl );
return 0;
}
static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
unsigned i;
unsigned byte_cnt = data->blocksize * data->blocks;
unsigned *buff;
unsigned timeout = 1000;
if (data->flags & MMC_DATA_READ) {
buff = (unsigned int *)data->dest;
for (i=0; i<(byte_cnt>>2); i++) {
while(--timeout && (readl(®->status)&(1 << 2))){
mdelay(1);
}
if (timeout <= 0)
goto out;
buff[i] = readl(mmchost->database);
timeout = 1000;
}
} else {
buff = (unsigned int *)data->src;
for (i=0; i<(byte_cnt>>2); i++) {
while(--timeout && (readl(®->status)&(1 << 3))){
mdelay(1);
}
if (timeout <= 0)
goto out;
writel(buff[i], mmchost->database);
timeout = 1000;
}
}
out:
if (timeout <= 0){
MMCINFO("transfer by cpu failed\n");
return -1;
}
return 0;
}
static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
struct mmc_des_v4p1 *pdes =(struct mmc_des_v4p1 *)mmchost->pdes;
unsigned byte_cnt = data->blocksize * data->blocks;
unsigned char *buff;
unsigned des_idx = 0;
unsigned buff_frag_num = 0;
unsigned remain;
unsigned i, rval;
buff = data->flags & MMC_DATA_READ ?
(unsigned char *)data->dest : (unsigned char *)data->src;
buff_frag_num = byte_cnt >> SDXC_DES_NUM_SHIFT;
remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN-1);
if (remain)
buff_frag_num ++;
else
remain = SDXC_DES_BUFFER_MAX_LEN;
//flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
OSAL_CacheRangeFlush(buff, (UINT32)byte_cnt, CACHE_CLEAN_FLUSH_D_CACHE_REGION);
for (i=0; i < buff_frag_num; i++, des_idx++) {
memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_des_v4p1));
pdes[des_idx].des_chain = 1;
pdes[des_idx].own = 1;
pdes[des_idx].dic = 1;
if (buff_frag_num > 1 && i != buff_frag_num-1)
pdes[des_idx].data_buf1_sz = SDXC_DES_BUFFER_MAX_LEN;
else
pdes[des_idx].data_buf1_sz = remain;
pdes[des_idx].buf_addr_ptr1 = (ulong)buff + i * SDXC_DES_BUFFER_MAX_LEN;
if (i==0)
pdes[des_idx].first_des = 1;
if (i == buff_frag_num-1) {
pdes[des_idx].dic = 0;
pdes[des_idx].last_des = 1;
pdes[des_idx].end_of_ring = 1;
pdes[des_idx].buf_addr_ptr2 = 0;
} else {
pdes[des_idx].buf_addr_ptr2 = (ulong)&pdes[des_idx+1];
}
MMCDBG("frag %d, remain %d, des[%d](%08x): "
"[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n",
i, remain, des_idx, (u32)&pdes[des_idx],
(u32)((u32*)&pdes[des_idx])[0], (u32)((u32*)&pdes[des_idx])[1],
(u32)((u32*)&pdes[des_idx])[2], (u32)((u32*)&pdes[des_idx])[3]);
}
//flush_cache((unsigned long)pdes, sizeof(struct mmc_des_v4p1) * (des_idx+1));
OSAL_CacheRangeFlush(pdes, (UINT32)(sizeof(struct mmc_des_v4p1) * (des_idx+1)), CACHE_CLEAN_FLUSH_D_CACHE_REGION);
__asm("DSB");
__asm("ISB");
/*
* GCTRLREG
* GCTRL[2] : DMA reset
* GCTRL[5] : DMA enable
*
* IDMACREG
* IDMAC[0] : IDMA soft reset
* IDMAC[1] : IDMA fix burst flag
* IDMAC[7] : IDMA on
*
* IDIECREG
* IDIE[0] : IDMA transmit interrupt flag
* IDIE[1] : IDMA receive interrupt flag
*/
rval = readl(®->gctrl);
writel(rval|(1 << 5)|(1 << 2), ®->gctrl); /* dma enable */
writel((1 << 0), ®->dmac); /* idma reset */
while(readl(®->dmac)& 0x1) {}; /* wait idma reset done */
writel((1 << 1) | (1 << 7), ®->dmac); /* idma on */
rval = readl(®->idie) & (~3);
if (data->flags & MMC_DATA_WRITE)
rval |= (1 << 0);
else
rval |= (1 << 1);
writel(rval, ®->idie);
writel((unsigned long)pdes, ®->dlba);
if (mmchost->mmc_no == 2)
writel((3U<<28)|(15U<<16)|240, ®->ftrglevel); /* burst-16, rx/tx trigger level=15/240 */
else
writel((2U<<28)|(7U<<16)|248, ®->ftrglevel); /* burst-8, rx/tx trigger level=7/248 */
return 0;
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
struct mmc_reg_v4p1 *reg = (struct mmc_reg_v4p1 *)mmchost->reg;
unsigned int cmdval = 0x80000000;
signed int timeout = 0;
int error = 0;
unsigned int status = 0;
unsigned int usedma = 0;
unsigned int bytecnt = 0;
if (mmchost->fatal_err) {
MMCINFO("mmc %d Found fatal err,so no send cmd\n",mmchost->mmc_no);
return -1;
}
if (cmd->resp_type & MMC_RSP_BUSY)
MMCDBG("mmc %d mmc cmd %d check rsp busy\n", mmchost->mmc_no,cmd->cmdidx);
if ((cmd->cmdidx == 12)&&!(cmd->flags&MMC_CMD_MANUAL)){
MMCDBG("note we don't send stop cmd,only check busy here\n");
timeout = 500*1000;
do {
status = readl(®->status);
if (!timeout--) {
error = -1;
MMCINFO("mmc %d cmd12 busy timeout\n",mmchost->mmc_no);
goto out;
}
udelay(1);
} while (status & (1 << 9));
return 0;
}
/*
* CMDREG
* CMD[5:0] : Command index
* CMD[6] : Has response
* CMD[7] : Long response
* CMD[8] : Check response CRC
* CMD[9] : Has data
* CMD[10] : Write
* CMD[11] : Steam mode
* CMD[12] : Auto stop
* CMD[13] : Wait previous over
* CMD[14] : About cmd
* CMD[15] : Send initialization
* CMD[21] : Update clock
* CMD[31] : Load cmd
*/
if (!cmd->cmdidx)
cmdval |= (1 << 15);
if (cmd->resp_type & MMC_RSP_PRESENT)
cmdval |= (1 << 6);
if (cmd->resp_type & MMC_RSP_136)
cmdval |= (1 << 7);
if (cmd->resp_type & MMC_RSP_CRC)
cmdval |= (1 << 8);
if (data) {
if ((ulong)data->dest & 0x3) {
MMCINFO("mmc %d dest is not 4 byte align: 0x%08lx\n",mmchost->mmc_no, (ulong)data->dest);
error = -1;
goto out;
}
cmdval |= (1 << 9) | (1 << 13);
if (data->flags & MMC_DATA_WRITE)