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Recompiler Ops.c
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Recompiler Ops.c
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/*
* RSP Compiler plug in for Project 64 (A Nintendo 64 emulator).
*
* (c) Copyright 2001 jabo (jabo@emulation64.com) and
* zilmar (zilmar@emulation64.com)
*
* pj64 homepage: www.pj64.net
*
* Permission to use, copy, modify and distribute Project64 in both binary and
* source form, for non-commercial purposes, is hereby granted without fee,
* providing that this license information and copyright notice appear with
* all copies and any derived work.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event shall the authors be held liable for any damages
* arising from the use of this software.
*
* Project64 is freeware for PERSONAL USE only. Commercial users should
* seek permission of the copyright holders first. Commercial use includes
* charging money for Project64 or software derived from Project64.
*
* The copyright holders request that bug fixes and improvements to the code
* should be forwarded to them so if they want them.
*
*/
#include <windows.h>
#include <stdio.h>
#include "RSP.h"
#include "CPU.h"
#include "Interpreter CPU.h"
#include "Interpreter Ops.h"
#include "Recompiler CPU.h"
#include "RSP Command.h"
#include "RSP Registers.h"
#include "memory.h"
#include "dma.h"
#include "log.h"
#include "x86.h"
#include "Profiling.h"
UWORD32 Recp, RecpResult, SQroot, SQrootResult;
DWORD ESP_RegSave = 0, EBP_RegSave = 0;
DWORD BranchCompare = 0;
/* align option affects: sw, lh, sh */
/* align option affects: lrv, ssv, lsv */
#define Compile_Immediates /* ADDI, ADDIU, ANDI, ORI, XORI, LUI */
#define Compile_GPRLoads /* LB, LH, LW, LBU, LHU */
#define Compile_GPRStores /* SB, SH, SW */
#define Compile_Special /* SLL, SRL, SRA, SRLV */
/* XOR, OR, AND, SUB, SUBU, ADDU, ADD, SLT */
#define Compile_Cop0
#define Compile_Cop2
#define RSP_VectorMuls
#define RSP_VectorLoads
#define RSP_VectorMisc
#ifdef RSP_VectorMuls
# define CompileVmulf /* Verified 12/17/2000 - Jabo */
# define CompileVmacf /* Rewritten & Verified 12/15/2000 - Jabo */
# define CompileVmudm /* Verified 12/17/2000 - Jabo */
# define CompileVmudh /* Verified 12/17/2000 - Jabo */
# define CompileVmudn /* Verified 12/17/2000 - Jabo */
# define CompileVmudl /* Verified 12/17/2000 - Jabo */
# define CompileVmadl
# define CompileVmadm /* Verified 12/17/2000 - Jabo */
# define CompileVmadh /* Verified 12/15/2000 - Jabo */
# define CompileVmadn /* Verified 12/17/2000 - Jabo */
#endif
#ifdef RSP_VectorMisc
# define CompileVrsqh
# define CompileVrcph
# define CompileVsaw /* Verified 12/17/2000 - Jabo */
# define CompileVabs /* Verified 12/15/2000 - Jabo */
# define CompileVmov /* Verified 12/17/2000 - Jabo */
# define CompileVxor /* Verified 12/17/2000 - Jabo */
# define CompileVor /* Verified 12/17/2000 - Jabo */
# define CompileVand /* Verified 12/17/2000 - Jabo */
# define CompileVsub /* Verified 12/17/2000 - Jabo (watch flags) */
# define CompileVadd /* Verified 12/17/2000 - Jabo (watch flags) */
# define CompileVaddc
# define CompileVsubc
# define CompileVmrg
#endif
#ifdef RSP_VectorLoads
# define CompileSqv /* Verified 12/17/2000 - Jabo */
# define CompileSdv /* Verified 12/17/2000 - Jabo */
# define CompileSsv /* Verified 12/17/2000 - Jabo */
# define CompileLrv /* Rewritten & Verified 12/17/2000 - Jabo */
# define CompileLqv /* Verified 12/17/2000 - Jabo */
# define CompileLdv /* Verified 12/17/2000 - Jabo */
# define CompileLsv /* Verified 12/17/2000 - Jabo */
# define CompileLlv /* Verified 12/17/2000 - Jabo */
# define CompileSlv
#endif
void Branch_AddRef(DWORD Target, DWORD * X86Loc) {
if (CurrentBlock.ResolveCount >= 150) {
CompilerWarning("Out of branch reference space");
} else {
BYTE * KnownCode = *(JumpTable + (Target >> 2));
if (KnownCode == NULL) {
DWORD i = CurrentBlock.ResolveCount;
CurrentBlock.BranchesToResolve[i].TargetPC = Target;
CurrentBlock.BranchesToResolve[i].X86JumpLoc = X86Loc;
CurrentBlock.ResolveCount += 1;
} else {
CPU_Message(" (static jump to %X)", KnownCode);
x86_SetBranch32b((DWORD*)X86Loc, (DWORD*)KnownCode);
}
}
}
void Cheat_r4300iOpcode ( void * FunctAddress, char * FunctName) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
MoveConstToVariable(RSPOpC.Hex, &RSPOpC.Hex, "RSPOpC.Hex" );
Call_Direct(FunctAddress, FunctName);
}
void Cheat_r4300iOpcodeNoMessage( void * FunctAddress, char * FunctName) {
MoveConstToVariable(RSPOpC.Hex, &RSPOpC.Hex, "RSPOpC.Hex" );
Call_Direct(FunctAddress, FunctName);
}
void x86_SetBranch8b(void * JumpByte, void * Destination) {
/* calculate 32-bit relative offset */
signed int n = (BYTE*)Destination - ((BYTE*)JumpByte + 1);
/* check limits, no pun intended */
if (n > 0x80 || n < -0x7F) {
CompilerWarning("FATAL: Jump out of 8b range %i (PC = %04X)", n, CompilePC);
} else
*(BYTE*)(JumpByte) = (BYTE)n;
}
void x86_SetBranch32b(void * JumpByte, void * Destination) {
*(DWORD*)(JumpByte) = (DWORD)((BYTE*)Destination - (BYTE*)((DWORD*)JumpByte + 1));
}
void BreakPoint() {
CPU_Message(" int 3");
*(RecompPos++) = 0xCC;
}
void CompileBranchExit(DWORD TargetPC, DWORD ContinuePC)
{
DWORD * X86Loc = NULL;
NextInstruction = FINISH_SUB_BLOCK;
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchEqual", 0);
X86Loc = (DWORD*)(RecompPos - 4);
MoveConstToVariable(ContinuePC,PrgCount,"RSP PC");
Ret();
CPU_Message("BranchEqual:");
x86_SetBranch32b(X86Loc, RecompPos);
MoveConstToVariable(TargetPC,PrgCount,"RSP PC");
Ret();
}
/************************* OpCode functions *************************/
void Compile_SPECIAL ( void ) {
((void (*)()) RSP_Special[ RSPOpC.funct ])();
}
void Compile_REGIMM ( void ) {
((void (*)()) RSP_RegImm[ RSPOpC.rt ])();
}
void Compile_J ( void ) {
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
JmpLabel32 ( "BranchToJump", 0 );
Branch_AddRef((RSPOpC.target << 2) & 0xFFC, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
} else if ( NextInstruction == DELAY_SLOT_EXIT_DONE ) {
MoveConstToVariable((RSPOpC.target << 2) & 0xFFC,PrgCount,"RSP PC");
NextInstruction = FINISH_SUB_BLOCK;
Ret();
} else {
CompilerWarning("J error\nWeird Delay Slot.\n\nNextInstruction = %X\nEmulation will now stop", NextInstruction);
BreakPoint();
}
}
void Compile_JAL ( void ) {
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
MoveConstToVariable(CompilePC + 8, &RSP_GPR[31].UW, "RA.W");
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
// before we branch quickly update our stats
if (Profiling && IndvidualBlock)
{
char Str[40];
sprintf(Str,"%03X",(RSPOpC.target << 2) & 0xFFC);
Push(x86_EAX);
PushImm32(Str,*PrgCount);
Call_Direct(StartTimer, "StartTimer");
AddConstToX86Reg(x86_ESP, 4);
Pop(x86_EAX);
}
JmpLabel32 ( "BranchToJump", 0 );
Branch_AddRef((RSPOpC.target << 2) & 0xFFC, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
} else if ( NextInstruction == DELAY_SLOT_EXIT_DONE ) {
MoveConstToVariable((RSPOpC.target << 2) & 0xFFC,PrgCount,"RSP PC");
NextInstruction = FINISH_SUB_BLOCK;
Ret();
} else {
CompilerWarning("J error\nWeird Delay Slot.\n\nNextInstruction = %X\nEmulation will now stop", NextInstruction);
BreakPoint();
}
}
void Compile_BEQ ( void ) {
static BOOL bDelayAffect;
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rs == 0 && RSPOpC.rt == 0) {
NextInstruction = DO_DELAY_SLOT;
return;
}
bDelayAffect = DelaySlotAffectBranch(CompilePC);
if (FALSE == bDelayAffect) {
NextInstruction = DO_DELAY_SLOT;
return;
}
if (RSPOpC.rt == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
} else if (RSPOpC.rs == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt),x86_EAX);
CompX86regToVariable(x86_EAX,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
}
SetzVariable(&BranchCompare, "BranchCompare");
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
if (RSPOpC.rs == 0 && RSPOpC.rt == 0) {
JmpLabel32 ( "BranchToJump", 0 );
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
return;
}
if (FALSE == bDelayAffect) {
if (RSPOpC.rt == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
} else if (RSPOpC.rs == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt),x86_EAX);
CompX86regToVariable(x86_EAX,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
}
JeLabel32("BranchEqual", 0);
} else {
/* take a look at the branch compare variable */
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchEqual", 0);
}
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
} else if ( NextInstruction == DELAY_SLOT_EXIT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
CompileBranchExit(Target, CompilePC + 8);
} else {
CompilerWarning("BEQ error\nWeird Delay Slot.\n\nNextInstruction = %X\nEmulation will now stop", NextInstruction);
BreakPoint();
}
}
void Compile_BNE ( void ) {
static BOOL bDelayAffect;
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rs == 0 && RSPOpC.rt == 0) {
NextInstruction = DO_DELAY_SLOT;
return;
}
bDelayAffect = DelaySlotAffectBranch(CompilePC);
if (FALSE == bDelayAffect) {
NextInstruction = DO_DELAY_SLOT;
return;
}
if (RSPOpC.rt == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
} else if (RSPOpC.rs == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt),x86_EAX);
CompX86regToVariable(x86_EAX,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
}
SetnzVariable(&BranchCompare, "BranchCompare");
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
if (RSPOpC.rs == 0 && RSPOpC.rt == 0) {
NextInstruction = FINISH_SUB_BLOCK;
return;
}
if (FALSE == bDelayAffect) {
if (RSPOpC.rt == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
} else if (RSPOpC.rs == 0) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W,GPR_Name(RSPOpC.rt),x86_EAX);
CompX86regToVariable(x86_EAX,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
}
JneLabel32("BranchNotEqual", 0);
} else {
/* take a look at the branch compare variable */
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchNotEqual", 0);
}
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
} else if ( NextInstruction == DELAY_SLOT_EXIT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
CompileBranchExit(Target, CompilePC + 8);
} else {
CompilerWarning("BNE error\nWeird Delay Slot.\n\nNextInstruction = %X\nEmulation will now stop", NextInstruction);
BreakPoint();
}
}
void Compile_BLEZ ( void ) {
static BOOL bDelayAffect;
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rs == 0) {
NextInstruction = DO_DELAY_SLOT;
return;
}
bDelayAffect = DelaySlotAffectBranch(CompilePC);
if (FALSE == bDelayAffect) {
NextInstruction = DO_DELAY_SLOT;
return;
}
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
SetleVariable(&BranchCompare, "BranchCompare");
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
if (RSPOpC.rs == 0) {
JmpLabel32 ( "BranchToJump", 0 );
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
return;
}
if (FALSE == bDelayAffect) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JleLabel32("BranchLessEqual", 0);
} else {
/* take a look at the branch compare variable */
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchLessEqual", 0);
}
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
} else if ( NextInstruction == DELAY_SLOT_EXIT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
CompileBranchExit(Target, CompilePC + 8);
} else {
CompilerWarning("BLEZ error\nWeird Delay Slot.\n\nNextInstruction = %X\nEmulation will now stop", NextInstruction);
BreakPoint();
}
}
void Compile_BGTZ ( void ) {
static BOOL bDelayAffect;
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rs == 0) {
NextInstruction = DO_DELAY_SLOT;
return;
}
bDelayAffect = DelaySlotAffectBranch(CompilePC);
if (FALSE == bDelayAffect) {
NextInstruction = DO_DELAY_SLOT;
return;
}
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
SetgVariable(&BranchCompare, "BranchCompare");
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
if (RSPOpC.rs == 0) {
NextInstruction = FINISH_SUB_BLOCK;
return;
}
if (FALSE == bDelayAffect) {
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JgLabel32("BranchGreater", 0);
} else {
/* take a look at the branch compare variable */
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchGreater", 0);
}
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
NextInstruction = FINISH_SUB_BLOCK;
} else if ( NextInstruction == DELAY_SLOT_EXIT_DONE ) {
DWORD Target = (CompilePC + ((short)RSPOpC.offset << 2) + 4) & 0xFFC;
CompileBranchExit(Target, CompilePC + 8);
} else {
CompilerWarning("BGTZ error\nWeird Delay Slot.\n\nNextInstruction = %X\nEmulation will now stop", NextInstruction);
BreakPoint();
}
}
void Compile_ADDI ( void ) {
int Immediate = (short)RSPOpC.immediate;
#ifndef Compile_Immediates
Cheat_r4300iOpcode(RSP_Opcode_ADDI,"RSP_Opcode_ADDI"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rt == 0) return;
if (RSPOpC.rt == RSPOpC.rs) {
AddConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else if (RSPOpC.rs == 0) {
MoveConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else if (IsRegConst(RSPOpC.rs) && 1) {
MoveConstToVariable(MipsRegConst(RSPOpC.rs) + Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rs].UW, GPR_Name(RSPOpC.rs), x86_EAX);
if (Immediate != 0) {
AddConstToX86Reg(x86_EAX, Immediate);
}
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
}
void Compile_ADDIU ( void ) {
int Immediate = (short)RSPOpC.immediate;
#ifndef Compile_Immediates
Cheat_r4300iOpcode(RSP_Opcode_ADDIU,"RSP_Opcode_ADDIU"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rt == 0) return;
if (RSPOpC.rt == RSPOpC.rs) {
AddConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else if (RSPOpC.rs == 0) {
MoveConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rs].UW, GPR_Name(RSPOpC.rs), x86_EAX);
AddConstToX86Reg(x86_EAX, Immediate);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
}
void Compile_SLTI ( void ) {
Cheat_r4300iOpcode(RSP_Opcode_SLTI,"RSP_Opcode_SLTI");
}
void Compile_SLTIU ( void ) {
Cheat_r4300iOpcode(RSP_Opcode_SLTIU,"RSP_Opcode_SLTIU");
}
void Compile_ANDI ( void ) {
int Immediate = (unsigned short)RSPOpC.immediate;
#ifndef Compile_Immediates
Cheat_r4300iOpcode(RSP_Opcode_ANDI,"RSP_Opcode_ANDI"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rt == 0) return;
if (RSPOpC.rt == RSPOpC.rs) {
AndConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else if (RSPOpC.rs == 0) {
MoveConstToVariable(0, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rs].UW, GPR_Name(RSPOpC.rs), x86_EAX);
AndConstToX86Reg(x86_EAX, Immediate);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
}
void Compile_ORI ( void ) {
int Immediate = (unsigned short)RSPOpC.immediate;
#ifndef Compile_Immediates
Cheat_r4300iOpcode(RSP_Opcode_ORI,"RSP_Opcode_ORI"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rt == 0) return;
if (RSPOpC.rt == RSPOpC.rs) {
OrConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else if (RSPOpC.rs == 0) {
MoveConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rs].UW, GPR_Name(RSPOpC.rs), x86_EAX);
if (Immediate != 0) {
OrConstToX86Reg(Immediate, x86_EAX);
}
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
}
void Compile_XORI ( void ) {
int Immediate = (unsigned short)RSPOpC.immediate;
#ifndef Compile_Immediates
Cheat_r4300iOpcode(RSP_Opcode_XORI,"RSP_Opcode_XORI"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rt == 0) return;
if (RSPOpC.rt == RSPOpC.rs) {
XorConstToVariable(&RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt), Immediate);
} else if (RSPOpC.rs == 0) {
MoveConstToVariable(Immediate, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rs].UW, GPR_Name(RSPOpC.rs), x86_EAX);
if (Immediate != 0) {
XorConstToX86Reg(x86_EAX, Immediate);
}
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
}
void Compile_LUI ( void ) {
int constant = (short)RSPOpC.offset << 16;
#ifndef Compile_Immediates
Cheat_r4300iOpcode(RSP_Opcode_LUI,"RSP_Opcode_LUI"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rt == 0) return;
MoveConstToVariable(constant, &RSP_GPR[RSPOpC.rt].W, GPR_Name(RSPOpC.rt));
}
void Compile_COP0 (void) {
((void (*)()) RSP_Cop0[ RSPOpC.rs ])();
}
void Compile_COP2 (void) {
((void (*)()) RSP_Cop2[ RSPOpC.rs ])();
}
void Compile_LB ( void ) {
int Offset = (short)RSPOpC.offset;
#ifndef Compile_GPRLoads
Cheat_r4300iOpcode(RSP_Opcode_LB,"RSP_Opcode_LB"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
XorConstToX86Reg(x86_EBX, 3);
AndConstToX86Reg(x86_EBX, 0x0fff);
MoveSxN64MemToX86regByte(x86_EAX, x86_EBX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
void Compile_LH ( void ) {
int Offset = (short)RSPOpC.offset;
BYTE * Jump[2];
#ifndef Compile_GPRLoads
Cheat_r4300iOpcode(RSP_Opcode_LH,"RSP_Opcode_LH"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (IsRegConst(RSPOpC.base) == TRUE) {
DWORD Addr = (MipsRegConst(RSPOpC.base) + Offset) ^ 2;
Addr &= 0xfff;
if ((Addr & 1) != 0) {
CompilerWarning("Unaligned LH at constant address PC = %04X", CompilePC);
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_LH,"RSP_Opcode_LH");
} else {
char Address[32];
sprintf(Address, "Dmem + %Xh", Addr);
MoveSxVariableToX86regHalf(RSPInfo.DMEM + Addr, Address, x86_EAX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
return;
}
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
AndConstToX86Reg(x86_EBX, 0x0fff);
TestConstToX86Reg(1, x86_EBX);
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
x86_SetBranch32b(Jump[0], RecompPos);
X86BreakPoint(__FILE__,__LINE__);
JmpLabel32("Done", 0);
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
XorConstToX86Reg(x86_EBX, 2);
MoveSxN64MemToX86regHalf(x86_EAX, x86_EBX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
CPU_Message(" Done:");
x86_SetBranch32b(Jump[1], RecompPos);
}
void Compile_LW ( void ) {
int Offset = (short)RSPOpC.offset;
BYTE * Jump[2];
#ifndef Compile_GPRLoads
Cheat_r4300iOpcode(RSP_Opcode_LW,"RSP_Opcode_LW"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (IsRegConst(RSPOpC.base) == TRUE) {
DWORD Addr = (MipsRegConst(RSPOpC.base) + Offset) & 0xfff;
if ((Addr & 3) != 0) {
CompilerWarning("Unaligned LW at constant address PC = %04X", CompilePC);
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_LW,"RSP_Opcode_LW");
} else {
char Address[32];
sprintf(Address, "Dmem + %Xh", Addr);
MoveVariableToX86reg(RSPInfo.DMEM + Addr, Address, x86_EAX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
return;
}
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
AndConstToX86Reg(x86_EBX, 0x0fff);
TestConstToX86Reg(3, x86_EBX);
JneLabel32("UnAligned", 0);
Jump[0] = RecompPos - 4;
CompilerToggleBuffer();
x86_SetBranch32b(Jump[0], RecompPos);
CPU_Message(" Unaligned:");
LeaSourceAndOffset(x86_ECX , x86_EBX, 2);
LeaSourceAndOffset(x86_EDX , x86_EBX, 3);
MoveX86RegToX86Reg(x86_EBX, x86_EAX);
AddConstToX86Reg(x86_EBX, 1);
XorConstToX86Reg(x86_EAX, 3);
XorConstToX86Reg(x86_EBX, 3);
XorConstToX86Reg(x86_ECX, 3);
XorConstToX86Reg(x86_EDX, 3);
MoveN64MemToX86regByte(x86_EAX, x86_EAX);
MoveN64MemToX86regByte(x86_EBX, x86_EBX);
MoveN64MemToX86regByte(x86_ECX, x86_ECX);
MoveN64MemToX86regByte(x86_EDX, x86_EDX);
MoveX86regByteToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UB[3], GPR_Name(RSPOpC.rt));
MoveX86regByteToVariable(x86_EBX, &RSP_GPR[RSPOpC.rt].UB[2], GPR_Name(RSPOpC.rt));
MoveX86regByteToVariable(x86_ECX, &RSP_GPR[RSPOpC.rt].UB[1], GPR_Name(RSPOpC.rt));
MoveX86regByteToVariable(x86_EDX, &RSP_GPR[RSPOpC.rt].UB[0], GPR_Name(RSPOpC.rt));
JmpLabel32("Done", 0);
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
MoveN64MemToX86reg(x86_EAX, x86_EBX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
CPU_Message(" Done:");
x86_SetBranch32b(Jump[1], RecompPos);
}
void Compile_LBU ( void ) {
int Offset = (short)RSPOpC.offset;
#ifndef Compile_GPRLoads
Cheat_r4300iOpcode(RSP_Opcode_LBU,"RSP_Opcode_LBU"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
XorX86RegToX86Reg(x86_EAX, x86_EAX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
XorConstToX86Reg(x86_EBX, 3);
AndConstToX86Reg(x86_EBX, 0x0fff);
MoveN64MemToX86regByte(x86_EAX, x86_EBX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
}
void Compile_LHU ( void ) {
int Offset = (short)RSPOpC.offset;
BYTE * Jump[2];
#ifndef Compile_GPRLoads
Cheat_r4300iOpcode(RSP_Opcode_LHU,"RSP_Opcode_LHU"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (IsRegConst(RSPOpC.base) == TRUE) {
DWORD Addr = (MipsRegConst(RSPOpC.base) + Offset) ^ 2;
Addr &= 0xfff;
if ((Addr & 1) != 0) {
CompilerWarning("Unaligned LHU at constant address PC = %04X", CompilePC);
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_LHU,"RSP_Opcode_LHU");
return;
} else {
char Address[32];
sprintf(Address, "Dmem + %Xh", Addr);
MoveZxVariableToX86regHalf(RSPInfo.DMEM + Addr, Address, x86_ECX);
MoveX86regToVariable(x86_ECX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
return;
}
}
/*
* should really just do it by bytes but whatever for now
*/
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) {
AddConstToX86Reg(x86_EBX, Offset);
}
TestConstToX86Reg(1, x86_EBX);
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
x86_SetBranch32b(Jump[0], RecompPos);
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_LHU,"RSP_Opcode_LHU");
JmpLabel32("Done", 0);
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
XorConstToX86Reg(x86_EBX, 2);
AndConstToX86Reg(x86_EBX, 0x0fff);
MoveZxN64MemToX86regHalf(x86_EAX, x86_EBX);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
CPU_Message(" Done:");
x86_SetBranch32b(Jump[1], RecompPos);
}
void Compile_SB ( void ) {
int Offset = (short)RSPOpC.offset;
#ifndef Compile_GPRStores
Cheat_r4300iOpcode(RSP_Opcode_SB,"RSP_Opcode_SB"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
MoveVariableToX86regByte(&RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt), x86_EAX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
XorConstToX86Reg(x86_EBX, 3);
AndConstToX86Reg(x86_EBX, 0x0fff);
MoveX86regByteToN64Mem(x86_EAX, x86_EBX);
}
void Compile_SH ( void ) {
int Offset = (short)RSPOpC.offset;
BYTE * Jump[2];
#ifndef Compile_GPRStores
Cheat_r4300iOpcode(RSP_Opcode_SH,"RSP_Opcode_SH"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (IsRegConst(RSPOpC.base) == TRUE) {
DWORD Addr = (MipsRegConst(RSPOpC.base) + Offset) ^ 2;
Addr &= 0xfff;
if ((Offset & 1) != 0) {
CompilerWarning("Unaligned SH at constant address PC = %04X", CompilePC);
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_SH,"RSP_Opcode_SH");
return;
} else {
char Address[32];
sprintf(Address, "Dmem + %Xh", Addr);
MoveVariableToX86regHalf(&RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt), x86_EAX);
MoveX86regHalfToVariable(x86_EAX, RSPInfo.DMEM + Addr, Address);
return;
}
}
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
TestConstToX86Reg(1, x86_EBX);
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
x86_SetBranch32b(Jump[0], RecompPos);
X86BreakPoint(__FILE__,__LINE__);
JmpLabel32("Done", 0);
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
XorConstToX86Reg(x86_EBX, 2);
AndConstToX86Reg(x86_EBX, 0x0fff);
MoveVariableToX86regHalf(&RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt), x86_EAX);
MoveX86regHalfToN64Mem(x86_EAX, x86_EBX);
CPU_Message(" Done:");
x86_SetBranch32b(Jump[1], RecompPos);
}
void Compile_SW ( void ) {
int Offset = (short)RSPOpC.offset;
BYTE * Jump[2];
#ifndef Compile_GPRStores
Cheat_r4300iOpcode(RSP_Opcode_SW,"RSP_Opcode_SW"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (IsRegConst(RSPOpC.base) == TRUE) {
DWORD Addr = (MipsRegConst(RSPOpC.base) + Offset) & 0xfff;
if ((Addr & 3) != 0) {
CompilerWarning("Unaligned SW at constant address PC = %04X", CompilePC);
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_SW,"RSP_Opcode_SW");
return;
} else {
char Address[32];
sprintf(Address, "Dmem + %Xh", Addr);
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt), x86_EAX);
MoveX86regToVariable(x86_EAX, RSPInfo.DMEM + Addr, Address);
return;
}
}
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) AddConstToX86Reg(x86_EBX, Offset);
AndConstToX86Reg(x86_EBX, 0x0fff);
TestConstToX86Reg(3, x86_EBX);
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
x86_SetBranch32b(Jump[0], RecompPos);
// X86BreakPoint(__FILE__,__LINE__);
Push(x86_EBX);
LeaSourceAndOffset(x86_ECX , x86_EBX, 2);
LeaSourceAndOffset(x86_EDX , x86_EBX, 3);
XorConstToX86Reg(x86_ECX, 3);
XorConstToX86Reg(x86_EDX, 3);
MoveVariableToX86regByte(&RSP_GPR[RSPOpC.rt].UB[1], GPR_Name(RSPOpC.rt),x86_EAX); //cx
MoveVariableToX86regByte(&RSP_GPR[RSPOpC.rt].UB[0], GPR_Name(RSPOpC.rt),x86_EBX); //dx
MoveX86regByteToN64Mem(x86_EAX, x86_ECX);
MoveX86regByteToN64Mem(x86_EBX, x86_EDX);
Pop(x86_EBX);
MoveX86RegToX86Reg(x86_EBX, x86_EAX);
AddConstToX86Reg(x86_EBX, 1);
XorConstToX86Reg(x86_EAX, 3);
XorConstToX86Reg(x86_EBX, 3);
MoveVariableToX86regByte(&RSP_GPR[RSPOpC.rt].UB[3], GPR_Name(RSPOpC.rt),x86_ECX); //ax
MoveVariableToX86regByte(&RSP_GPR[RSPOpC.rt].UB[2], GPR_Name(RSPOpC.rt),x86_EDX); //bx
MoveX86regByteToN64Mem(x86_ECX, x86_EAX);
MoveX86regByteToN64Mem(x86_EDX, x86_EBX);
JmpLabel32("Done", 0);
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
if (RSPOpC.rt == 0) {
XorX86RegToX86Reg(x86_EAX,x86_EAX);
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt), x86_EAX);
}
MoveX86regToN64Mem(x86_EAX, x86_EBX);
CPU_Message(" Done:");
x86_SetBranch32b(Jump[1], RecompPos);
}
void Compile_LC2 (void) {
((void (*)()) RSP_Lc2 [ RSPOpC.rd ])();
}
void Compile_SC2 (void) {
((void (*)()) RSP_Sc2 [ RSPOpC.rd ])();
}
/********************** R4300i OpCodes: Special **********************/
void Compile_Special_SLL ( void ) {
#ifndef Compile_Special
Cheat_r4300iOpcode(RSP_Special_SLL,"RSP_Special_SLL"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rd == 0) return;
if (RSPOpC.rd == RSPOpC.rt) {
ShiftLeftSignVariableImmed(&RSP_GPR[RSPOpC.rd].W, GPR_Name(RSPOpC.rd), (BYTE)RSPOpC.sa);
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W, GPR_Name(RSPOpC.rt), x86_EAX);
ShiftLeftSignImmed(x86_EAX, (BYTE)RSPOpC.sa);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rd].W, GPR_Name(RSPOpC.rd));
}
}
void Compile_Special_SRL ( void ) {
#ifndef Compile_Special
Cheat_r4300iOpcode(RSP_Special_SRL,"RSP_Special_SRL"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rd == 0) return;
if (RSPOpC.rd == RSPOpC.rt) {
ShiftRightUnsignVariableImmed(&RSP_GPR[RSPOpC.rd].W, GPR_Name(RSPOpC.rd), (BYTE)RSPOpC.sa);
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W, GPR_Name(RSPOpC.rt), x86_EAX);
ShiftRightUnsignImmed(x86_EAX, (BYTE)RSPOpC.sa);
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rd].W, GPR_Name(RSPOpC.rd));
}
}
void Compile_Special_SRA ( void ) {
#ifndef Compile_Special
Cheat_r4300iOpcode(RSP_Special_SRA,"RSP_Special_SRA"); return;
#endif
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (RSPOpC.rd == 0) return;
if (RSPOpC.rd == RSPOpC.rt) {
ShiftRightSignVariableImmed(&RSP_GPR[RSPOpC.rd].W, GPR_Name(RSPOpC.rd), (BYTE)RSPOpC.sa);
} else {
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rt].W, GPR_Name(RSPOpC.rt), x86_EAX);