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clock-gcc-8953.c
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clock-gcc-8953.c
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/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <soc/qcom/clock-alpha-pll.h>
#include <soc/qcom/clock-local2.h>
#include <soc/qcom/clock-pll.h>
#include <soc/qcom/clock-voter.h>
#include <soc/qcom/rpm-smd.h>
#include <soc/qcom/clock-rpm.h>
#include <linux/clk/msm-clock-generic.h>
#include <linux/regulator/rpm-smd-regulator.h>
#include <dt-bindings/clock/msm-clocks-hwio-8953.h>
#include <dt-bindings/clock/msm-clocks-8953.h>
#include "clock.h"
enum {
GCC_BASE,
GFX_BASE,
MDSS_BASE,
N_BASES,
};
static void __iomem *virt_bases[N_BASES];
#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src,
RPM_MISC_CLK_TYPE, XO_ID, 19200000);
DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
DEFINE_CLK_RPM_SMD(pcnoc_clk, pcnoc_a_clk, RPM_BUS_CLK_TYPE, PCNOC_ID, NULL);
DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
SYSMMNOC_ID, NULL);
DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_ID, NULL);
DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
/* BIMC voter */
static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
/* PCNOC Voter */
static DEFINE_CLK_VOTER(pcnoc_keepalive_a_clk, &pcnoc_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(pcnoc_msmbus_clk, &pcnoc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(pcnoc_msmbus_a_clk, &pcnoc_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(pcnoc_usb_clk, &pcnoc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(pcnoc_usb_a_clk, &pcnoc_a_clk.c, LONG_MAX);
/* SNOC Voter */
static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
/* SYSMMNOC Voter */
static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
/* XO Voter */
static DEFINE_CLK_BRANCH_VOTER(xo_dwc3_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
/* SMD_XO_BUFFER */
DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk3, rf_clk3_a, RF_CLK3_ID);
DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
DEFINE_EXT_CLK(debug_cpu_clk, NULL);
static struct pll_vote_clk gpll0_clk_src = {
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
.en_mask = BIT(0),
.status_reg = (void __iomem *)GPLL0_MODE,
.status_mask = BIT(30),
.base = &virt_bases[GCC_BASE],
.c = {
.rate = 800000000,
.parent = &xo_clk_src.c,
.dbg_name = "gpll0_clk_src",
.ops = &clk_ops_pll_vote,
CLK_INIT(gpll0_clk_src.c),
},
};
static struct pll_vote_clk gpll2_clk_src = {
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
.en_mask = BIT(2),
.status_reg = (void __iomem *)GPLL2_MODE,
.status_mask = BIT(30),
.base = &virt_bases[GCC_BASE],
.c = {
.rate = 930000000,
.parent = &xo_clk_src.c,
.dbg_name = "gpll2_clk_src",
.ops = &clk_ops_pll_vote,
CLK_INIT(gpll2_clk_src.c),
},
};
static struct alpha_pll_masks gpll3_masks_p = {
.lock_mask = BIT(31),
.active_mask = BIT(30),
.vco_mask = BM(21, 20) >> 20,
.vco_shift = 20,
.alpha_en_mask = BIT(24),
.output_mask = 0xf,
.update_mask = BIT(22),
.post_div_mask = BM(11, 8),
.test_ctl_lo_mask = BM(31, 0),
.test_ctl_hi_mask = BM(31, 0),
};
static struct alpha_pll_vco_tbl gpll3_p_vco[] = {
VCO(0, 1000000000, 2000000000),
};
static struct alpha_pll_clk gpll3_clk_src = {
.masks = &gpll3_masks_p,
.base = &virt_bases[GCC_BASE],
.offset = GPLL3_MODE,
.vco_tbl = gpll3_p_vco,
.num_vco = ARRAY_SIZE(gpll3_p_vco),
.enable_config = 1,
.post_div_config = 1 << 8,
.slew = true,
.config_ctl_val = 0x4001055b,
.c = {
.rate = 1300000000,
.parent = &xo_clk_src.c,
.dbg_name = "gpll3_clk_src",
.ops = &clk_ops_dyna_alpha_pll,
VDD_DIG_FMAX_MAP1(SVS, 2000000000),
CLK_INIT(gpll3_clk_src.c),
},
};
static struct pll_vote_clk gpll4_clk_src = {
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
.en_mask = BIT(5),
.status_reg = (void __iomem *)GPLL4_MODE,
.status_mask = BIT(30),
.base = &virt_bases[GCC_BASE],
.c = {
.rate = 1152000000,
.parent = &xo_clk_src.c,
.dbg_name = "gpll4_clk_src",
.ops = &clk_ops_pll_vote,
CLK_INIT(gpll4_clk_src.c),
},
};
/* Brammo PLL status BIT(2) PLL_LOCK_DET */
static struct pll_vote_clk gpll6_clk_src = {
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
.en_mask = BIT(7),
.status_reg = (void __iomem *)GPLL6_STATUS,
.status_mask = BIT(2),
.base = &virt_bases[GCC_BASE],
.c = {
.rate = 1080000000,
.parent = &xo_clk_src.c,
.dbg_name = "gpll6_clk_src",
.ops = &clk_ops_pll_vote,
CLK_INIT(gpll6_clk_src.c),
},
};
DEFINE_EXT_CLK(xo_pipe_clk_src, &xo_clk_src.c);
DEFINE_EXT_CLK(gpll0_main_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll0_main_div2_cci_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll0_main_div2_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll0_main_div2_mm_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll0_main_div2_usb3_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll0_main_mock_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll2_out_main_clk_src, &gpll2_clk_src.c);
DEFINE_EXT_CLK(gpll2_vcodec_clk_src, &gpll2_clk_src.c);
DEFINE_EXT_CLK(gpll4_aux_clk_src, &gpll4_clk_src.c);
DEFINE_EXT_CLK(gpll4_out_aux_clk_src, &gpll4_clk_src.c);
DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_div2_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_div2_gfx_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_gfx_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_div2_mock_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_out_aux_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
static struct clk_freq_tbl ftbl_camss_top_ahb_clk_src[] = {
F( 40000000, gpll0_main_div2, 10, 0, 0),
F( 80000000, gpll0, 10, 0, 0),
F_END
};
static struct rcg_clk camss_top_ahb_clk_src = {
.cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_camss_top_ahb_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "camss_top_ahb_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP2(LOW_SVS, 40000000, SVS_PLUS, 80000000),
CLK_INIT(camss_top_ahb_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_csi0_clk_src[] = {
F( 100000000, gpll0_main_div2_mm, 4, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2, 2, 0, 0),
F_END
};
static struct rcg_clk csi0_clk_src = {
.cmd_rcgr_reg = CSI0_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_csi0_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "csi0_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP5(LOW_SVS, 100000000, SVS, 200000000, SVS_PLUS,
310000000, NOM, 400000000, NOM_PLUS, 465000000),
CLK_INIT(csi0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_apss_ahb_clk_src[] = {
F( 19200000, xo_a, 1, 0, 0),
F( 25000000, gpll0_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F( 100000000, gpll0, 8, 0, 0),
F( 133330000, gpll0, 6, 0, 0),
F_END
};
static struct rcg_clk apss_ahb_clk_src = {
.cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_apss_ahb_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "apss_ahb_clk_src",
.ops = &clk_ops_rcg,
CLK_INIT(apss_ahb_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_csi1_clk_src[] = {
F( 100000000, gpll0_main_div2, 4, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 310000000, gpll2_out_main, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2_out_main, 2, 0, 0),
F_END
};
static struct rcg_clk csi1_clk_src = {
.cmd_rcgr_reg = CSI1_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_csi1_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "csi1_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP5(LOW_SVS, 100000000, SVS, 200000000, SVS_PLUS,
310000000, NOM, 400000000, NOM_PLUS, 465000000),
CLK_INIT(csi1_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_csi2_clk_src[] = {
F( 100000000, gpll0_main_div2, 4, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 310000000, gpll2_out_main, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2_out_main, 2, 0, 0),
F_END
};
static struct rcg_clk csi2_clk_src = {
.cmd_rcgr_reg = CSI2_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_csi2_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "csi2_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP5(LOW_SVS, 100000000, SVS, 200000000, SVS_PLUS,
310000000, NOM, 400000000, NOM_PLUS, 465000000),
CLK_INIT(csi2_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_vfe0_clk_src[] = {
F( 50000000, gpll0_main_div2_mm, 8, 0, 0),
F( 100000000, gpll0_main_div2_mm, 4, 0, 0),
F( 133330000, gpll0, 6, 0, 0),
F( 160000000, gpll0, 5, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 266670000, gpll0, 3, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2, 2, 0, 0),
F_END
};
static struct rcg_clk vfe0_clk_src = {
.cmd_rcgr_reg = VFE0_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_vfe0_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "vfe0_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP4(LOW_SVS, 100000000, SVS, 200000000, SVS_PLUS,
310000000, NOM, 465000000),
CLK_INIT(vfe0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = {
F_MM( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
F_MM( 50000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 8, 0, 0),
F_MM( 80000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 5, 0, 0),
F_MM( 100000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 4, 0, 0),
F_MM( 133330000, FIXED_CLK_SRC, gpll0_main_div2_mm, 3, 0, 0),
F_MM( 160000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 2.5, 0, 0),
F_MM( 200000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 2, 0, 0),
F_MM( 216000000, FIXED_CLK_SRC, gpll6_main_div2_gfx, 2.5, 0, 0),
F_MM( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
F_MM( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
F_MM( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
F_MM( 460800000, FIXED_CLK_SRC, gpll4_out_aux, 2.5, 0, 0),
F_MM( 510000000, 1020000000, gpll3, 1, 0, 0),
F_MM( 560000000, 1120000000, gpll3, 1, 0, 0),
F_MM( 650000000, 1300000000, gpll3, 1, 0, 0),
F_END
};
static struct clk_freq_tbl ftbl_gfx3d_clk_src_sdm450[] = {
F_MM( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
F_MM( 50000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 8, 0, 0),
F_MM( 80000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 5, 0, 0),
F_MM( 100000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 4, 0, 0),
F_MM( 133330000, FIXED_CLK_SRC, gpll0_main_div2_mm, 3, 0, 0),
F_MM( 160000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 2.5, 0, 0),
F_MM( 200000000, FIXED_CLK_SRC, gpll0_main_div2_mm, 2, 0, 0),
F_MM( 216000000, FIXED_CLK_SRC, gpll6_main_div2_gfx, 2.5, 0, 0),
F_MM( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
F_MM( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
F_MM( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
F_MM( 460800000, FIXED_CLK_SRC, gpll4_out_aux, 2.5, 0, 0),
F_MM( 510000000, 1020000000, gpll3, 1, 0, 0),
F_MM( 560000000, 1120000000, gpll3, 1, 0, 0),
F_MM( 600000000, 1200000000, gpll3, 1, 0, 0),
F_END
};
static struct rcg_clk gfx3d_clk_src = {
.cmd_rcgr_reg = GFX3D_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_gfx3d_clk_src,
.current_freq = &rcg_dummy_freq,
.non_local_control_timeout = 1000,
.base = &virt_bases[GFX_BASE],
.c = {
.dbg_name = "gfx3d_clk_src",
.ops = &clk_ops_rcg,
CLK_INIT(gfx3d_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_vcodec0_clk_src[] = {
F( 114290000, gpll0_main_div2, 3.5, 0, 0),
F( 228570000, gpll0, 3.5, 0, 0),
F( 310000000, gpll2_vcodec, 3, 0, 0),
F( 360000000, gpll6, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2_vcodec, 2, 0, 0),
F_END
};
static struct clk_freq_tbl ftbl_vcodec0_clk_src_540MHz[] = {
F( 114290000, gpll0_main_div2, 3.5, 0, 0),
F( 228570000, gpll0, 3.5, 0, 0),
F( 310000000, gpll2_vcodec, 3, 0, 0),
F( 360000000, gpll6, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2_vcodec, 2, 0, 0),
F( 540000000, gpll6, 2, 0, 0),
F_END
};
static struct rcg_clk vcodec0_clk_src = {
.cmd_rcgr_reg = VCODEC0_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_vcodec0_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "vcodec0_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP6(LOW_SVS, 114290000, SVS, 228570000, SVS_PLUS,
310000000, NOM, 360000000, NOM_PLUS, 400000000,
HIGH, 465000000),
CLK_INIT(vcodec0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_cpp_clk_src[] = {
F( 100000000, gpll0_main_div2_mm, 4, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 266670000, gpll0, 3, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2, 2, 0, 0),
F_END
};
static struct rcg_clk cpp_clk_src = {
.cmd_rcgr_reg = CPP_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_cpp_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "cpp_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP5(LOW_SVS, 100000000, SVS, 200000000, SVS_PLUS,
266670000, NOM, 400000000, NOM_PLUS, 465000000),
CLK_INIT(cpp_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_jpeg0_clk_src[] = {
F( 66670000, gpll0_main_div2, 6, 0, 0),
F( 133330000, gpll0, 6, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 266670000, gpll0, 3, 0, 0),
F( 310000000, gpll2_out_main, 3, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
F_END
};
static struct rcg_clk jpeg0_clk_src = {
.cmd_rcgr_reg = JPEG0_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_jpeg0_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "jpeg0_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP6(LOW_SVS, 66670000, SVS, 133330000, SVS_PLUS,
200000000, NOM, 266670000, NOM_PLUS, 310000000,
HIGH, 320000000),
CLK_INIT(jpeg0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_mdp_clk_src[] = {
F( 50000000, gpll0_main_div2, 8, 0, 0),
F( 80000000, gpll0_main_div2, 5, 0, 0),
F( 160000000, gpll0_main_div2, 2.5, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 266670000, gpll0, 3, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F_END
};
static struct rcg_clk mdp_clk_src = {
.cmd_rcgr_reg = MDP_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_mdp_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "mdp_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP4(LOW_SVS, 160000000, SVS, 266670000, NOM,
320000000, HIGH, 400000000),
CLK_INIT(mdp_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_pclk0_clk_src[] = {
{
.div_src_val = BVAL(10, 8, xo_src_val)
| BVAL(4, 0, 0),
.src_clk = &xo_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_src_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk0_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_src_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk1_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct rcg_clk pclk0_clk_src = {
.cmd_rcgr_reg = PCLK0_CMD_RCGR,
.set_rate = set_rate_mnd,
.current_freq = ftbl_pclk0_clk_src,
.freq_tbl = ftbl_pclk0_clk_src,
.base = &virt_bases[MDSS_BASE],
.c = {
.dbg_name = "pclk0_clk_src",
.ops = &clk_ops_pixel_multiparent,
.flags = CLKFLAG_NO_RATE_CACHE,
VDD_DIG_FMAX_MAP3(LOW_SVS, 175000000, SVS, 280000000, NOM,
350000000),
CLK_INIT(pclk0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_pclk1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, xo_src_val)
| BVAL(4, 0, 0),
.src_clk = &xo_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi1_phypll_clk_mm_src_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk1_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi0_phypll_clk_mm_src_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk0_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct rcg_clk pclk1_clk_src = {
.cmd_rcgr_reg = PCLK1_CMD_RCGR,
.set_rate = set_rate_mnd,
.current_freq = ftbl_pclk1_clk_src,
.freq_tbl = ftbl_pclk1_clk_src,
.base = &virt_bases[MDSS_BASE],
.c = {
.dbg_name = "pclk1_clk_src",
.ops = &clk_ops_pixel_multiparent,
.flags = CLKFLAG_NO_RATE_CACHE,
VDD_DIG_FMAX_MAP3(LOW_SVS, 175000000, SVS, 280000000, NOM,
350000000),
CLK_INIT(pclk1_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_usb30_master_clk_src[] = {
F( 80000000, gpll0_main_div2_usb3, 5, 0, 0),
F( 100000000, gpll0, 8, 0, 0),
F( 133330000, gpll0, 6, 0, 0),
F_END
};
static struct rcg_clk usb30_master_clk_src = {
.cmd_rcgr_reg = USB30_MASTER_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_usb30_master_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "usb30_master_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP2(LOW_SVS, 80000000, NOM, 133330000),
CLK_INIT(usb30_master_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_vfe1_clk_src[] = {
F( 50000000, gpll0_main_div2_mm, 8, 0, 0),
F( 100000000, gpll0_main_div2_mm, 4, 0, 0),
F( 133330000, gpll0, 6, 0, 0),
F( 160000000, gpll0, 5, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 266670000, gpll0, 3, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 465000000, gpll2, 2, 0, 0),
F_END
};
static struct rcg_clk vfe1_clk_src = {
.cmd_rcgr_reg = VFE1_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_vfe1_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "vfe1_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP4(LOW_SVS, 100000000, SVS, 200000000, SVS_PLUS,
310000000, NOM, 465000000),
CLK_INIT(vfe1_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_apc0_droop_detector_clk_src[] = {
F( 19200000, xo, 1, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 576000000, gpll4, 2, 0, 0),
F_END
};
static struct rcg_clk apc0_droop_detector_clk_src = {
.cmd_rcgr_reg = APC0_VOLTAGE_DROOP_DETECTOR_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_apc0_droop_detector_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "apc0_droop_detector_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW_SVS, 19200000, SVS, 400000000, NOM,
600000000),
CLK_INIT(apc0_droop_detector_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_apc1_droop_detector_clk_src[] = {
F( 19200000, xo, 1, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
F( 576000000, gpll4, 2, 0, 0),
F_END
};
static struct rcg_clk apc1_droop_detector_clk_src = {
.cmd_rcgr_reg = APC1_VOLTAGE_DROOP_DETECTOR_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_apc1_droop_detector_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "apc1_droop_detector_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW_SVS, 19200000, SVS, 400000000, NOM,
600000000),
CLK_INIT(apc1_droop_detector_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F( 19200000, xo, 1, 0, 0),
F( 25000000, gpll0_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F_END
};
static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup1_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F( 960000, xo, 10, 1, 2),
F( 4800000, xo, 4, 0, 0),
F( 9600000, xo, 2, 0, 0),
F( 12500000, gpll0_main_div2, 16, 1, 2),
F( 16000000, gpll0, 10, 1, 5),
F( 19200000, xo, 1, 0, 0),
F( 25000000, gpll0, 16, 1, 2),
F( 50000000, gpll0, 16, 0, 0),
F_END
};
static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup1_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup2_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup2_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup3_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup3_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup4_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_qup4_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F( 3686400, gpll0_main_div2, 1, 144, 15625),
F( 7372800, gpll0_main_div2, 1, 288, 15625),
F( 14745600, gpll0_main_div2, 1, 576, 15625),
F( 16000000, gpll0_main_div2, 5, 1, 5),
F( 19200000, xo, 1, 0, 0),
F( 24000000, gpll0, 1, 3, 100),
F( 25000000, gpll0, 16, 1, 2),
F( 32000000, gpll0, 1, 1, 25),
F( 40000000, gpll0, 1, 1, 20),
F( 46400000, gpll0, 1, 29, 500),
F( 48000000, gpll0, 1, 3, 50),
F( 51200000, gpll0, 1, 8, 125),
F( 56000000, gpll0, 1, 7, 100),
F( 58982400, gpll0, 1, 1152, 15625),
F( 60000000, gpll0, 1, 3, 40),
F( 64000000, gpll0, 1, 2, 25),
F_END
};
static struct rcg_clk blsp1_uart1_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_uart1_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 16000000, SVS, 32000000, NOM,
64000000),
CLK_INIT(blsp1_uart1_apps_clk_src.c),
},
};
static struct rcg_clk blsp1_uart2_apps_clk_src = {
.cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp1_uart2_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 16000000, SVS, 32000000, NOM,
64000000),
CLK_INIT(blsp1_uart2_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup1_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup1_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup2_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup2_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup3_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup3_spi_apps_clk_src",
.ops = &clk_ops_rcg_mnd,
VDD_DIG_FMAX_MAP3(LOW_SVS, 12500000, SVS, 25000000, NOM,
50000000),
CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
.set_rate = set_rate_hid,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "blsp2_qup4_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW_SVS, 25000000, SVS, 50000000),
CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
},
};
static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.current_freq = &rcg_dummy_freq,