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lj_asm_x86.h
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lj_asm_x86.h
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/*
** x86/x64 IR assembler (SSA IR -> machine code).
** Copyright (C) 2005-2022 Mike Pall. See Copyright Notice in luajit.h
*/
/* -- Guard handling ------------------------------------------------------ */
/* Generate an exit stub group at the bottom of the reserved MCode memory. */
static MCode *asm_exitstub_gen(ASMState *as, ExitNo group)
{
ExitNo i, groupofs = (group*EXITSTUBS_PER_GROUP) & 0xff;
MCode *mxp = as->mcbot;
MCode *mxpstart = mxp;
if (mxp + (2+2)*EXITSTUBS_PER_GROUP+8+5 >= as->mctop)
asm_mclimit(as);
/* Push low byte of exitno for each exit stub. */
*mxp++ = XI_PUSHi8; *mxp++ = (MCode)groupofs;
for (i = 1; i < EXITSTUBS_PER_GROUP; i++) {
*mxp++ = XI_JMPs; *mxp++ = (MCode)((2+2)*(EXITSTUBS_PER_GROUP - i) - 2);
*mxp++ = XI_PUSHi8; *mxp++ = (MCode)(groupofs + i);
}
/* Push the high byte of the exitno for each exit stub group. */
*mxp++ = XI_PUSHi8; *mxp++ = (MCode)((group*EXITSTUBS_PER_GROUP)>>8);
#if !LJ_GC64
/* Store DISPATCH at original stack slot 0. Account for the two push ops. */
*mxp++ = XI_MOVmi;
*mxp++ = MODRM(XM_OFS8, 0, RID_ESP);
*mxp++ = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
*mxp++ = 2*sizeof(void *);
*(int32_t *)mxp = ptr2addr(J2GG(as->J)->dispatch); mxp += 4;
#endif
/* Jump to exit handler which fills in the ExitState. */
*mxp++ = XI_JMP; mxp += 4;
*((int32_t *)(mxp-4)) = jmprel(as->J, mxp, (MCode *)(void *)lj_vm_exit_handler);
/* Commit the code for this group (even if assembly fails later on). */
lj_mcode_commitbot(as->J, mxp);
as->mcbot = mxp;
as->mclim = as->mcbot + MCLIM_REDZONE;
return mxpstart;
}
/* Setup all needed exit stubs. */
static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
{
ExitNo i;
if (nexits >= EXITSTUBS_PER_GROUP*LJ_MAX_EXITSTUBGR)
lj_trace_err(as->J, LJ_TRERR_SNAPOV);
for (i = 0; i < (nexits+EXITSTUBS_PER_GROUP-1)/EXITSTUBS_PER_GROUP; i++)
if (as->J->exitstubgroup[i] == NULL)
as->J->exitstubgroup[i] = asm_exitstub_gen(as, i);
}
/* Emit conditional branch to exit for guard.
** It's important to emit this *after* all registers have been allocated,
** because rematerializations may invalidate the flags.
*/
static void asm_guardcc(ASMState *as, int cc)
{
MCode *target = exitstub_addr(as->J, as->snapno);
MCode *p = as->mcp;
if (LJ_UNLIKELY(p == as->invmcp)) {
as->loopinv = 1;
*(int32_t *)(p+1) = jmprel(as->J, p+5, target);
target = p;
cc ^= 1;
if (as->realign) {
if (LJ_GC64 && LJ_UNLIKELY(as->mrm.base == RID_RIP))
as->mrm.ofs += 2; /* Fixup RIP offset for pending fused load. */
emit_sjcc(as, cc, target);
return;
}
}
if (LJ_GC64 && LJ_UNLIKELY(as->mrm.base == RID_RIP))
as->mrm.ofs += 6; /* Fixup RIP offset for pending fused load. */
emit_jcc(as, cc, target);
}
/* -- Memory operand fusion ----------------------------------------------- */
/* Limit linear search to this distance. Avoids O(n^2) behavior. */
#define CONFLICT_SEARCH_LIM 31
/* Check if a reference is a signed 32 bit constant. */
static int asm_isk32(ASMState *as, IRRef ref, int32_t *k)
{
if (irref_isk(ref)) {
IRIns *ir = IR(ref);
#if LJ_GC64
if (ir->o == IR_KNULL || !irt_is64(ir->t)) {
*k = ir->i;
return 1;
} else if (checki32((int64_t)ir_k64(ir)->u64)) {
*k = (int32_t)ir_k64(ir)->u64;
return 1;
}
#else
if (ir->o != IR_KINT64) {
*k = ir->i;
return 1;
} else if (checki32((int64_t)ir_kint64(ir)->u64)) {
*k = (int32_t)ir_kint64(ir)->u64;
return 1;
}
#endif
}
return 0;
}
/* Check if there's no conflicting instruction between curins and ref.
** Also avoid fusing loads if there are multiple references.
*/
static int noconflict(ASMState *as, IRRef ref, IROp conflict, int noload)
{
IRIns *ir = as->ir;
IRRef i = as->curins;
if (i > ref + CONFLICT_SEARCH_LIM)
return 0; /* Give up, ref is too far away. */
while (--i > ref) {
if (ir[i].o == conflict)
return 0; /* Conflict found. */
else if (!noload && (ir[i].op1 == ref || ir[i].op2 == ref))
return 0;
}
return 1; /* Ok, no conflict. */
}
/* Fuse array base into memory operand. */
static IRRef asm_fuseabase(ASMState *as, IRRef ref)
{
IRIns *irb = IR(ref);
as->mrm.ofs = 0;
if (irb->o == IR_FLOAD) {
IRIns *ira = IR(irb->op1);
lj_assertA(irb->op2 == IRFL_TAB_ARRAY, "expected FLOAD TAB_ARRAY");
/* We can avoid the FLOAD of t->array for colocated arrays. */
if (ira->o == IR_TNEW && ira->op1 <= LJ_MAX_COLOSIZE &&
!neverfuse(as) && noconflict(as, irb->op1, IR_NEWREF, 1)) {
as->mrm.ofs = (int32_t)sizeof(GCtab); /* Ofs to colocated array. */
return irb->op1; /* Table obj. */
}
} else if (irb->o == IR_ADD && irref_isk(irb->op2)) {
/* Fuse base offset (vararg load). */
as->mrm.ofs = IR(irb->op2)->i;
return irb->op1;
}
return ref; /* Otherwise use the given array base. */
}
/* Fuse array reference into memory operand. */
static void asm_fusearef(ASMState *as, IRIns *ir, RegSet allow)
{
IRIns *irx;
lj_assertA(ir->o == IR_AREF, "expected AREF");
as->mrm.base = (uint8_t)ra_alloc1(as, asm_fuseabase(as, ir->op1), allow);
irx = IR(ir->op2);
if (irref_isk(ir->op2)) {
as->mrm.ofs += 8*irx->i;
as->mrm.idx = RID_NONE;
} else {
rset_clear(allow, as->mrm.base);
as->mrm.scale = XM_SCALE8;
/* Fuse a constant ADD (e.g. t[i+1]) into the offset.
** Doesn't help much without ABCelim, but reduces register pressure.
*/
if (!LJ_64 && /* Has bad effects with negative index on x64. */
mayfuse(as, ir->op2) && ra_noreg(irx->r) &&
irx->o == IR_ADD && irref_isk(irx->op2)) {
as->mrm.ofs += 8*IR(irx->op2)->i;
as->mrm.idx = (uint8_t)ra_alloc1(as, irx->op1, allow);
} else {
as->mrm.idx = (uint8_t)ra_alloc1(as, ir->op2, allow);
}
}
}
/* Fuse array/hash/upvalue reference into memory operand.
** Caveat: this may allocate GPRs for the base/idx registers. Be sure to
** pass the final allow mask, excluding any GPRs used for other inputs.
** In particular: 2-operand GPR instructions need to call ra_dest() first!
*/
static void asm_fuseahuref(ASMState *as, IRRef ref, RegSet allow)
{
IRIns *ir = IR(ref);
if (ra_noreg(ir->r)) {
switch ((IROp)ir->o) {
case IR_AREF:
if (mayfuse(as, ref)) {
asm_fusearef(as, ir, allow);
return;
}
break;
case IR_HREFK:
if (mayfuse(as, ref)) {
as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
as->mrm.ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
as->mrm.idx = RID_NONE;
return;
}
break;
case IR_UREFC:
if (irref_isk(ir->op1)) {
GCfunc *fn = ir_kfunc(IR(ir->op1));
GCupval *uv = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv;
#if LJ_GC64
int64_t ofs = dispofs(as, &uv->tv);
if (checki32(ofs) && checki32(ofs+4)) {
as->mrm.ofs = (int32_t)ofs;
as->mrm.base = RID_DISPATCH;
as->mrm.idx = RID_NONE;
return;
}
#else
as->mrm.ofs = ptr2addr(&uv->tv);
as->mrm.base = as->mrm.idx = RID_NONE;
return;
#endif
}
break;
case IR_TMPREF:
#if LJ_GC64
as->mrm.ofs = (int32_t)dispofs(as, &J2G(as->J)->tmptv);
as->mrm.base = RID_DISPATCH;
as->mrm.idx = RID_NONE;
#else
as->mrm.ofs = igcptr(&J2G(as->J)->tmptv);
as->mrm.base = as->mrm.idx = RID_NONE;
#endif
return;
default:
break;
}
}
as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
as->mrm.ofs = 0;
as->mrm.idx = RID_NONE;
}
/* Fuse FLOAD/FREF reference into memory operand. */
static void asm_fusefref(ASMState *as, IRIns *ir, RegSet allow)
{
lj_assertA(ir->o == IR_FLOAD || ir->o == IR_FREF,
"bad IR op %d", ir->o);
as->mrm.idx = RID_NONE;
if (ir->op1 == REF_NIL) { /* FLOAD from GG_State with offset. */
#if LJ_GC64
as->mrm.ofs = (int32_t)(ir->op2 << 2) - GG_OFS(dispatch);
as->mrm.base = RID_DISPATCH;
#else
as->mrm.ofs = (int32_t)(ir->op2 << 2) + ptr2addr(J2GG(as->J));
as->mrm.base = RID_NONE;
#endif
return;
}
as->mrm.ofs = field_ofs[ir->op2];
if (irref_isk(ir->op1)) {
IRIns *op1 = IR(ir->op1);
#if LJ_GC64
if (ir->op1 == REF_NIL) {
as->mrm.ofs -= GG_OFS(dispatch);
as->mrm.base = RID_DISPATCH;
return;
} else if (op1->o == IR_KPTR || op1->o == IR_KKPTR) {
intptr_t ofs = dispofs(as, ir_kptr(op1));
if (checki32(as->mrm.ofs + ofs)) {
as->mrm.ofs += (int32_t)ofs;
as->mrm.base = RID_DISPATCH;
return;
}
}
#else
as->mrm.ofs += op1->i;
as->mrm.base = RID_NONE;
return;
#endif
}
as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
}
/* Fuse string reference into memory operand. */
static void asm_fusestrref(ASMState *as, IRIns *ir, RegSet allow)
{
IRIns *irr;
lj_assertA(ir->o == IR_STRREF, "bad IR op %d", ir->o);
as->mrm.base = as->mrm.idx = RID_NONE;
as->mrm.scale = XM_SCALE1;
as->mrm.ofs = sizeof(GCstr);
if (!LJ_GC64 && irref_isk(ir->op1)) {
as->mrm.ofs += IR(ir->op1)->i;
} else {
Reg r = ra_alloc1(as, ir->op1, allow);
rset_clear(allow, r);
as->mrm.base = (uint8_t)r;
}
irr = IR(ir->op2);
if (irref_isk(ir->op2)) {
as->mrm.ofs += irr->i;
} else {
Reg r;
/* Fuse a constant add into the offset, e.g. string.sub(s, i+10). */
if (!LJ_64 && /* Has bad effects with negative index on x64. */
mayfuse(as, ir->op2) && irr->o == IR_ADD && irref_isk(irr->op2)) {
as->mrm.ofs += IR(irr->op2)->i;
r = ra_alloc1(as, irr->op1, allow);
} else {
r = ra_alloc1(as, ir->op2, allow);
}
if (as->mrm.base == RID_NONE)
as->mrm.base = (uint8_t)r;
else
as->mrm.idx = (uint8_t)r;
}
}
static void asm_fusexref(ASMState *as, IRRef ref, RegSet allow)
{
IRIns *ir = IR(ref);
as->mrm.idx = RID_NONE;
if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
#if LJ_GC64
intptr_t ofs = dispofs(as, ir_kptr(ir));
if (checki32(ofs)) {
as->mrm.ofs = (int32_t)ofs;
as->mrm.base = RID_DISPATCH;
return;
}
} if (0) {
#else
as->mrm.ofs = ir->i;
as->mrm.base = RID_NONE;
} else if (ir->o == IR_STRREF) {
asm_fusestrref(as, ir, allow);
#endif
} else {
as->mrm.ofs = 0;
if (canfuse(as, ir) && ir->o == IR_ADD && ra_noreg(ir->r)) {
/* Gather (base+idx*sz)+ofs as emitted by cdata ptr/array indexing. */
IRIns *irx;
IRRef idx;
Reg r;
if (asm_isk32(as, ir->op2, &as->mrm.ofs)) { /* Recognize x+ofs. */
ref = ir->op1;
ir = IR(ref);
if (!(ir->o == IR_ADD && canfuse(as, ir) && ra_noreg(ir->r)))
goto noadd;
}
as->mrm.scale = XM_SCALE1;
idx = ir->op1;
ref = ir->op2;
irx = IR(idx);
if (!(irx->o == IR_BSHL || irx->o == IR_ADD)) { /* Try other operand. */
idx = ir->op2;
ref = ir->op1;
irx = IR(idx);
}
if (canfuse(as, irx) && ra_noreg(irx->r)) {
if (irx->o == IR_BSHL && irref_isk(irx->op2) && IR(irx->op2)->i <= 3) {
/* Recognize idx<<b with b = 0-3, corresponding to sz = (1),2,4,8. */
idx = irx->op1;
as->mrm.scale = (uint8_t)(IR(irx->op2)->i << 6);
} else if (irx->o == IR_ADD && irx->op1 == irx->op2) {
/* FOLD does idx*2 ==> idx<<1 ==> idx+idx. */
idx = irx->op1;
as->mrm.scale = XM_SCALE2;
}
}
r = ra_alloc1(as, idx, allow);
rset_clear(allow, r);
as->mrm.idx = (uint8_t)r;
}
noadd:
as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
}
}
/* Fuse load of 64 bit IR constant into memory operand. */
static Reg asm_fuseloadk64(ASMState *as, IRIns *ir)
{
const uint64_t *k = &ir_k64(ir)->u64;
if (!LJ_GC64 || checki32((intptr_t)k)) {
as->mrm.ofs = ptr2addr(k);
as->mrm.base = RID_NONE;
#if LJ_GC64
} else if (checki32(dispofs(as, k))) {
as->mrm.ofs = (int32_t)dispofs(as, k);
as->mrm.base = RID_DISPATCH;
} else if (checki32(mcpofs(as, k)) && checki32(mcpofs(as, k+1)) &&
checki32(mctopofs(as, k)) && checki32(mctopofs(as, k+1))) {
as->mrm.ofs = (int32_t)mcpofs(as, k);
as->mrm.base = RID_RIP;
} else { /* Intern 64 bit constant at bottom of mcode. */
if (ir->i) {
lj_assertA(*k == *(uint64_t*)(as->mctop - ir->i),
"bad interned 64 bit constant");
} else {
while ((uintptr_t)as->mcbot & 7) *as->mcbot++ = XI_INT3;
*(uint64_t*)as->mcbot = *k;
ir->i = (int32_t)(as->mctop - as->mcbot);
as->mcbot += 8;
as->mclim = as->mcbot + MCLIM_REDZONE;
lj_mcode_commitbot(as->J, as->mcbot);
}
as->mrm.ofs = (int32_t)mcpofs(as, as->mctop - ir->i);
as->mrm.base = RID_RIP;
#endif
}
as->mrm.idx = RID_NONE;
return RID_MRM;
}
/* Fuse load into memory operand.
**
** Important caveat: this may emit RIP-relative loads! So don't place any
** code emitters between this function and the use of its result.
** The only permitted exception is asm_guardcc().
*/
static Reg asm_fuseload(ASMState *as, IRRef ref, RegSet allow)
{
IRIns *ir = IR(ref);
if (ra_hasreg(ir->r)) {
if (allow != RSET_EMPTY) { /* Fast path. */
ra_noweak(as, ir->r);
return ir->r;
}
fusespill:
/* Force a spill if only memory operands are allowed (asm_x87load). */
as->mrm.base = RID_ESP;
as->mrm.ofs = ra_spill(as, ir);
as->mrm.idx = RID_NONE;
return RID_MRM;
}
if (ir->o == IR_KNUM) {
RegSet avail = as->freeset & ~as->modset & RSET_FPR;
lj_assertA(allow != RSET_EMPTY, "no register allowed");
if (!(avail & (avail-1))) /* Fuse if less than two regs available. */
return asm_fuseloadk64(as, ir);
} else if (ref == REF_BASE || ir->o == IR_KINT64) {
RegSet avail = as->freeset & ~as->modset & RSET_GPR;
lj_assertA(allow != RSET_EMPTY, "no register allowed");
if (!(avail & (avail-1))) { /* Fuse if less than two regs available. */
if (ref == REF_BASE) {
#if LJ_GC64
as->mrm.ofs = (int32_t)dispofs(as, &J2G(as->J)->jit_base);
as->mrm.base = RID_DISPATCH;
#else
as->mrm.ofs = ptr2addr(&J2G(as->J)->jit_base);
as->mrm.base = RID_NONE;
#endif
as->mrm.idx = RID_NONE;
return RID_MRM;
} else {
return asm_fuseloadk64(as, ir);
}
}
} else if (mayfuse(as, ref)) {
RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
if (ir->o == IR_SLOAD) {
if (!(ir->op2 & (IRSLOAD_PARENT|IRSLOAD_CONVERT)) &&
noconflict(as, ref, IR_RETF, 0) &&
!(LJ_GC64 && irt_isaddr(ir->t))) {
as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
as->mrm.ofs = 8*((int32_t)ir->op1-1-LJ_FR2) +
(!LJ_FR2 && (ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
as->mrm.idx = RID_NONE;
return RID_MRM;
}
} else if (ir->o == IR_FLOAD) {
/* Generic fusion is only ok for 32 bit operand (but see asm_comp). */
if ((irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t)) &&
noconflict(as, ref, IR_FSTORE, 0)) {
asm_fusefref(as, ir, xallow);
return RID_MRM;
}
} else if (ir->o == IR_ALOAD || ir->o == IR_HLOAD || ir->o == IR_ULOAD) {
if (noconflict(as, ref, ir->o + IRDELTA_L2S, 0) &&
!(LJ_GC64 && irt_isaddr(ir->t))) {
asm_fuseahuref(as, ir->op1, xallow);
return RID_MRM;
}
} else if (ir->o == IR_XLOAD) {
/* Generic fusion is not ok for 8/16 bit operands (but see asm_comp).
** Fusing unaligned memory operands is ok on x86 (except for SIMD types).
*/
if ((!irt_typerange(ir->t, IRT_I8, IRT_U16)) &&
noconflict(as, ref, IR_XSTORE, 0)) {
asm_fusexref(as, ir->op1, xallow);
return RID_MRM;
}
} else if (ir->o == IR_VLOAD && !(LJ_GC64 && irt_isaddr(ir->t))) {
asm_fuseahuref(as, ir->op1, xallow);
as->mrm.ofs += 8 * ir->op2;
return RID_MRM;
}
}
if (ir->o == IR_FLOAD && ir->op1 == REF_NIL) {
asm_fusefref(as, ir, RSET_EMPTY);
return RID_MRM;
}
if (!(as->freeset & allow) && !emit_canremat(ref) &&
(allow == RSET_EMPTY || ra_hasspill(ir->s) || iscrossref(as, ref)))
goto fusespill;
return ra_allocref(as, ref, allow);
}
#if LJ_64
/* Don't fuse a 32 bit load into a 64 bit operation. */
static Reg asm_fuseloadm(ASMState *as, IRRef ref, RegSet allow, int is64)
{
if (is64 && !irt_is64(IR(ref)->t))
return ra_alloc1(as, ref, allow);
return asm_fuseload(as, ref, allow);
}
#else
#define asm_fuseloadm(as, ref, allow, is64) asm_fuseload(as, (ref), (allow))
#endif
/* -- Calls --------------------------------------------------------------- */
/* Count the required number of stack slots for a call. */
static int asm_count_call_slots(ASMState *as, const CCallInfo *ci, IRRef *args)
{
uint32_t i, nargs = CCI_XNARGS(ci);
int nslots = 0;
#if LJ_64
if (LJ_ABI_WIN) {
nslots = (int)(nargs*2); /* Only matters for more than four args. */
} else {
int ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
for (i = 0; i < nargs; i++)
if (args[i] && irt_isfp(IR(args[i])->t)) {
if (nfpr > 0) nfpr--; else nslots += 2;
} else {
if (ngpr > 0) ngpr--; else nslots += 2;
}
}
#else
int ngpr = 0;
if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
ngpr = 2;
else if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
ngpr = 1;
for (i = 0; i < nargs; i++)
if (args[i] && irt_isfp(IR(args[i])->t)) {
nslots += irt_isnum(IR(args[i])->t) ? 2 : 1;
} else {
if (ngpr > 0) ngpr--; else nslots++;
}
#endif
return nslots;
}
/* Generate a call to a C function. */
static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
{
uint32_t n, nargs = CCI_XNARGS(ci);
int32_t ofs = STACKARG_OFS;
#if LJ_64
uint32_t gprs = REGARG_GPRS;
Reg fpr = REGARG_FIRSTFPR;
#if !LJ_ABI_WIN
MCode *patchnfpr = NULL;
#endif
#else
uint32_t gprs = 0;
if ((ci->flags & CCI_CC_MASK) != CCI_CC_CDECL) {
if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
gprs = (REGARG_GPRS & 31);
else if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
gprs = REGARG_GPRS;
}
#endif
if ((void *)ci->func)
emit_call(as, ci->func);
#if LJ_64
if ((ci->flags & CCI_VARARG)) { /* Special handling for vararg calls. */
#if LJ_ABI_WIN
for (n = 0; n < 4 && n < nargs; n++) {
IRIns *ir = IR(args[n]);
if (irt_isfp(ir->t)) /* Duplicate FPRs in GPRs. */
emit_rr(as, XO_MOVDto, (irt_isnum(ir->t) ? REX_64 : 0) | (fpr+n),
((gprs >> (n*5)) & 31)); /* Either MOVD or MOVQ. */
}
#else
patchnfpr = --as->mcp; /* Indicate number of used FPRs in register al. */
*--as->mcp = XI_MOVrib | RID_EAX;
#endif
}
#endif
for (n = 0; n < nargs; n++) { /* Setup args. */
IRRef ref = args[n];
IRIns *ir = IR(ref);
Reg r;
#if LJ_64 && LJ_ABI_WIN
/* Windows/x64 argument registers are strictly positional. */
r = irt_isfp(ir->t) ? (fpr <= REGARG_LASTFPR ? fpr : 0) : (gprs & 31);
fpr++; gprs >>= 5;
#elif LJ_64
/* POSIX/x64 argument registers are used in order of appearance. */
if (irt_isfp(ir->t)) {
r = fpr <= REGARG_LASTFPR ? fpr++ : 0;
} else {
r = gprs & 31; gprs >>= 5;
}
#else
if (ref && irt_isfp(ir->t)) {
r = 0;
} else {
r = gprs & 31; gprs >>= 5;
if (!ref) continue;
}
#endif
if (r) { /* Argument is in a register. */
if (r < RID_MAX_GPR && ref < ASMREF_TMP1) {
#if LJ_64
if (LJ_GC64 ? !(ir->o == IR_KINT || ir->o == IR_KNULL) : ir->o == IR_KINT64)
emit_loadu64(as, r, ir_k64(ir)->u64);
else
#endif
emit_loadi(as, r, ir->i);
} else {
/* Must have been evicted. */
lj_assertA(rset_test(as->freeset, r), "reg %d not free", r);
if (ra_hasreg(ir->r)) {
ra_noweak(as, ir->r);
emit_movrr(as, ir, r, ir->r);
} else {
ra_allocref(as, ref, RID2RSET(r));
}
}
} else if (irt_isfp(ir->t)) { /* FP argument is on stack. */
lj_assertA(!(irt_isfloat(ir->t) && irref_isk(ref)),
"unexpected float constant");
if (LJ_32 && (ofs & 4) && irref_isk(ref)) {
/* Split stores for unaligned FP consts. */
emit_movmroi(as, RID_ESP, ofs, (int32_t)ir_knum(ir)->u32.lo);
emit_movmroi(as, RID_ESP, ofs+4, (int32_t)ir_knum(ir)->u32.hi);
} else {
r = ra_alloc1(as, ref, RSET_FPR);
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto,
r, RID_ESP, ofs);
}
ofs += (LJ_32 && irt_isfloat(ir->t)) ? 4 : 8;
} else { /* Non-FP argument is on stack. */
if (LJ_32 && ref < ASMREF_TMP1) {
emit_movmroi(as, RID_ESP, ofs, ir->i);
} else {
r = ra_alloc1(as, ref, RSET_GPR);
emit_movtomro(as, REX_64 + r, RID_ESP, ofs);
}
ofs += sizeof(intptr_t);
}
checkmclim(as);
}
#if LJ_64 && !LJ_ABI_WIN
if (patchnfpr) *patchnfpr = fpr - REGARG_FIRSTFPR;
#endif
}
/* Setup result reg/sp for call. Evict scratch regs. */
static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
{
RegSet drop = RSET_SCRATCH;
int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
if ((ci->flags & CCI_NOFPRCLOBBER))
drop &= ~RSET_FPR;
if (ra_hasreg(ir->r))
rset_clear(drop, ir->r); /* Dest reg handled below. */
if (hiop && ra_hasreg((ir+1)->r))
rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
ra_evictset(as, drop); /* Evictions must be performed first. */
if (ra_used(ir)) {
if (irt_isfp(ir->t)) {
int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
#if LJ_64
if ((ci->flags & CCI_CASTU64)) {
Reg dest = ir->r;
if (ra_hasreg(dest)) {
ra_free(as, dest);
ra_modified(as, dest);
emit_rr(as, XO_MOVD, dest|REX_64, RID_RET); /* Really MOVQ. */
}
if (ofs) emit_movtomro(as, RID_RET|REX_64, RID_ESP, ofs);
} else {
ra_destreg(as, ir, RID_FPRET);
}
#else
/* Number result is in x87 st0 for x86 calling convention. */
Reg dest = ir->r;
if (ra_hasreg(dest)) {
ra_free(as, dest);
ra_modified(as, dest);
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS,
dest, RID_ESP, ofs);
}
if ((ci->flags & CCI_CASTU64)) {
emit_movtomro(as, RID_RETLO, RID_ESP, ofs);
emit_movtomro(as, RID_RETHI, RID_ESP, ofs+4);
} else {
emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
}
#endif
} else if (hiop) {
ra_destpair(as, ir);
} else {
lj_assertA(!irt_ispri(ir->t), "PRI dest");
ra_destreg(as, ir, RID_RET);
}
} else if (LJ_32 && irt_isfp(ir->t) && !(ci->flags & CCI_CASTU64)) {
emit_x87op(as, XI_FPOP); /* Pop unused result from x87 st0. */
}
}
/* Return a constant function pointer or NULL for indirect calls. */
static void *asm_callx_func(ASMState *as, IRIns *irf, IRRef func)
{
#if LJ_32
UNUSED(as);
if (irref_isk(func))
return (void *)irf->i;
#else
if (irref_isk(func)) {
MCode *p;
if (irf->o == IR_KINT64)
p = (MCode *)(void *)ir_k64(irf)->u64;
else
p = (MCode *)(void *)(uintptr_t)(uint32_t)irf->i;
if (p - as->mcp == (int32_t)(p - as->mcp))
return p; /* Call target is still in +-2GB range. */
/* Avoid the indirect case of emit_call(). Try to hoist func addr. */
}
#endif
return NULL;
}
static void asm_callx(ASMState *as, IRIns *ir)
{
IRRef args[CCI_NARGS_MAX*2];
CCallInfo ci;
IRRef func;
IRIns *irf;
int32_t spadj = 0;
ci.flags = asm_callx_flags(as, ir);
asm_collectargs(as, ir, &ci, args);
asm_setupresult(as, ir, &ci);
#if LJ_32
/* Have to readjust stack after non-cdecl calls due to callee cleanup. */
if ((ci.flags & CCI_CC_MASK) != CCI_CC_CDECL)
spadj = 4 * asm_count_call_slots(as, &ci, args);
#endif
func = ir->op2; irf = IR(func);
if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
ci.func = (ASMFunction)asm_callx_func(as, irf, func);
if (!(void *)ci.func) {
/* Use a (hoistable) non-scratch register for indirect calls. */
RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
Reg r = ra_alloc1(as, func, allow);
if (LJ_32) emit_spsub(as, spadj); /* Above code may cause restores! */
emit_rr(as, XO_GROUP5, XOg_CALL, r);
} else if (LJ_32) {
emit_spsub(as, spadj);
}
asm_gencall(as, &ci, args);
}
/* -- Returns ------------------------------------------------------------- */
/* Return to lower frame. Guard that it goes to the right spot. */
static void asm_retf(ASMState *as, IRIns *ir)
{
Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
#if LJ_FR2
Reg rpc = ra_scratch(as, rset_exclude(RSET_GPR, base));
#endif
void *pc = ir_kptr(IR(ir->op2));
int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
as->topslot -= (BCReg)delta;
if ((int32_t)as->topslot < 0) as->topslot = 0;
irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
emit_setgl(as, base, jit_base);
emit_addptr(as, base, -8*delta);
asm_guardcc(as, CC_NE);
#if LJ_FR2
emit_rmro(as, XO_CMP, rpc|REX_GC64, base, -8);
emit_loadu64(as, rpc, u64ptr(pc));
#else
emit_gmroi(as, XG_ARITHi(XOg_CMP), base, -4, ptr2addr(pc));
#endif
}
/* -- Buffer operations --------------------------------------------------- */
#if LJ_HASBUFFER
static void asm_bufhdr_write(ASMState *as, Reg sb)
{
Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, sb));
IRIns irgc;
irgc.ot = IRT(0, IRT_PGC); /* GC type. */
emit_storeofs(as, &irgc, tmp, sb, offsetof(SBuf, L));
emit_opgl(as, XO_ARITH(XOg_OR), tmp|REX_GC64, cur_L);
emit_gri(as, XG_ARITHi(XOg_AND), tmp, SBUF_MASK_FLAG);
emit_loadofs(as, &irgc, tmp, sb, offsetof(SBuf, L));
}
#endif
/* -- Type conversions ---------------------------------------------------- */
static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
{
Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
Reg dest = ra_dest(as, ir, RSET_GPR);
asm_guardcc(as, CC_P);
asm_guardcc(as, CC_NE);
emit_rr(as, XO_UCOMISD, left, tmp);
emit_rr(as, XO_CVTSI2SD, tmp, dest);
emit_rr(as, XO_XORPS, tmp, tmp); /* Avoid partial register stall. */
emit_rr(as, XO_CVTTSD2SI, dest, left);
/* Can't fuse since left is needed twice. */
}
static void asm_tobit(ASMState *as, IRIns *ir)
{
Reg dest = ra_dest(as, ir, RSET_GPR);
Reg tmp = ra_noreg(IR(ir->op1)->r) ?
ra_alloc1(as, ir->op1, RSET_FPR) :
ra_scratch(as, RSET_FPR);
Reg right;
emit_rr(as, XO_MOVDto, tmp, dest);
right = asm_fuseload(as, ir->op2, rset_exclude(RSET_FPR, tmp));
emit_mrm(as, XO_ADDSD, tmp, right);
ra_left(as, tmp, ir->op1);
}
static void asm_conv(ASMState *as, IRIns *ir)
{
IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
int st64 = (st == IRT_I64 || st == IRT_U64 || (LJ_64 && st == IRT_P64));
int stfp = (st == IRT_NUM || st == IRT_FLOAT);
IRRef lref = ir->op1;
lj_assertA(irt_type(ir->t) != st, "inconsistent types for CONV");
lj_assertA(!(LJ_32 && (irt_isint64(ir->t) || st64)),
"IR %04d has unsplit 64 bit type",
(int)(ir - as->ir) - REF_BIAS);
if (irt_isfp(ir->t)) {
Reg dest = ra_dest(as, ir, RSET_FPR);
if (stfp) { /* FP to FP conversion. */
Reg left = asm_fuseload(as, lref, RSET_FPR);
emit_mrm(as, st == IRT_NUM ? XO_CVTSD2SS : XO_CVTSS2SD, dest, left);
if (left == dest) return; /* Avoid the XO_XORPS. */
} else if (LJ_32 && st == IRT_U32) { /* U32 to FP conversion on x86. */
/* number = (2^52+2^51 .. u32) - (2^52+2^51) */
cTValue *k = &as->J->k64[LJ_K64_TOBIT];
Reg bias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
if (irt_isfloat(ir->t))
emit_rr(as, XO_CVTSD2SS, dest, dest);
emit_rr(as, XO_SUBSD, dest, bias); /* Subtract 2^52+2^51 bias. */
emit_rr(as, XO_XORPS, dest, bias); /* Merge bias and integer. */
emit_rma(as, XO_MOVSD, bias, k);
emit_mrm(as, XO_MOVD, dest, asm_fuseload(as, lref, RSET_GPR));
return;
} else { /* Integer to FP conversion. */
Reg left = (LJ_64 && (st == IRT_U32 || st == IRT_U64)) ?
ra_alloc1(as, lref, RSET_GPR) :
asm_fuseloadm(as, lref, RSET_GPR, st64);
if (LJ_64 && st == IRT_U64) {
MCLabel l_end = emit_label(as);
cTValue *k = &as->J->k64[LJ_K64_2P64];
emit_rma(as, XO_ADDSD, dest, k); /* Add 2^64 to compensate. */
emit_sjcc(as, CC_NS, l_end);
emit_rr(as, XO_TEST, left|REX_64, left); /* Check if u64 >= 2^63. */
}
emit_mrm(as, irt_isnum(ir->t) ? XO_CVTSI2SD : XO_CVTSI2SS,
dest|((LJ_64 && (st64 || st == IRT_U32)) ? REX_64 : 0), left);
}
emit_rr(as, XO_XORPS, dest, dest); /* Avoid partial register stall. */
} else if (stfp) { /* FP to integer conversion. */
if (irt_isguard(ir->t)) {
/* Checked conversions are only supported from number to int. */
lj_assertA(irt_isint(ir->t) && st == IRT_NUM,
"bad type for checked CONV");
asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
} else {
Reg dest = ra_dest(as, ir, RSET_GPR);
x86Op op = st == IRT_NUM ? XO_CVTTSD2SI : XO_CVTTSS2SI;
if (LJ_64 ? irt_isu64(ir->t) : irt_isu32(ir->t)) {
/* LJ_64: For inputs >= 2^63 add -2^64, convert again. */
/* LJ_32: For inputs >= 2^31 add -2^31, convert again and add 2^31. */
Reg tmp = ra_noreg(IR(lref)->r) ? ra_alloc1(as, lref, RSET_FPR) :
ra_scratch(as, RSET_FPR);
MCLabel l_end = emit_label(as);
if (LJ_32)
emit_gri(as, XG_ARITHi(XOg_ADD), dest, (int32_t)0x80000000);
emit_rr(as, op, dest|REX_64, tmp);
if (st == IRT_NUM)
emit_rma(as, XO_ADDSD, tmp, &as->J->k64[LJ_K64_M2P64_31]);
else
emit_rma(as, XO_ADDSS, tmp, &as->J->k32[LJ_K32_M2P64_31]);
emit_sjcc(as, CC_NS, l_end);
emit_rr(as, XO_TEST, dest|REX_64, dest); /* Check if dest negative. */
emit_rr(as, op, dest|REX_64, tmp);
ra_left(as, tmp, lref);
} else {
if (LJ_64 && irt_isu32(ir->t))
emit_rr(as, XO_MOV, dest, dest); /* Zero hiword. */
emit_mrm(as, op,
dest|((LJ_64 &&
(irt_is64(ir->t) || irt_isu32(ir->t))) ? REX_64 : 0),
asm_fuseload(as, lref, RSET_FPR));
}
}
} else if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
Reg left, dest = ra_dest(as, ir, RSET_GPR);
RegSet allow = RSET_GPR;
x86Op op;
lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t), "bad type for CONV EXT");
if (st == IRT_I8) {
op = XO_MOVSXb; allow = RSET_GPR8; dest |= FORCE_REX;
} else if (st == IRT_U8) {
op = XO_MOVZXb; allow = RSET_GPR8; dest |= FORCE_REX;
} else if (st == IRT_I16) {
op = XO_MOVSXw;
} else {
op = XO_MOVZXw;
}
left = asm_fuseload(as, lref, allow);
/* Add extra MOV if source is already in wrong register. */
if (!LJ_64 && left != RID_MRM && !rset_test(allow, left)) {
Reg tmp = ra_scratch(as, allow);
emit_rr(as, op, dest, tmp);
emit_rr(as, XO_MOV, tmp, left);
} else {
emit_mrm(as, op, dest, left);
}
} else { /* 32/64 bit integer conversions. */
if (LJ_32) { /* Only need to handle 32/32 bit no-op (cast) on x86. */
Reg dest = ra_dest(as, ir, RSET_GPR);
ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
} else if (irt_is64(ir->t)) {
Reg dest = ra_dest(as, ir, RSET_GPR);
if (st64 || !(ir->op2 & IRCONV_SEXT)) {
/* 64/64 bit no-op (cast) or 32 to 64 bit zero extension. */
ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
} else { /* 32 to 64 bit sign extension. */
Reg left = asm_fuseload(as, lref, RSET_GPR);
emit_mrm(as, XO_MOVSXd, dest|REX_64, left);
}
} else {
Reg dest = ra_dest(as, ir, RSET_GPR);
if (st64 && !(ir->op2 & IRCONV_NONE)) {
Reg left = asm_fuseload(as, lref, RSET_GPR);
/* This is either a 32 bit reg/reg mov which zeroes the hiword
** or a load of the loword from a 64 bit address.
*/
emit_mrm(as, XO_MOV, dest, left);
} else { /* 32/32 bit no-op (cast). */
ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
}
}
}
}
#if LJ_32 && LJ_HASFFI
/* No SSE conversions to/from 64 bit on x86, so resort to ugly x87 code. */
/* 64 bit integer to FP conversion in 32 bit mode. */
static void asm_conv_fp_int64(ASMState *as, IRIns *ir)
{
Reg hi = ra_alloc1(as, ir->op1, RSET_GPR);
Reg lo = ra_alloc1(as, (ir-1)->op1, rset_exclude(RSET_GPR, hi));
int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
Reg dest = ir->r;
if (ra_hasreg(dest)) {
ra_free(as, dest);
ra_modified(as, dest);
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS, dest, RID_ESP, ofs);
}
emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
if (((ir-1)->op2 & IRCONV_SRCMASK) == IRT_U64) {
/* For inputs in [2^63,2^64-1] add 2^64 to compensate. */
MCLabel l_end = emit_label(as);
emit_rma(as, XO_FADDq, XOg_FADDq, &as->J->k64[LJ_K64_2P64]);
emit_sjcc(as, CC_NS, l_end);
emit_rr(as, XO_TEST, hi, hi); /* Check if u64 >= 2^63. */
} else {
lj_assertA(((ir-1)->op2 & IRCONV_SRCMASK) == IRT_I64, "bad type for CONV");
}
emit_rmro(as, XO_FILDq, XOg_FILDq, RID_ESP, 0);
/* NYI: Avoid narrow-to-wide store-to-load forwarding stall. */
emit_rmro(as, XO_MOVto, hi, RID_ESP, 4);
emit_rmro(as, XO_MOVto, lo, RID_ESP, 0);
}
/* FP to 64 bit integer conversion in 32 bit mode. */
static void asm_conv_int64_fp(ASMState *as, IRIns *ir)
{
IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
Reg lo, hi;
lj_assertA(st == IRT_NUM || st == IRT_FLOAT, "bad type for CONV");
lj_assertA(dt == IRT_I64 || dt == IRT_U64, "bad type for CONV");