-
Notifications
You must be signed in to change notification settings - Fork 933
/
vm_mips.dasc
5395 lines (5327 loc) · 144 KB
/
vm_mips.dasc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
|// Low-level VM code for MIPS CPUs.
|// Bytecode interpreter, fast functions and helper functions.
|// Copyright (C) 2005-2022 Mike Pall. See Copyright Notice in luajit.h
|//
|// MIPS soft-float support contributed by Djordje Kovacevic and
|// Stefan Pejic from RT-RK.com, sponsored by Cisco Systems, Inc.
|
|.arch mips
|.section code_op, code_sub
|
|.actionlist build_actionlist
|.globals GLOB_
|.globalnames globnames
|.externnames extnames
|
|// Note: The ragged indentation of the instructions is intentional.
|// The starting columns indicate data dependencies.
|
|//-----------------------------------------------------------------------
|
|// Fixed register assignments for the interpreter.
|// Don't use: r0 = 0, r26/r27 = reserved, r28 = gp, r29 = sp, r31 = ra
|
|.macro .FPU, a, b
|.if FPU
| a, b
|.endif
|.endmacro
|
|// The following must be C callee-save (but BASE is often refetched).
|.define BASE, r16 // Base of current Lua stack frame.
|.define KBASE, r17 // Constants of current Lua function.
|.define PC, r18 // Next PC.
|.define DISPATCH, r19 // Opcode dispatch table.
|.define LREG, r20 // Register holding lua_State (also in SAVE_L).
|.define MULTRES, r21 // Size of multi-result: (nresults+1)*8.
|
|.define JGL, r30 // On-trace: global_State + 32768.
|
|// Constants for type-comparisons, stores and conversions. C callee-save.
|.define TISNUM, r22
|.define TISNIL, r30
|.if FPU
|.define TOBIT, f30 // 2^52 + 2^51.
|.endif
|
|// The following temporaries are not saved across C calls, except for RA.
|.define RA, r23 // Callee-save.
|.define RB, r8
|.define RC, r9
|.define RD, r10
|.define INS, r11
|
|.define AT, r1 // Assembler temporary.
|.define TMP0, r12
|.define TMP1, r13
|.define TMP2, r14
|.define TMP3, r15
|
|// MIPS o32 calling convention.
|.define CFUNCADDR, r25
|.define CARG1, r4
|.define CARG2, r5
|.define CARG3, r6
|.define CARG4, r7
|
|.define CRET1, r2
|.define CRET2, r3
|
|.if ENDIAN_LE
|.define SFRETLO, CRET1
|.define SFRETHI, CRET2
|.define SFARG1LO, CARG1
|.define SFARG1HI, CARG2
|.define SFARG2LO, CARG3
|.define SFARG2HI, CARG4
|.else
|.define SFRETLO, CRET2
|.define SFRETHI, CRET1
|.define SFARG1LO, CARG2
|.define SFARG1HI, CARG1
|.define SFARG2LO, CARG4
|.define SFARG2HI, CARG3
|.endif
|
|.if FPU
|.define FARG1, f12
|.define FARG2, f14
|
|.define FRET1, f0
|.define FRET2, f2
|.endif
|
|// Stack layout while in interpreter. Must match with lj_frame.h.
|.if FPU // MIPS32 hard-float.
|
|.define CFRAME_SPACE, 112 // Delta for sp.
|
|.define SAVE_ERRF, 124(sp) // 32 bit C frame info.
|.define SAVE_NRES, 120(sp)
|.define SAVE_CFRAME, 116(sp)
|.define SAVE_L, 112(sp)
|//----- 8 byte aligned, ^^^^ 16 byte register save area, owned by interpreter.
|.define SAVE_GPR_, 72 // .. 72+10*4: 32 bit GPR saves.
|.define SAVE_FPR_, 24 // .. 24+6*8: 64 bit FPR saves.
|
|.else // MIPS32 soft-float
|
|.define CFRAME_SPACE, 64 // Delta for sp.
|
|.define SAVE_ERRF, 76(sp) // 32 bit C frame info.
|.define SAVE_NRES, 72(sp)
|.define SAVE_CFRAME, 68(sp)
|.define SAVE_L, 64(sp)
|//----- 8 byte aligned, ^^^^ 16 byte register save area, owned by interpreter.
|.define SAVE_GPR_, 24 // .. 24+10*4: 32 bit GPR saves.
|
|.endif
|
|.define SAVE_PC, 20(sp)
|.define ARG5, 16(sp)
|.define CSAVE_4, 12(sp)
|.define CSAVE_3, 8(sp)
|.define CSAVE_2, 4(sp)
|.define CSAVE_1, 0(sp)
|//----- 8 byte aligned, ^^^^ 16 byte register save area, owned by callee.
|
|.define ARG5_OFS, 16
|.define SAVE_MULTRES, ARG5
|
|//-----------------------------------------------------------------------
|
|.macro saveregs
| addiu sp, sp, -CFRAME_SPACE
| sw ra, SAVE_GPR_+9*4(sp)
| sw r30, SAVE_GPR_+8*4(sp)
| .FPU sdc1 f30, SAVE_FPR_+5*8(sp)
| sw r23, SAVE_GPR_+7*4(sp)
| sw r22, SAVE_GPR_+6*4(sp)
| .FPU sdc1 f28, SAVE_FPR_+4*8(sp)
| sw r21, SAVE_GPR_+5*4(sp)
| sw r20, SAVE_GPR_+4*4(sp)
| .FPU sdc1 f26, SAVE_FPR_+3*8(sp)
| sw r19, SAVE_GPR_+3*4(sp)
| sw r18, SAVE_GPR_+2*4(sp)
| .FPU sdc1 f24, SAVE_FPR_+2*8(sp)
| sw r17, SAVE_GPR_+1*4(sp)
| sw r16, SAVE_GPR_+0*4(sp)
| .FPU sdc1 f22, SAVE_FPR_+1*8(sp)
| .FPU sdc1 f20, SAVE_FPR_+0*8(sp)
|.endmacro
|
|.macro restoreregs_ret
| lw ra, SAVE_GPR_+9*4(sp)
| lw r30, SAVE_GPR_+8*4(sp)
| .FPU ldc1 f30, SAVE_FPR_+5*8(sp)
| lw r23, SAVE_GPR_+7*4(sp)
| lw r22, SAVE_GPR_+6*4(sp)
| .FPU ldc1 f28, SAVE_FPR_+4*8(sp)
| lw r21, SAVE_GPR_+5*4(sp)
| lw r20, SAVE_GPR_+4*4(sp)
| .FPU ldc1 f26, SAVE_FPR_+3*8(sp)
| lw r19, SAVE_GPR_+3*4(sp)
| lw r18, SAVE_GPR_+2*4(sp)
| .FPU ldc1 f24, SAVE_FPR_+2*8(sp)
| lw r17, SAVE_GPR_+1*4(sp)
| lw r16, SAVE_GPR_+0*4(sp)
| .FPU ldc1 f22, SAVE_FPR_+1*8(sp)
| .FPU ldc1 f20, SAVE_FPR_+0*8(sp)
| jr ra
| addiu sp, sp, CFRAME_SPACE
|.endmacro
|
|// Type definitions. Some of these are only used for documentation.
|.type L, lua_State, LREG
|.type GL, global_State
|.type TVALUE, TValue
|.type GCOBJ, GCobj
|.type STR, GCstr
|.type TAB, GCtab
|.type LFUNC, GCfuncL
|.type CFUNC, GCfuncC
|.type PROTO, GCproto
|.type UPVAL, GCupval
|.type NODE, Node
|.type NARGS8, int
|.type TRACE, GCtrace
|.type SBUF, SBuf
|
|//-----------------------------------------------------------------------
|
|// Trap for not-yet-implemented parts.
|.macro NYI; .long 0xec1cf0f0; .endmacro
|
|// Macros to mark delay slots.
|.macro ., a; a; .endmacro
|.macro ., a,b; a,b; .endmacro
|.macro ., a,b,c; a,b,c; .endmacro
|
|//-----------------------------------------------------------------------
|
|// Endian-specific defines.
|.if ENDIAN_LE
|.define FRAME_PC, -4
|.define FRAME_FUNC, -8
|.define HI, 4
|.define LO, 0
|.define OFS_RD, 2
|.define OFS_RA, 1
|.define OFS_OP, 0
|.else
|.define FRAME_PC, -8
|.define FRAME_FUNC, -4
|.define HI, 0
|.define LO, 4
|.define OFS_RD, 0
|.define OFS_RA, 2
|.define OFS_OP, 3
|.endif
|
|// Instruction decode.
|.macro decode_OP1, dst, ins; andi dst, ins, 0xff; .endmacro
|.macro decode_OP4a, dst, ins; andi dst, ins, 0xff; .endmacro
|.macro decode_OP4b, dst; sll dst, dst, 2; .endmacro
|.macro decode_RC4a, dst, ins; srl dst, ins, 14; .endmacro
|.macro decode_RC4b, dst; andi dst, dst, 0x3fc; .endmacro
|.macro decode_RD4b, dst; sll dst, dst, 2; .endmacro
|.macro decode_RA8a, dst, ins; srl dst, ins, 5; .endmacro
|.macro decode_RA8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RB8a, dst, ins; srl dst, ins, 21; .endmacro
|.macro decode_RB8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RD8a, dst, ins; srl dst, ins, 16; .endmacro
|.macro decode_RD8b, dst; sll dst, dst, 3; .endmacro
|.macro decode_RDtoRC8, dst, src; andi dst, src, 0x7f8; .endmacro
|
|// Instruction fetch.
|.macro ins_NEXT1
| lw INS, 0(PC)
| addiu PC, PC, 4
|.endmacro
|// Instruction decode+dispatch.
|.macro ins_NEXT2
| decode_OP4a TMP1, INS
| decode_OP4b TMP1
| addu TMP0, DISPATCH, TMP1
| decode_RD8a RD, INS
| lw AT, 0(TMP0)
| decode_RA8a RA, INS
| decode_RD8b RD
| jr AT
| decode_RA8b RA
|.endmacro
|.macro ins_NEXT
| ins_NEXT1
| ins_NEXT2
|.endmacro
|
|// Instruction footer.
|.if 1
| // Replicated dispatch. Less unpredictable branches, but higher I-Cache use.
| .define ins_next, ins_NEXT
| .define ins_next_, ins_NEXT
| .define ins_next1, ins_NEXT1
| .define ins_next2, ins_NEXT2
|.else
| // Common dispatch. Lower I-Cache use, only one (very) unpredictable branch.
| // Affects only certain kinds of benchmarks (and only with -j off).
| .macro ins_next
| b ->ins_next
| .endmacro
| .macro ins_next1
| .endmacro
| .macro ins_next2
| b ->ins_next
| .endmacro
| .macro ins_next_
| ->ins_next:
| ins_NEXT
| .endmacro
|.endif
|
|// Call decode and dispatch.
|.macro ins_callt
| // BASE = new base, RB = LFUNC/CFUNC, RC = nargs*8, FRAME_PC(BASE) = PC
| lw PC, LFUNC:RB->pc
| lw INS, 0(PC)
| addiu PC, PC, 4
| decode_OP4a TMP1, INS
| decode_RA8a RA, INS
| decode_OP4b TMP1
| decode_RA8b RA
| addu TMP0, DISPATCH, TMP1
| lw TMP0, 0(TMP0)
| jr TMP0
| addu RA, RA, BASE
|.endmacro
|
|.macro ins_call
| // BASE = new base, RB = LFUNC/CFUNC, RC = nargs*8, PC = caller PC
| sw PC, FRAME_PC(BASE)
| ins_callt
|.endmacro
|
|//-----------------------------------------------------------------------
|
|.macro branch_RD
| srl TMP0, RD, 1
| lui AT, (-(BCBIAS_J*4 >> 16) & 65535)
| addu TMP0, TMP0, AT
| addu PC, PC, TMP0
|.endmacro
|
|// Assumes DISPATCH is relative to GL.
#define DISPATCH_GL(field) (GG_DISP2G + (int)offsetof(global_State, field))
#define DISPATCH_J(field) (GG_DISP2J + (int)offsetof(jit_State, field))
#define GG_DISP2GOT (GG_OFS(got) - GG_OFS(dispatch))
#define DISPATCH_GOT(name) (GG_DISP2GOT + 4*LJ_GOT_##name)
|
#define PC2PROTO(field) ((int)offsetof(GCproto, field)-(int)sizeof(GCproto))
|
|.macro load_got, func
| lw CFUNCADDR, DISPATCH_GOT(func)(DISPATCH)
|.endmacro
|// Much faster. Sadly, there's no easy way to force the required code layout.
|// .macro call_intern, func; bal extern func; .endmacro
|.macro call_intern, func; jalr CFUNCADDR; .endmacro
|.macro call_extern; jalr CFUNCADDR; .endmacro
|.macro jmp_extern; jr CFUNCADDR; .endmacro
|
|.macro hotcheck, delta, target
| srl TMP1, PC, 1
| andi TMP1, TMP1, 126
| addu TMP1, TMP1, DISPATCH
| lhu TMP2, GG_DISP2HOT(TMP1)
| addiu TMP2, TMP2, -delta
| bltz TMP2, target
|. sh TMP2, GG_DISP2HOT(TMP1)
|.endmacro
|
|.macro hotloop
| hotcheck HOTCOUNT_LOOP, ->vm_hotloop
|.endmacro
|
|.macro hotcall
| hotcheck HOTCOUNT_CALL, ->vm_hotcall
|.endmacro
|
|// Set current VM state. Uses TMP0.
|.macro li_vmstate, st; li TMP0, ~LJ_VMST_..st; .endmacro
|.macro st_vmstate; sw TMP0, DISPATCH_GL(vmstate)(DISPATCH); .endmacro
|
|// Move table write barrier back. Overwrites mark and tmp.
|.macro barrierback, tab, mark, tmp, target
| lw tmp, DISPATCH_GL(gc.grayagain)(DISPATCH)
| andi mark, mark, ~LJ_GC_BLACK & 255 // black2gray(tab)
| sw tab, DISPATCH_GL(gc.grayagain)(DISPATCH)
| sb mark, tab->marked
| b target
|. sw tmp, tab->gclist
|.endmacro
|
|//-----------------------------------------------------------------------
/* Generate subroutines used by opcodes and other parts of the VM. */
/* The .code_sub section should be last to help static branch prediction. */
static void build_subroutines(BuildCtx *ctx)
{
|.code_sub
|
|//-----------------------------------------------------------------------
|//-- Return handling ----------------------------------------------------
|//-----------------------------------------------------------------------
|
|->vm_returnp:
| // See vm_return. Also: TMP2 = previous base.
| andi AT, PC, FRAME_P
| beqz AT, ->cont_dispatch
|. li TMP1, LJ_TTRUE
|
| // Return from pcall or xpcall fast func.
| lw PC, FRAME_PC(TMP2) // Fetch PC of previous frame.
| move BASE, TMP2 // Restore caller base.
| // Prepending may overwrite the pcall frame, so do it at the end.
| sw TMP1, FRAME_PC(RA) // Prepend true to results.
| addiu RA, RA, -8
|
|->vm_returnc:
| addiu RD, RD, 8 // RD = (nresults+1)*8.
| andi TMP0, PC, FRAME_TYPE
| beqz RD, ->vm_unwind_c_eh
|. li CRET1, LUA_YIELD
| beqz TMP0, ->BC_RET_Z // Handle regular return to Lua.
|. move MULTRES, RD
|
|->vm_return:
| // BASE = base, RA = resultptr, RD/MULTRES = (nresults+1)*8, PC = return
| // TMP0 = PC & FRAME_TYPE
| li TMP2, -8
| xori AT, TMP0, FRAME_C
| and TMP2, PC, TMP2
| bnez AT, ->vm_returnp
|. subu TMP2, BASE, TMP2 // TMP2 = previous base.
|
| addiu TMP1, RD, -8
| sw TMP2, L->base
| li_vmstate C
| lw TMP2, SAVE_NRES
| addiu BASE, BASE, -8
| st_vmstate
| beqz TMP1, >2
|. sll TMP2, TMP2, 3
|1:
| addiu TMP1, TMP1, -8
| lw SFRETHI, HI(RA)
| lw SFRETLO, LO(RA)
| addiu RA, RA, 8
| sw SFRETHI, HI(BASE)
| sw SFRETLO, LO(BASE)
| bnez TMP1, <1
|. addiu BASE, BASE, 8
|
|2:
| bne TMP2, RD, >6
|3:
|. sw BASE, L->top // Store new top.
|
|->vm_leave_cp:
| lw TMP0, SAVE_CFRAME // Restore previous C frame.
| move CRET1, r0 // Ok return status for vm_pcall.
| sw TMP0, L->cframe
|
|->vm_leave_unw:
| restoreregs_ret
|
|6:
| lw TMP1, L->maxstack
| slt AT, TMP2, RD
| bnez AT, >7 // Less results wanted?
| // More results wanted. Check stack size and fill up results with nil.
|. slt AT, BASE, TMP1
| beqz AT, >8
|. nop
| sw TISNIL, HI(BASE)
| addiu RD, RD, 8
| b <2
|. addiu BASE, BASE, 8
|
|7: // Less results wanted.
| subu TMP0, RD, TMP2
| subu TMP0, BASE, TMP0 // Either keep top or shrink it.
| b <3
|. movn BASE, TMP0, TMP2 // LUA_MULTRET+1 case?
|
|8: // Corner case: need to grow stack for filling up results.
| // This can happen if:
| // - A C function grows the stack (a lot).
| // - The GC shrinks the stack in between.
| // - A return back from a lua_call() with (high) nresults adjustment.
| load_got lj_state_growstack
| move MULTRES, RD
| srl CARG2, TMP2, 3
| call_intern lj_state_growstack // (lua_State *L, int n)
|. move CARG1, L
| lw TMP2, SAVE_NRES
| lw BASE, L->top // Need the (realloced) L->top in BASE.
| move RD, MULTRES
| b <2
|. sll TMP2, TMP2, 3
|
|->vm_unwind_c: // Unwind C stack, return from vm_pcall.
| // (void *cframe, int errcode)
| move sp, CARG1
| move CRET1, CARG2
|->vm_unwind_c_eh: // Landing pad for external unwinder.
| lw L, SAVE_L
| li TMP0, ~LJ_VMST_C
| lw GL:TMP1, L->glref
| b ->vm_leave_unw
|. sw TMP0, GL:TMP1->vmstate
|
|->vm_unwind_ff: // Unwind C stack, return from ff pcall.
| // (void *cframe)
| li AT, -4
| and sp, CARG1, AT
|->vm_unwind_ff_eh: // Landing pad for external unwinder.
| lw L, SAVE_L
| .FPU lui TMP3, 0x59c0 // TOBIT = 2^52 + 2^51 (float).
| li TISNUM, LJ_TISNUM // Setup type comparison constants.
| li TISNIL, LJ_TNIL
| lw BASE, L->base
| lw DISPATCH, L->glref // Setup pointer to dispatch table.
| .FPU mtc1 TMP3, TOBIT
| li TMP1, LJ_TFALSE
| li_vmstate INTERP
| lw PC, FRAME_PC(BASE) // Fetch PC of previous frame.
| .FPU cvt.d.s TOBIT, TOBIT
| addiu RA, BASE, -8 // Results start at BASE-8.
| addiu DISPATCH, DISPATCH, GG_G2DISP
| sw TMP1, HI(RA) // Prepend false to error message.
| st_vmstate
| b ->vm_returnc
|. li RD, 16 // 2 results: false + error message.
|
|->vm_unwind_stub: // Jump to exit stub from unwinder.
| jr CARG1
|. move ra, CARG2
|
|//-----------------------------------------------------------------------
|//-- Grow stack for calls -----------------------------------------------
|//-----------------------------------------------------------------------
|
|->vm_growstack_c: // Grow stack for C function.
| b >2
|. li CARG2, LUA_MINSTACK
|
|->vm_growstack_l: // Grow stack for Lua function.
| // BASE = new base, RA = BASE+framesize*8, RC = nargs*8, PC = first PC
| addu RC, BASE, RC
| subu RA, RA, BASE
| sw BASE, L->base
| addiu PC, PC, 4 // Must point after first instruction.
| sw RC, L->top
| srl CARG2, RA, 3
|2:
| // L->base = new base, L->top = top
| load_got lj_state_growstack
| sw PC, SAVE_PC
| call_intern lj_state_growstack // (lua_State *L, int n)
|. move CARG1, L
| lw BASE, L->base
| lw RC, L->top
| lw LFUNC:RB, FRAME_FUNC(BASE)
| subu RC, RC, BASE
| // BASE = new base, RB = LFUNC/CFUNC, RC = nargs*8, FRAME_PC(BASE) = PC
| ins_callt // Just retry the call.
|
|//-----------------------------------------------------------------------
|//-- Entry points into the assembler VM ---------------------------------
|//-----------------------------------------------------------------------
|
|->vm_resume: // Setup C frame and resume thread.
| // (lua_State *L, TValue *base, int nres1 = 0, ptrdiff_t ef = 0)
| saveregs
| move L, CARG1
| lw DISPATCH, L->glref // Setup pointer to dispatch table.
| move BASE, CARG2
| lbu TMP1, L->status
| sw L, SAVE_L
| li PC, FRAME_CP
| addiu TMP0, sp, CFRAME_RESUME
| addiu DISPATCH, DISPATCH, GG_G2DISP
| sw r0, SAVE_NRES
| sw r0, SAVE_ERRF
| sw CARG1, SAVE_PC // Any value outside of bytecode is ok.
| sw r0, SAVE_CFRAME
| beqz TMP1, >3
|. sw TMP0, L->cframe
|
| // Resume after yield (like a return).
| sw L, DISPATCH_GL(cur_L)(DISPATCH)
| move RA, BASE
| lw BASE, L->base
| li TISNUM, LJ_TISNUM // Setup type comparison constants.
| lw TMP1, L->top
| lw PC, FRAME_PC(BASE)
| .FPU lui TMP3, 0x59c0 // TOBIT = 2^52 + 2^51 (float).
| subu RD, TMP1, BASE
| .FPU mtc1 TMP3, TOBIT
| sb r0, L->status
| .FPU cvt.d.s TOBIT, TOBIT
| li_vmstate INTERP
| addiu RD, RD, 8
| st_vmstate
| move MULTRES, RD
| andi TMP0, PC, FRAME_TYPE
| beqz TMP0, ->BC_RET_Z
|. li TISNIL, LJ_TNIL
| b ->vm_return
|. nop
|
|->vm_pcall: // Setup protected C frame and enter VM.
| // (lua_State *L, TValue *base, int nres1, ptrdiff_t ef)
| saveregs
| sw CARG4, SAVE_ERRF
| b >1
|. li PC, FRAME_CP
|
|->vm_call: // Setup C frame and enter VM.
| // (lua_State *L, TValue *base, int nres1)
| saveregs
| li PC, FRAME_C
|
|1: // Entry point for vm_pcall above (PC = ftype).
| lw TMP1, L:CARG1->cframe
| move L, CARG1
| sw CARG3, SAVE_NRES
| lw DISPATCH, L->glref // Setup pointer to dispatch table.
| sw CARG1, SAVE_L
| move BASE, CARG2
| addiu DISPATCH, DISPATCH, GG_G2DISP
| sw CARG1, SAVE_PC // Any value outside of bytecode is ok.
| sw TMP1, SAVE_CFRAME
| sw sp, L->cframe // Add our C frame to cframe chain.
|
|3: // Entry point for vm_cpcall/vm_resume (BASE = base, PC = ftype).
| sw L, DISPATCH_GL(cur_L)(DISPATCH)
| lw TMP2, L->base // TMP2 = old base (used in vmeta_call).
| li TISNUM, LJ_TISNUM // Setup type comparison constants.
| .FPU lui TMP3, 0x59c0 // TOBIT = 2^52 + 2^51 (float).
| lw TMP1, L->top
| .FPU mtc1 TMP3, TOBIT
| addu PC, PC, BASE
| subu NARGS8:RC, TMP1, BASE
| subu PC, PC, TMP2 // PC = frame delta + frame type
| .FPU cvt.d.s TOBIT, TOBIT
| li_vmstate INTERP
| li TISNIL, LJ_TNIL
| st_vmstate
|
|->vm_call_dispatch:
| // TMP2 = old base, BASE = new base, RC = nargs*8, PC = caller PC
| lw TMP0, FRAME_PC(BASE)
| li AT, LJ_TFUNC
| bne TMP0, AT, ->vmeta_call
|. lw LFUNC:RB, FRAME_FUNC(BASE)
|
|->vm_call_dispatch_f:
| ins_call
| // BASE = new base, RB = func, RC = nargs*8, PC = caller PC
|
|->vm_cpcall: // Setup protected C frame, call C.
| // (lua_State *L, lua_CFunction func, void *ud, lua_CPFunction cp)
| saveregs
| move L, CARG1
| lw TMP0, L:CARG1->stack
| sw CARG1, SAVE_L
| lw TMP1, L->top
| lw DISPATCH, L->glref // Setup pointer to dispatch table.
| sw CARG1, SAVE_PC // Any value outside of bytecode is ok.
| subu TMP0, TMP0, TMP1 // Compute -savestack(L, L->top).
| lw TMP1, L->cframe
| addiu DISPATCH, DISPATCH, GG_G2DISP
| sw TMP0, SAVE_NRES // Neg. delta means cframe w/o frame.
| sw r0, SAVE_ERRF // No error function.
| sw TMP1, SAVE_CFRAME
| sw sp, L->cframe // Add our C frame to cframe chain.
| sw L, DISPATCH_GL(cur_L)(DISPATCH)
| jalr CARG4 // (lua_State *L, lua_CFunction func, void *ud)
|. move CFUNCADDR, CARG4
| move BASE, CRET1
| bnez CRET1, <3 // Else continue with the call.
|. li PC, FRAME_CP
| b ->vm_leave_cp // No base? Just remove C frame.
|. nop
|
|//-----------------------------------------------------------------------
|//-- Metamethod handling ------------------------------------------------
|//-----------------------------------------------------------------------
|
|// The lj_meta_* functions (except for lj_meta_cat) don't reallocate the
|// stack, so BASE doesn't need to be reloaded across these calls.
|
|//-- Continuation dispatch ----------------------------------------------
|
|->cont_dispatch:
| // BASE = meta base, RA = resultptr, RD = (nresults+1)*8
| lw TMP0, -16+LO(BASE) // Continuation.
| move RB, BASE
| move BASE, TMP2 // Restore caller BASE.
| lw LFUNC:TMP1, FRAME_FUNC(TMP2)
|.if FFI
| sltiu AT, TMP0, 2
|.endif
| lw PC, -16+HI(RB) // Restore PC from [cont|PC].
| addu TMP2, RA, RD
|.if FFI
| bnez AT, >1
|.endif
|. sw TISNIL, -8+HI(TMP2) // Ensure one valid arg.
| lw TMP1, LFUNC:TMP1->pc
| // BASE = base, RA = resultptr, RB = meta base
| jr TMP0 // Jump to continuation.
|. lw KBASE, PC2PROTO(k)(TMP1)
|
|.if FFI
|1:
| bnez TMP0, ->cont_ffi_callback // cont = 1: return from FFI callback.
| // cont = 0: tailcall from C function.
|. addiu TMP1, RB, -16
| b ->vm_call_tail
|. subu RC, TMP1, BASE
|.endif
|
|->cont_cat: // RA = resultptr, RB = meta base
| lw INS, -4(PC)
| addiu CARG2, RB, -16
| lw SFRETHI, HI(RA)
| lw SFRETLO, LO(RA)
| decode_RB8a MULTRES, INS
| decode_RA8a RA, INS
| decode_RB8b MULTRES
| decode_RA8b RA
| addu TMP1, BASE, MULTRES
| sw BASE, L->base
| subu CARG3, CARG2, TMP1
| sw SFRETHI, HI(CARG2)
| bne TMP1, CARG2, ->BC_CAT_Z
|. sw SFRETLO, LO(CARG2)
| addu RA, BASE, RA
| sw SFRETHI, HI(RA)
| b ->cont_nop
|. sw SFRETLO, LO(RA)
|
|//-- Table indexing metamethods -----------------------------------------
|
|->vmeta_tgets1:
| addiu CARG3, DISPATCH, DISPATCH_GL(tmptv)
| li TMP0, LJ_TSTR
| sw STR:RC, LO(CARG3)
| b >1
|. sw TMP0, HI(CARG3)
|
|->vmeta_tgets:
| addiu CARG2, DISPATCH, DISPATCH_GL(tmptv)
| li TMP0, LJ_TTAB
| sw TAB:RB, LO(CARG2)
| addiu CARG3, DISPATCH, DISPATCH_GL(tmptv2)
| sw TMP0, HI(CARG2)
| li TMP1, LJ_TSTR
| sw STR:RC, LO(CARG3)
| b >1
|. sw TMP1, HI(CARG3)
|
|->vmeta_tgetb: // TMP0 = index
| addiu CARG3, DISPATCH, DISPATCH_GL(tmptv)
| sw TMP0, LO(CARG3)
| sw TISNUM, HI(CARG3)
|
|->vmeta_tgetv:
|1:
| load_got lj_meta_tget
| sw BASE, L->base
| sw PC, SAVE_PC
| call_intern lj_meta_tget // (lua_State *L, TValue *o, TValue *k)
|. move CARG1, L
| // Returns TValue * (finished) or NULL (metamethod).
| beqz CRET1, >3
|. addiu TMP1, BASE, -FRAME_CONT
| lw SFARG1HI, HI(CRET1)
| lw SFARG2HI, LO(CRET1)
| ins_next1
| sw SFARG1HI, HI(RA)
| sw SFARG2HI, LO(RA)
| ins_next2
|
|3: // Call __index metamethod.
| // BASE = base, L->top = new base, stack = cont/func/t/k
| lw BASE, L->top
| sw PC, -16+HI(BASE) // [cont|PC]
| subu PC, BASE, TMP1
| lw LFUNC:RB, FRAME_FUNC(BASE) // Guaranteed to be a function here.
| b ->vm_call_dispatch_f
|. li NARGS8:RC, 16 // 2 args for func(t, k).
|
|->vmeta_tgetr:
| load_got lj_tab_getinth
| call_intern lj_tab_getinth // (GCtab *t, int32_t key)
|. nop
| // Returns cTValue * or NULL.
| beqz CRET1, ->BC_TGETR_Z
|. move SFARG2HI, TISNIL
| lw SFARG2HI, HI(CRET1)
| b ->BC_TGETR_Z
|. lw SFARG2LO, LO(CRET1)
|
|//-----------------------------------------------------------------------
|
|->vmeta_tsets1:
| addiu CARG3, DISPATCH, DISPATCH_GL(tmptv)
| li TMP0, LJ_TSTR
| sw STR:RC, LO(CARG3)
| b >1
|. sw TMP0, HI(CARG3)
|
|->vmeta_tsets:
| addiu CARG2, DISPATCH, DISPATCH_GL(tmptv)
| li TMP0, LJ_TTAB
| sw TAB:RB, LO(CARG2)
| addiu CARG3, DISPATCH, DISPATCH_GL(tmptv2)
| sw TMP0, HI(CARG2)
| li TMP1, LJ_TSTR
| sw STR:RC, LO(CARG3)
| b >1
|. sw TMP1, HI(CARG3)
|
|->vmeta_tsetb: // TMP0 = index
| addiu CARG3, DISPATCH, DISPATCH_GL(tmptv)
| sw TMP0, LO(CARG3)
| sw TISNUM, HI(CARG3)
|
|->vmeta_tsetv:
|1:
| load_got lj_meta_tset
| sw BASE, L->base
| sw PC, SAVE_PC
| call_intern lj_meta_tset // (lua_State *L, TValue *o, TValue *k)
|. move CARG1, L
| // Returns TValue * (finished) or NULL (metamethod).
| lw SFARG1HI, HI(RA)
| beqz CRET1, >3
|. lw SFARG1LO, LO(RA)
| // NOBARRIER: lj_meta_tset ensures the table is not black.
| ins_next1
| sw SFARG1HI, HI(CRET1)
| sw SFARG1LO, LO(CRET1)
| ins_next2
|
|3: // Call __newindex metamethod.
| // BASE = base, L->top = new base, stack = cont/func/t/k/(v)
| addiu TMP1, BASE, -FRAME_CONT
| lw BASE, L->top
| sw PC, -16+HI(BASE) // [cont|PC]
| subu PC, BASE, TMP1
| lw LFUNC:RB, FRAME_FUNC(BASE) // Guaranteed to be a function here.
| sw SFARG1HI, 16+HI(BASE) // Copy value to third argument.
| sw SFARG1LO, 16+LO(BASE)
| b ->vm_call_dispatch_f
|. li NARGS8:RC, 24 // 3 args for func(t, k, v)
|
|->vmeta_tsetr:
| load_got lj_tab_setinth
| sw BASE, L->base
| sw PC, SAVE_PC
| call_intern lj_tab_setinth // (lua_State *L, GCtab *t, int32_t key)
|. move CARG1, L
| // Returns TValue *.
| b ->BC_TSETR_Z
|. nop
|
|//-- Comparison metamethods ---------------------------------------------
|
|->vmeta_comp:
| // RA/RD point to o1/o2.
| move CARG2, RA
| move CARG3, RD
| load_got lj_meta_comp
| addiu PC, PC, -4
| sw BASE, L->base
| sw PC, SAVE_PC
| decode_OP1 CARG4, INS
| call_intern lj_meta_comp // (lua_State *L, TValue *o1, *o2, int op)
|. move CARG1, L
| // Returns 0/1 or TValue * (metamethod).
|3:
| sltiu AT, CRET1, 2
| beqz AT, ->vmeta_binop
| negu TMP2, CRET1
|4:
| lhu RD, OFS_RD(PC)
| addiu PC, PC, 4
| lui TMP1, (-(BCBIAS_J*4 >> 16) & 65535)
| sll RD, RD, 2
| addu RD, RD, TMP1
| and RD, RD, TMP2
| addu PC, PC, RD
|->cont_nop:
| ins_next
|
|->cont_ra: // RA = resultptr
| lbu TMP1, -4+OFS_RA(PC)
| lw SFRETHI, HI(RA)
| lw SFRETLO, LO(RA)
| sll TMP1, TMP1, 3
| addu TMP1, BASE, TMP1
| sw SFRETHI, HI(TMP1)
| b ->cont_nop
|. sw SFRETLO, LO(TMP1)
|
|->cont_condt: // RA = resultptr
| lw TMP0, HI(RA)
| sltiu AT, TMP0, LJ_TISTRUECOND
| b <4
|. negu TMP2, AT // Branch if result is true.
|
|->cont_condf: // RA = resultptr
| lw TMP0, HI(RA)
| sltiu AT, TMP0, LJ_TISTRUECOND
| b <4
|. addiu TMP2, AT, -1 // Branch if result is false.
|
|->vmeta_equal:
| // SFARG1LO/SFARG2LO point to o1/o2. TMP0 is set to 0/1.
| load_got lj_meta_equal
| move CARG2, SFARG1LO
| move CARG3, SFARG2LO
| move CARG4, TMP0
| addiu PC, PC, -4
| sw BASE, L->base
| sw PC, SAVE_PC
| call_intern lj_meta_equal // (lua_State *L, GCobj *o1, *o2, int ne)
|. move CARG1, L
| // Returns 0/1 or TValue * (metamethod).
| b <3
|. nop
|
|->vmeta_equal_cd:
|.if FFI
| load_got lj_meta_equal_cd
| move CARG2, INS
| addiu PC, PC, -4
| sw BASE, L->base
| sw PC, SAVE_PC
| call_intern lj_meta_equal_cd // (lua_State *L, BCIns op)
|. move CARG1, L
| // Returns 0/1 or TValue * (metamethod).
| b <3
|. nop
|.endif
|
|->vmeta_istype:
| load_got lj_meta_istype
| addiu PC, PC, -4
| sw BASE, L->base
| srl CARG2, RA, 3
| srl CARG3, RD, 3
| sw PC, SAVE_PC
| call_intern lj_meta_istype // (lua_State *L, BCReg ra, BCReg tp)
|. move CARG1, L
| b ->cont_nop
|. nop
|
|//-- Arithmetic metamethods ---------------------------------------------
|
|->vmeta_unm:
| move RC, RB
|
|->vmeta_arith:
| load_got lj_meta_arith
| decode_OP1 TMP0, INS
| sw BASE, L->base
| move CARG2, RA
| sw PC, SAVE_PC
| move CARG3, RB
| move CARG4, RC
| sw TMP0, ARG5
| call_intern lj_meta_arith // (lua_State *L, TValue *ra,*rb,*rc, BCReg op)
|. move CARG1, L
| // Returns NULL (finished) or TValue * (metamethod).
| beqz CRET1, ->cont_nop
|. nop
|
| // Call metamethod for binary op.
|->vmeta_binop:
| // BASE = old base, CRET1 = new base, stack = cont/func/o1/o2
| subu TMP1, CRET1, BASE
| sw PC, -16+HI(CRET1) // [cont|PC]
| move TMP2, BASE
| addiu PC, TMP1, FRAME_CONT
| move BASE, CRET1
| b ->vm_call_dispatch
|. li NARGS8:RC, 16 // 2 args for func(o1, o2).
|
|->vmeta_len:
| // CARG2 already set by BC_LEN.
#if LJ_52
| move MULTRES, CARG1
#endif
| load_got lj_meta_len
| sw BASE, L->base
| sw PC, SAVE_PC
| call_intern lj_meta_len // (lua_State *L, TValue *o)
|. move CARG1, L
| // Returns NULL (retry) or TValue * (metamethod base).
#if LJ_52
| bnez CRET1, ->vmeta_binop // Binop call for compatibility.
|. nop
| b ->BC_LEN_Z
|. move CARG1, MULTRES
#else
| b ->vmeta_binop // Binop call for compatibility.
|. nop
#endif
|
|//-- Call metamethod ----------------------------------------------------
|
|->vmeta_call: // Resolve and call __call metamethod.
| // TMP2 = old base, BASE = new base, RC = nargs*8
| load_got lj_meta_call
| sw TMP2, L->base // This is the callers base!
| addiu CARG2, BASE, -8
| sw PC, SAVE_PC
| addu CARG3, BASE, RC
| move MULTRES, NARGS8:RC
| call_intern lj_meta_call // (lua_State *L, TValue *func, TValue *top)
|. move CARG1, L
| lw LFUNC:RB, FRAME_FUNC(BASE) // Guaranteed to be a function here.
| addiu NARGS8:RC, MULTRES, 8 // Got one more argument now.
| ins_call
|
|->vmeta_callt: // Resolve __call for BC_CALLT.