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lj_asm_ppc.h
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lj_asm_ppc.h
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/*
** PPC IR assembler (SSA IR -> machine code).
** Copyright (C) 2005-2020 Mike Pall. See Copyright Notice in luajit.h
*/
/* -- Register allocator extensions --------------------------------------- */
/* Allocate a register with a hint. */
static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
{
Reg r = IR(ref)->r;
if (ra_noreg(r)) {
if (!ra_hashint(r) && !iscrossref(as, ref))
ra_sethint(IR(ref)->r, hint); /* Propagate register hint. */
r = ra_allocref(as, ref, allow);
}
ra_noweak(as, r);
return r;
}
/* Allocate two source registers for three-operand instructions. */
static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
{
IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
Reg left = irl->r, right = irr->r;
if (ra_hasreg(left)) {
ra_noweak(as, left);
if (ra_noreg(right))
right = ra_allocref(as, ir->op2, rset_exclude(allow, left));
else
ra_noweak(as, right);
} else if (ra_hasreg(right)) {
ra_noweak(as, right);
left = ra_allocref(as, ir->op1, rset_exclude(allow, right));
} else if (ra_hashint(right)) {
right = ra_allocref(as, ir->op2, allow);
left = ra_alloc1(as, ir->op1, rset_exclude(allow, right));
} else {
left = ra_allocref(as, ir->op1, allow);
right = ra_alloc1(as, ir->op2, rset_exclude(allow, left));
}
return left | (right << 8);
}
/* -- Guard handling ------------------------------------------------------ */
/* Setup exit stubs after the end of each trace. */
static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
{
ExitNo i;
MCode *mxp = as->mctop;
if (mxp - (nexits + 3 + MCLIM_REDZONE) < as->mclim)
asm_mclimit(as);
/* 1: mflr r0; bl ->vm_exit_handler; li r0, traceno; bl <1; bl <1; ... */
for (i = nexits-1; (int32_t)i >= 0; i--)
*--mxp = PPCI_BL|(((-3-i)&0x00ffffffu)<<2);
*--mxp = PPCI_LI|PPCF_T(RID_TMP)|as->T->traceno; /* Read by exit handler. */
mxp--;
*mxp = PPCI_BL|((((MCode *)(void *)lj_vm_exit_handler-mxp)&0x00ffffffu)<<2);
*--mxp = PPCI_MFLR|PPCF_T(RID_TMP);
as->mctop = mxp;
}
static MCode *asm_exitstub_addr(ASMState *as, ExitNo exitno)
{
/* Keep this in-sync with exitstub_trace_addr(). */
return as->mctop + exitno + 3;
}
/* Emit conditional branch to exit for guard. */
static void asm_guardcc(ASMState *as, PPCCC cc)
{
MCode *target = asm_exitstub_addr(as, as->snapno);
MCode *p = as->mcp;
if (LJ_UNLIKELY(p == as->invmcp)) {
as->loopinv = 1;
*p = PPCI_B | (((target-p) & 0x00ffffffu) << 2);
emit_condbranch(as, PPCI_BC, cc^4, p);
return;
}
emit_condbranch(as, PPCI_BC, cc, target);
}
/* -- Operand fusion ------------------------------------------------------ */
/* Limit linear search to this distance. Avoids O(n^2) behavior. */
#define CONFLICT_SEARCH_LIM 31
/* Check if there's no conflicting instruction between curins and ref. */
static int noconflict(ASMState *as, IRRef ref, IROp conflict)
{
IRIns *ir = as->ir;
IRRef i = as->curins;
if (i > ref + CONFLICT_SEARCH_LIM)
return 0; /* Give up, ref is too far away. */
while (--i > ref)
if (ir[i].o == conflict)
return 0; /* Conflict found. */
return 1; /* Ok, no conflict. */
}
/* Fuse the array base of colocated arrays. */
static int32_t asm_fuseabase(ASMState *as, IRRef ref)
{
IRIns *ir = IR(ref);
if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
!neverfuse(as) && noconflict(as, ref, IR_NEWREF))
return (int32_t)sizeof(GCtab);
return 0;
}
/* Indicates load/store indexed is ok. */
#define AHUREF_LSX ((int32_t)0x80000000)
/* Fuse array/hash/upvalue reference into register+offset operand. */
static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow)
{
IRIns *ir = IR(ref);
if (ra_noreg(ir->r)) {
if (ir->o == IR_AREF) {
if (mayfuse(as, ref)) {
if (irref_isk(ir->op2)) {
IRRef tab = IR(ir->op1)->op1;
int32_t ofs = asm_fuseabase(as, tab);
IRRef refa = ofs ? tab : ir->op1;
ofs += 8*IR(ir->op2)->i;
if (checki16(ofs)) {
*ofsp = ofs;
return ra_alloc1(as, refa, allow);
}
}
if (*ofsp == AHUREF_LSX) {
Reg base = ra_alloc1(as, ir->op1, allow);
Reg idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
return base | (idx << 8);
}
}
} else if (ir->o == IR_HREFK) {
if (mayfuse(as, ref)) {
int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
if (checki16(ofs)) {
*ofsp = ofs;
return ra_alloc1(as, ir->op1, allow);
}
}
} else if (ir->o == IR_UREFC) {
if (irref_isk(ir->op1)) {
GCfunc *fn = ir_kfunc(IR(ir->op1));
int32_t ofs = i32ptr(&gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.tv);
int32_t jgl = (intptr_t)J2G(as->J);
if ((uint32_t)(ofs-jgl) < 65536) {
*ofsp = ofs-jgl-32768;
return RID_JGL;
} else {
*ofsp = (int16_t)ofs;
return ra_allock(as, ofs-(int16_t)ofs, allow);
}
}
}
}
*ofsp = 0;
return ra_alloc1(as, ref, allow);
}
/* Fuse XLOAD/XSTORE reference into load/store operand. */
static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
RegSet allow, int32_t ofs)
{
IRIns *ir = IR(ref);
Reg base;
if (ra_noreg(ir->r) && canfuse(as, ir)) {
if (ir->o == IR_ADD) {
int32_t ofs2;
if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
ofs = ofs2;
ref = ir->op1;
} else if (ofs == 0) {
Reg right, left = ra_alloc2(as, ir, allow);
right = (left >> 8); left &= 255;
emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
return;
}
} else if (ir->o == IR_STRREF) {
lua_assert(ofs == 0);
ofs = (int32_t)sizeof(GCstr);
if (irref_isk(ir->op2)) {
ofs += IR(ir->op2)->i;
ref = ir->op1;
} else if (irref_isk(ir->op1)) {
ofs += IR(ir->op1)->i;
ref = ir->op2;
} else {
/* NYI: Fuse ADD with constant. */
Reg tmp, right, left = ra_alloc2(as, ir, allow);
right = (left >> 8); left &= 255;
tmp = ra_scratch(as, rset_exclude(rset_exclude(allow, left), right));
emit_fai(as, pi, rt, tmp, ofs);
emit_tab(as, PPCI_ADD, tmp, left, right);
return;
}
if (!checki16(ofs)) {
Reg left = ra_alloc1(as, ref, allow);
Reg right = ra_allock(as, ofs, rset_exclude(allow, left));
emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
return;
}
}
}
base = ra_alloc1(as, ref, allow);
emit_fai(as, pi, rt, base, ofs);
}
/* Fuse XLOAD/XSTORE reference into indexed-only load/store operand. */
static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
RegSet allow)
{
IRIns *ira = IR(ref);
Reg right, left;
if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
left = ra_alloc2(as, ira, allow);
right = (left >> 8); left &= 255;
} else {
right = ra_alloc1(as, ref, allow);
left = RID_R0;
}
emit_tab(as, pi, rt, left, right);
}
#if !LJ_SOFTFP
/* Fuse to multiply-add/sub instruction. */
static int asm_fusemadd(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pir)
{
IRRef lref = ir->op1, rref = ir->op2;
IRIns *irm;
if (lref != rref &&
((mayfuse(as, lref) && (irm = IR(lref), irm->o == IR_MUL) &&
ra_noreg(irm->r)) ||
(mayfuse(as, rref) && (irm = IR(rref), irm->o == IR_MUL) &&
(rref = lref, pi = pir, ra_noreg(irm->r))))) {
Reg dest = ra_dest(as, ir, RSET_FPR);
Reg add = ra_alloc1(as, rref, RSET_FPR);
Reg right, left = ra_alloc2(as, irm, rset_exclude(RSET_FPR, add));
right = (left >> 8); left &= 255;
emit_facb(as, pi, dest, left, right, add);
return 1;
}
return 0;
}
#endif
/* -- Calls --------------------------------------------------------------- */
/* Generate a call to a C function. */
static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
{
uint32_t n, nargs = CCI_XNARGS(ci);
int32_t ofs = 8;
Reg gpr = REGARG_FIRSTGPR;
#if !LJ_SOFTFP
Reg fpr = REGARG_FIRSTFPR;
#endif
if ((void *)ci->func)
emit_call(as, (void *)ci->func);
for (n = 0; n < nargs; n++) { /* Setup args. */
IRRef ref = args[n];
if (ref) {
IRIns *ir = IR(ref);
#if !LJ_SOFTFP
if (irt_isfp(ir->t)) {
if (fpr <= REGARG_LASTFPR) {
lua_assert(rset_test(as->freeset, fpr)); /* Already evicted. */
ra_leftov(as, fpr, ref);
fpr++;
} else {
Reg r = ra_alloc1(as, ref, RSET_FPR);
if (irt_isnum(ir->t)) ofs = (ofs + 4) & ~4;
emit_spstore(as, ir, r, ofs);
ofs += irt_isnum(ir->t) ? 8 : 4;
}
} else
#endif
{
if (gpr <= REGARG_LASTGPR) {
lua_assert(rset_test(as->freeset, gpr)); /* Already evicted. */
ra_leftov(as, gpr, ref);
gpr++;
} else {
Reg r = ra_alloc1(as, ref, RSET_GPR);
emit_spstore(as, ir, r, ofs);
ofs += 4;
}
}
} else {
if (gpr <= REGARG_LASTGPR)
gpr++;
else
ofs += 4;
}
checkmclim(as);
}
#if !LJ_SOFTFP
if ((ci->flags & CCI_VARARG)) /* Vararg calls need to know about FPR use. */
emit_tab(as, fpr == REGARG_FIRSTFPR ? PPCI_CRXOR : PPCI_CREQV, 6, 6, 6);
#endif
}
/* Setup result reg/sp for call. Evict scratch regs. */
static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
{
RegSet drop = RSET_SCRATCH;
int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
#if !LJ_SOFTFP
if ((ci->flags & CCI_NOFPRCLOBBER))
drop &= ~RSET_FPR;
#endif
if (ra_hasreg(ir->r))
rset_clear(drop, ir->r); /* Dest reg handled below. */
if (hiop && ra_hasreg((ir+1)->r))
rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
ra_evictset(as, drop); /* Evictions must be performed first. */
if (ra_used(ir)) {
lua_assert(!irt_ispri(ir->t));
if (!LJ_SOFTFP && irt_isfp(ir->t)) {
if ((ci->flags & CCI_CASTU64)) {
/* Use spill slot or temp slots. */
int32_t ofs = ir->s ? sps_scale(ir->s) : SPOFS_TMP;
Reg dest = ir->r;
if (ra_hasreg(dest)) {
ra_free(as, dest);
ra_modified(as, dest);
emit_fai(as, PPCI_LFD, dest, RID_SP, ofs);
}
emit_tai(as, PPCI_STW, RID_RETHI, RID_SP, ofs);
emit_tai(as, PPCI_STW, RID_RETLO, RID_SP, ofs+4);
} else {
ra_destreg(as, ir, RID_FPRET);
}
#if LJ_32
} else if (hiop) {
ra_destpair(as, ir);
#endif
} else {
ra_destreg(as, ir, RID_RET);
}
}
}
static void asm_callx(ASMState *as, IRIns *ir)
{
IRRef args[CCI_NARGS_MAX*2];
CCallInfo ci;
IRRef func;
IRIns *irf;
ci.flags = asm_callx_flags(as, ir);
asm_collectargs(as, ir, &ci, args);
asm_setupresult(as, ir, &ci);
func = ir->op2; irf = IR(func);
if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
if (irref_isk(func)) { /* Call to constant address. */
ci.func = (ASMFunction)(void *)(intptr_t)(irf->i);
} else { /* Need a non-argument register for indirect calls. */
RegSet allow = RSET_GPR & ~RSET_RANGE(RID_R0, REGARG_LASTGPR+1);
Reg freg = ra_alloc1(as, func, allow);
*--as->mcp = PPCI_BCTRL;
*--as->mcp = PPCI_MTCTR | PPCF_T(freg);
ci.func = (ASMFunction)(void *)0;
}
asm_gencall(as, &ci, args);
}
/* -- Returns ------------------------------------------------------------- */
/* Return to lower frame. Guard that it goes to the right spot. */
static void asm_retf(ASMState *as, IRIns *ir)
{
Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
void *pc = ir_kptr(IR(ir->op2));
int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
as->topslot -= (BCReg)delta;
if ((int32_t)as->topslot < 0) as->topslot = 0;
irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
emit_setgl(as, base, jit_base);
emit_addptr(as, base, -8*delta);
asm_guardcc(as, CC_NE);
emit_ab(as, PPCI_CMPW, RID_TMP,
ra_allock(as, i32ptr(pc), rset_exclude(RSET_GPR, base)));
emit_tai(as, PPCI_LWZ, RID_TMP, base, -8);
}
/* -- Type conversions ---------------------------------------------------- */
#if !LJ_SOFTFP
static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
{
RegSet allow = RSET_FPR;
Reg tmp = ra_scratch(as, rset_clear(allow, left));
Reg fbias = ra_scratch(as, rset_clear(allow, tmp));
Reg dest = ra_dest(as, ir, RSET_GPR);
Reg hibias = ra_allock(as, 0x43300000, rset_exclude(RSET_GPR, dest));
asm_guardcc(as, CC_NE);
emit_fab(as, PPCI_FCMPU, 0, tmp, left);
emit_fab(as, PPCI_FSUB, tmp, tmp, fbias);
emit_fai(as, PPCI_LFD, tmp, RID_SP, SPOFS_TMP);
emit_tai(as, PPCI_STW, RID_TMP, RID_SP, SPOFS_TMPLO);
emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
emit_asi(as, PPCI_XORIS, RID_TMP, dest, 0x8000);
emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
emit_lsptr(as, PPCI_LFS, (fbias & 31),
(void *)&as->J->k32[LJ_K32_2P52_2P31], RSET_GPR);
emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
emit_fb(as, PPCI_FCTIWZ, tmp, left);
}
static void asm_tobit(ASMState *as, IRIns *ir)
{
RegSet allow = RSET_FPR;
Reg dest = ra_dest(as, ir, RSET_GPR);
Reg left = ra_alloc1(as, ir->op1, allow);
Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
Reg tmp = ra_scratch(as, rset_clear(allow, right));
emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
emit_fab(as, PPCI_FADD, tmp, left, right);
}
#endif
static void asm_conv(ASMState *as, IRIns *ir)
{
IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
#if !LJ_SOFTFP
int stfp = (st == IRT_NUM || st == IRT_FLOAT);
#endif
IRRef lref = ir->op1;
lua_assert(!(irt_isint64(ir->t) ||
(st == IRT_I64 || st == IRT_U64))); /* Handled by SPLIT. */
#if LJ_SOFTFP
/* FP conversions are handled by SPLIT. */
lua_assert(!irt_isfp(ir->t) && !(st == IRT_NUM || st == IRT_FLOAT));
/* Can't check for same types: SPLIT uses CONV int.int + BXOR for sfp NEG. */
#else
lua_assert(irt_type(ir->t) != st);
if (irt_isfp(ir->t)) {
Reg dest = ra_dest(as, ir, RSET_FPR);
if (stfp) { /* FP to FP conversion. */
if (st == IRT_NUM) /* double -> float conversion. */
emit_fb(as, PPCI_FRSP, dest, ra_alloc1(as, lref, RSET_FPR));
else /* float -> double conversion is a no-op on PPC. */
ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
} else { /* Integer to FP conversion. */
/* IRT_INT: Flip hibit, bias with 2^52, subtract 2^52+2^31. */
/* IRT_U32: Bias with 2^52, subtract 2^52. */
RegSet allow = RSET_GPR;
Reg left = ra_alloc1(as, lref, allow);
Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, left));
Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
if (irt_isfloat(ir->t)) emit_fb(as, PPCI_FRSP, dest, dest);
emit_fab(as, PPCI_FSUB, dest, dest, fbias);
emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
emit_lsptr(as, PPCI_LFS, (fbias & 31),
&as->J->k32[st == IRT_U32 ? LJ_K32_2P52 : LJ_K32_2P52_2P31],
rset_clear(allow, hibias));
emit_tai(as, PPCI_STW, st == IRT_U32 ? left : RID_TMP,
RID_SP, SPOFS_TMPLO);
emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
if (st != IRT_U32) emit_asi(as, PPCI_XORIS, RID_TMP, left, 0x8000);
}
} else if (stfp) { /* FP to integer conversion. */
if (irt_isguard(ir->t)) {
/* Checked conversions are only supported from number to int. */
lua_assert(irt_isint(ir->t) && st == IRT_NUM);
asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
} else {
Reg dest = ra_dest(as, ir, RSET_GPR);
Reg left = ra_alloc1(as, lref, RSET_FPR);
Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
if (irt_isu32(ir->t)) {
/* Convert both x and x-2^31 to int and merge results. */
Reg tmpi = ra_scratch(as, rset_exclude(RSET_GPR, dest));
emit_asb(as, PPCI_OR, dest, dest, tmpi); /* Select with mask idiom. */
emit_asb(as, PPCI_AND, tmpi, tmpi, RID_TMP);
emit_asb(as, PPCI_ANDC, dest, dest, RID_TMP);
emit_tai(as, PPCI_LWZ, tmpi, RID_SP, SPOFS_TMPLO); /* tmp = (int)(x) */
emit_tai(as, PPCI_ADDIS, dest, dest, 0x8000); /* dest += 2^31 */
emit_asb(as, PPCI_SRAWI, RID_TMP, dest, 31); /* mask = -(dest < 0) */
emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
emit_tai(as, PPCI_LWZ, dest,
RID_SP, SPOFS_TMPLO); /* dest = (int)(x-2^31) */
emit_fb(as, PPCI_FCTIWZ, tmp, left);
emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
emit_fb(as, PPCI_FCTIWZ, tmp, tmp);
emit_fab(as, PPCI_FSUB, tmp, left, tmp);
emit_lsptr(as, PPCI_LFS, (tmp & 31),
(void *)&as->J->k32[LJ_K32_2P31], RSET_GPR);
} else {
emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
emit_fb(as, PPCI_FCTIWZ, tmp, left);
}
}
} else
#endif
{
Reg dest = ra_dest(as, ir, RSET_GPR);
if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
if ((ir->op2 & IRCONV_SEXT))
emit_as(as, st == IRT_I8 ? PPCI_EXTSB : PPCI_EXTSH, dest, left);
else
emit_rot(as, PPCI_RLWINM, dest, left, 0, st == IRT_U8 ? 24 : 16, 31);
} else { /* 32/64 bit integer conversions. */
/* Only need to handle 32/32 bit no-op (cast) on 32 bit archs. */
ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
}
}
}
static void asm_strto(ASMState *as, IRIns *ir)
{
const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
IRRef args[2];
int32_t ofs = SPOFS_TMP;
#if LJ_SOFTFP
ra_evictset(as, RSET_SCRATCH);
if (ra_used(ir)) {
if (ra_hasspill(ir->s) && ra_hasspill((ir+1)->s) &&
(ir->s & 1) == LJ_BE && (ir->s ^ 1) == (ir+1)->s) {
int i;
for (i = 0; i < 2; i++) {
Reg r = (ir+i)->r;
if (ra_hasreg(r)) {
ra_free(as, r);
ra_modified(as, r);
emit_spload(as, ir+i, r, sps_scale((ir+i)->s));
}
}
ofs = sps_scale(ir->s & ~1);
} else {
Reg rhi = ra_dest(as, ir+1, RSET_GPR);
Reg rlo = ra_dest(as, ir, rset_exclude(RSET_GPR, rhi));
emit_tai(as, PPCI_LWZ, rhi, RID_SP, ofs);
emit_tai(as, PPCI_LWZ, rlo, RID_SP, ofs+4);
}
}
#else
RegSet drop = RSET_SCRATCH;
if (ra_hasreg(ir->r)) rset_set(drop, ir->r); /* Spill dest reg (if any). */
ra_evictset(as, drop);
if (ir->s) ofs = sps_scale(ir->s);
#endif
asm_guardcc(as, CC_EQ);
emit_ai(as, PPCI_CMPWI, RID_RET, 0); /* Test return status. */
args[0] = ir->op1; /* GCstr *str */
args[1] = ASMREF_TMP1; /* TValue *n */
asm_gencall(as, ci, args);
/* Store the result to the spill slot or temp slots. */
emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_SP, ofs);
}
/* -- Memory references --------------------------------------------------- */
/* Get pointer to TValue. */
static void asm_tvptr(ASMState *as, Reg dest, IRRef ref)
{
IRIns *ir = IR(ref);
if (irt_isnum(ir->t)) {
if (irref_isk(ref)) /* Use the number constant itself as a TValue. */
ra_allockreg(as, i32ptr(ir_knum(ir)), dest);
else /* Otherwise force a spill and use the spill slot. */
emit_tai(as, PPCI_ADDI, dest, RID_SP, ra_spill(as, ir));
} else {
/* Otherwise use g->tmptv to hold the TValue. */
RegSet allow = rset_exclude(RSET_GPR, dest);
Reg type;
emit_tai(as, PPCI_ADDI, dest, RID_JGL, (int32_t)offsetof(global_State, tmptv)-32768);
if (!irt_ispri(ir->t)) {
Reg src = ra_alloc1(as, ref, allow);
emit_setgl(as, src, tmptv.gcr);
}
if (LJ_SOFTFP && (ir+1)->o == IR_HIOP)
type = ra_alloc1(as, ref+1, allow);
else
type = ra_allock(as, irt_toitype(ir->t), allow);
emit_setgl(as, type, tmptv.it);
}
}
static void asm_aref(ASMState *as, IRIns *ir)
{
Reg dest = ra_dest(as, ir, RSET_GPR);
Reg idx, base;
if (irref_isk(ir->op2)) {
IRRef tab = IR(ir->op1)->op1;
int32_t ofs = asm_fuseabase(as, tab);
IRRef refa = ofs ? tab : ir->op1;
ofs += 8*IR(ir->op2)->i;
if (checki16(ofs)) {
base = ra_alloc1(as, refa, RSET_GPR);
emit_tai(as, PPCI_ADDI, dest, base, ofs);
return;
}
}
base = ra_alloc1(as, ir->op1, RSET_GPR);
idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
emit_tab(as, PPCI_ADD, dest, RID_TMP, base);
emit_slwi(as, RID_TMP, idx, 3);
}
/* Inlined hash lookup. Specialized for key type and for const keys.
** The equivalent C code is:
** Node *n = hashkey(t, key);
** do {
** if (lj_obj_equal(&n->key, key)) return &n->val;
** } while ((n = nextnode(n)));
** return niltv(L);
*/
static void asm_href(ASMState *as, IRIns *ir, IROp merge)
{
RegSet allow = RSET_GPR;
int destused = ra_used(ir);
Reg dest = ra_dest(as, ir, allow);
Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
Reg key = RID_NONE, tmp1 = RID_TMP, tmp2;
Reg tisnum = RID_NONE, tmpnum = RID_NONE;
IRRef refkey = ir->op2;
IRIns *irkey = IR(refkey);
int isk = irref_isk(refkey);
IRType1 kt = irkey->t;
uint32_t khash;
MCLabel l_end, l_loop, l_next;
rset_clear(allow, tab);
#if LJ_SOFTFP
if (!isk) {
key = ra_alloc1(as, refkey, allow);
rset_clear(allow, key);
if (irkey[1].o == IR_HIOP) {
if (ra_hasreg((irkey+1)->r)) {
tmpnum = (irkey+1)->r;
ra_noweak(as, tmpnum);
} else {
tmpnum = ra_allocref(as, refkey+1, allow);
}
rset_clear(allow, tmpnum);
}
}
#else
if (irt_isnum(kt)) {
key = ra_alloc1(as, refkey, RSET_FPR);
tmpnum = ra_scratch(as, rset_exclude(RSET_FPR, key));
tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
rset_clear(allow, tisnum);
} else if (!irt_ispri(kt)) {
key = ra_alloc1(as, refkey, allow);
rset_clear(allow, key);
}
#endif
tmp2 = ra_scratch(as, allow);
rset_clear(allow, tmp2);
/* Key not found in chain: jump to exit (if merged) or load niltv. */
l_end = emit_label(as);
as->invmcp = NULL;
if (merge == IR_NE)
asm_guardcc(as, CC_EQ);
else if (destused)
emit_loada(as, dest, niltvg(J2G(as->J)));
/* Follow hash chain until the end. */
l_loop = --as->mcp;
emit_ai(as, PPCI_CMPWI, dest, 0);
emit_tai(as, PPCI_LWZ, dest, dest, (int32_t)offsetof(Node, next));
l_next = emit_label(as);
/* Type and value comparison. */
if (merge == IR_EQ)
asm_guardcc(as, CC_EQ);
else
emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
if (!LJ_SOFTFP && irt_isnum(kt)) {
emit_fab(as, PPCI_FCMPU, 0, tmpnum, key);
emit_condbranch(as, PPCI_BC, CC_GE, l_next);
emit_ab(as, PPCI_CMPLW, tmp1, tisnum);
emit_fai(as, PPCI_LFD, tmpnum, dest, (int32_t)offsetof(Node, key.n));
} else {
if (!irt_ispri(kt)) {
emit_ab(as, PPCI_CMPW, tmp2, key);
emit_condbranch(as, PPCI_BC, CC_NE, l_next);
}
if (LJ_SOFTFP && ra_hasreg(tmpnum))
emit_ab(as, PPCI_CMPW, tmp1, tmpnum);
else
emit_ai(as, PPCI_CMPWI, tmp1, irt_toitype(irkey->t));
if (!irt_ispri(kt))
emit_tai(as, PPCI_LWZ, tmp2, dest, (int32_t)offsetof(Node, key.gcr));
}
emit_tai(as, PPCI_LWZ, tmp1, dest, (int32_t)offsetof(Node, key.it));
*l_loop = PPCI_BC | PPCF_Y | PPCF_CC(CC_NE) |
(((char *)as->mcp-(char *)l_loop) & 0xffffu);
/* Load main position relative to tab->node into dest. */
khash = isk ? ir_khash(irkey) : 1;
if (khash == 0) {
emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
} else {
Reg tmphash = tmp1;
if (isk)
tmphash = ra_allock(as, khash, allow);
emit_tab(as, PPCI_ADD, dest, dest, tmp1);
emit_tai(as, PPCI_MULLI, tmp1, tmp1, sizeof(Node));
emit_asb(as, PPCI_AND, tmp1, tmp2, tmphash);
emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
emit_tai(as, PPCI_LWZ, tmp2, tab, (int32_t)offsetof(GCtab, hmask));
if (isk) {
/* Nothing to do. */
} else if (irt_isstr(kt)) {
emit_tai(as, PPCI_LWZ, tmp1, key, (int32_t)offsetof(GCstr, hash));
} else { /* Must match with hash*() in lj_tab.c. */
emit_tab(as, PPCI_SUBF, tmp1, tmp2, tmp1);
emit_rotlwi(as, tmp2, tmp2, HASH_ROT3);
emit_asb(as, PPCI_XOR, tmp1, tmp1, tmp2);
emit_rotlwi(as, tmp1, tmp1, (HASH_ROT2+HASH_ROT1)&31);
emit_tab(as, PPCI_SUBF, tmp2, dest, tmp2);
if (LJ_SOFTFP ? (irkey[1].o == IR_HIOP) : irt_isnum(kt)) {
#if LJ_SOFTFP
emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
emit_rotlwi(as, dest, tmp1, HASH_ROT1);
emit_tab(as, PPCI_ADD, tmp1, tmpnum, tmpnum);
#else
int32_t ofs = ra_spill(as, irkey);
emit_asb(as, PPCI_XOR, tmp2, tmp2, tmp1);
emit_rotlwi(as, dest, tmp1, HASH_ROT1);
emit_tab(as, PPCI_ADD, tmp1, tmp1, tmp1);
emit_tai(as, PPCI_LWZ, tmp2, RID_SP, ofs+4);
emit_tai(as, PPCI_LWZ, tmp1, RID_SP, ofs);
#endif
} else {
emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
emit_rotlwi(as, dest, tmp1, HASH_ROT1);
emit_tai(as, PPCI_ADDI, tmp1, tmp2, HASH_BIAS);
emit_tai(as, PPCI_ADDIS, tmp2, key, (HASH_BIAS + 32768)>>16);
}
}
}
}
static void asm_hrefk(ASMState *as, IRIns *ir)
{
IRIns *kslot = IR(ir->op2);
IRIns *irkey = IR(kslot->op1);
int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
int32_t kofs = ofs + (int32_t)offsetof(Node, key);
Reg dest = (ra_used(ir)||ofs > 32736) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
Reg key = RID_NONE, type = RID_TMP, idx = node;
RegSet allow = rset_exclude(RSET_GPR, node);
lua_assert(ofs % sizeof(Node) == 0);
if (ofs > 32736) {
idx = dest;
rset_clear(allow, dest);
kofs = (int32_t)offsetof(Node, key);
} else if (ra_hasreg(dest)) {
emit_tai(as, PPCI_ADDI, dest, node, ofs);
}
asm_guardcc(as, CC_NE);
if (!irt_ispri(irkey->t)) {
key = ra_scratch(as, allow);
rset_clear(allow, key);
}
rset_clear(allow, type);
if (irt_isnum(irkey->t)) {
emit_cmpi(as, key, (int32_t)ir_knum(irkey)->u32.lo);
asm_guardcc(as, CC_NE);
emit_cmpi(as, type, (int32_t)ir_knum(irkey)->u32.hi);
} else {
if (ra_hasreg(key)) {
emit_cmpi(as, key, irkey->i); /* May use RID_TMP, i.e. type. */
asm_guardcc(as, CC_NE);
}
emit_ai(as, PPCI_CMPWI, type, irt_toitype(irkey->t));
}
if (ra_hasreg(key)) emit_tai(as, PPCI_LWZ, key, idx, kofs+4);
emit_tai(as, PPCI_LWZ, type, idx, kofs);
if (ofs > 32736) {
emit_tai(as, PPCI_ADDIS, dest, dest, (ofs + 32768) >> 16);
emit_tai(as, PPCI_ADDI, dest, node, ofs);
}
}
static void asm_uref(ASMState *as, IRIns *ir)
{
Reg dest = ra_dest(as, ir, RSET_GPR);
if (irref_isk(ir->op1)) {
GCfunc *fn = ir_kfunc(IR(ir->op1));
MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
emit_lsptr(as, PPCI_LWZ, dest, v, RSET_GPR);
} else {
Reg uv = ra_scratch(as, RSET_GPR);
Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
if (ir->o == IR_UREFC) {
asm_guardcc(as, CC_NE);
emit_ai(as, PPCI_CMPWI, RID_TMP, 1);
emit_tai(as, PPCI_ADDI, dest, uv, (int32_t)offsetof(GCupval, tv));
emit_tai(as, PPCI_LBZ, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
} else {
emit_tai(as, PPCI_LWZ, dest, uv, (int32_t)offsetof(GCupval, v));
}
emit_tai(as, PPCI_LWZ, uv, func,
(int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
}
}
static void asm_fref(ASMState *as, IRIns *ir)
{
UNUSED(as); UNUSED(ir);
lua_assert(!ra_used(ir));
}
static void asm_strref(ASMState *as, IRIns *ir)
{
Reg dest = ra_dest(as, ir, RSET_GPR);
IRRef ref = ir->op2, refk = ir->op1;
int32_t ofs = (int32_t)sizeof(GCstr);
Reg r;
if (irref_isk(ref)) {
IRRef tmp = refk; refk = ref; ref = tmp;
} else if (!irref_isk(refk)) {
Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
IRIns *irr = IR(ir->op2);
if (ra_hasreg(irr->r)) {
ra_noweak(as, irr->r);
right = irr->r;
} else if (mayfuse(as, irr->op2) &&
irr->o == IR_ADD && irref_isk(irr->op2) &&
checki16(ofs + IR(irr->op2)->i)) {
ofs += IR(irr->op2)->i;
right = ra_alloc1(as, irr->op1, rset_exclude(RSET_GPR, left));
} else {
right = ra_allocref(as, ir->op2, rset_exclude(RSET_GPR, left));
}
emit_tai(as, PPCI_ADDI, dest, dest, ofs);
emit_tab(as, PPCI_ADD, dest, left, right);
return;
}
r = ra_alloc1(as, ref, RSET_GPR);
ofs += IR(refk)->i;
if (checki16(ofs))
emit_tai(as, PPCI_ADDI, dest, r, ofs);
else
emit_tab(as, PPCI_ADD, dest, r,
ra_allock(as, ofs, rset_exclude(RSET_GPR, r)));
}
/* -- Loads and stores ---------------------------------------------------- */
static PPCIns asm_fxloadins(IRIns *ir)
{
switch (irt_type(ir->t)) {
case IRT_I8: return PPCI_LBZ; /* Needs sign-extension. */
case IRT_U8: return PPCI_LBZ;
case IRT_I16: return PPCI_LHA;
case IRT_U16: return PPCI_LHZ;
case IRT_NUM: lua_assert(!LJ_SOFTFP); return PPCI_LFD;
case IRT_FLOAT: if (!LJ_SOFTFP) return PPCI_LFS;
default: return PPCI_LWZ;
}
}
static PPCIns asm_fxstoreins(IRIns *ir)
{
switch (irt_type(ir->t)) {
case IRT_I8: case IRT_U8: return PPCI_STB;
case IRT_I16: case IRT_U16: return PPCI_STH;
case IRT_NUM: lua_assert(!LJ_SOFTFP); return PPCI_STFD;
case IRT_FLOAT: if (!LJ_SOFTFP) return PPCI_STFS;
default: return PPCI_STW;
}
}
static void asm_fload(ASMState *as, IRIns *ir)
{
Reg dest = ra_dest(as, ir, RSET_GPR);
PPCIns pi = asm_fxloadins(ir);
Reg idx;
int32_t ofs;
if (ir->op1 == REF_NIL) {
idx = RID_JGL;
ofs = (ir->op2 << 2) - 32768;
} else {
idx = ra_alloc1(as, ir->op1, RSET_GPR);
if (ir->op2 == IRFL_TAB_ARRAY) {
ofs = asm_fuseabase(as, ir->op1);
if (ofs) { /* Turn the t->array load into an add for colocated arrays. */
emit_tai(as, PPCI_ADDI, dest, idx, ofs);
return;
}
}
ofs = field_ofs[ir->op2];
}
lua_assert(!irt_isi8(ir->t));
emit_tai(as, pi, dest, idx, ofs);
}
static void asm_fstore(ASMState *as, IRIns *ir)
{
if (ir->r != RID_SINK) {
Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
IRIns *irf = IR(ir->op1);
Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
int32_t ofs = field_ofs[irf->op2];
PPCIns pi = asm_fxstoreins(ir);
emit_tai(as, pi, src, idx, ofs);
}
}
static void asm_xload(ASMState *as, IRIns *ir)
{
Reg dest = ra_dest(as, ir,
(!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
lua_assert(!(ir->op2 & IRXLOAD_UNALIGNED));
if (irt_isi8(ir->t))
emit_as(as, PPCI_EXTSB, dest, dest);
asm_fusexref(as, asm_fxloadins(ir), dest, ir->op1, RSET_GPR, 0);
}
static void asm_xstore_(ASMState *as, IRIns *ir, int32_t ofs)
{
IRIns *irb;
if (ir->r == RID_SINK)
return;
if (ofs == 0 && mayfuse(as, ir->op2) && (irb = IR(ir->op2))->o == IR_BSWAP &&
ra_noreg(irb->r) && (irt_isint(ir->t) || irt_isu32(ir->t))) {
/* Fuse BSWAP with XSTORE to stwbrx. */
Reg src = ra_alloc1(as, irb->op1, RSET_GPR);
asm_fusexrefx(as, PPCI_STWBRX, src, ir->op1, rset_exclude(RSET_GPR, src));
} else {
Reg src = ra_alloc1(as, ir->op2,
(!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
rset_exclude(RSET_GPR, src), ofs);
}
}
#define asm_xstore(as, ir) asm_xstore_(as, ir, 0)
static void asm_ahuvload(ASMState *as, IRIns *ir)
{
IRType1 t = ir->t;
Reg dest = RID_NONE, type = RID_TMP, tmp = RID_TMP, idx;
RegSet allow = RSET_GPR;
int32_t ofs = AHUREF_LSX;
if (LJ_SOFTFP && (ir+1)->o == IR_HIOP) {
t.irt = IRT_NUM;
if (ra_used(ir+1)) {
type = ra_dest(as, ir+1, allow);
rset_clear(allow, type);
}
ofs = 0;
}
if (ra_used(ir)) {
lua_assert((LJ_SOFTFP ? 0 : irt_isnum(ir->t)) ||
irt_isint(ir->t) || irt_isaddr(ir->t));
if (LJ_SOFTFP || !irt_isnum(t)) ofs = 0;
dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
rset_clear(allow, dest);
}
idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
if (irt_isnum(t)) {
Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, rset_exclude(allow, idx));
asm_guardcc(as, CC_GE);
emit_ab(as, PPCI_CMPLW, type, tisnum);
if (ra_hasreg(dest)) {
if (!LJ_SOFTFP && ofs == AHUREF_LSX) {
tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR,
(idx&255)), (idx>>8)));
emit_fab(as, PPCI_LFDX, dest, (idx&255), tmp);
} else {
emit_fai(as, LJ_SOFTFP ? PPCI_LWZ : PPCI_LFD, dest, idx,
ofs+4*LJ_SOFTFP);
}
}
} else {
asm_guardcc(as, CC_NE);
emit_ai(as, PPCI_CMPWI, type, irt_toitype(t));
if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, idx, ofs+4);
}
if (ofs == AHUREF_LSX) {
emit_tab(as, PPCI_LWZX, type, (idx&255), tmp);
emit_slwi(as, tmp, (idx>>8), 3);
} else {
emit_tai(as, PPCI_LWZ, type, idx, ofs);
}
}
static void asm_ahustore(ASMState *as, IRIns *ir)
{
RegSet allow = RSET_GPR;
Reg idx, src = RID_NONE, type = RID_NONE;
int32_t ofs = AHUREF_LSX;
if (ir->r == RID_SINK)