/
lj_asm.c
2404 lines (2220 loc) · 70.5 KB
/
lj_asm.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
** IR assembler (SSA IR -> machine code).
** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
*/
#define lj_asm_c
#define LUA_CORE
#include "lj_obj.h"
#if LJ_HASJIT
#include "lj_gc.h"
#include "lj_str.h"
#include "lj_tab.h"
#include "lj_frame.h"
#if LJ_HASFFI
#include "lj_ctype.h"
#endif
#include "lj_ir.h"
#include "lj_jit.h"
#include "lj_ircall.h"
#include "lj_iropt.h"
#include "lj_mcode.h"
#include "lj_iropt.h"
#include "lj_trace.h"
#include "lj_snap.h"
#include "lj_asm.h"
#include "lj_dispatch.h"
#include "lj_vm.h"
#include "lj_target.h"
#ifdef LUA_USE_ASSERT
#include <stdio.h>
#endif
/* -- Assembler state and common macros ----------------------------------- */
/* Assembler state. */
typedef struct ASMState {
RegCost cost[RID_MAX]; /* Reference and blended allocation cost for regs. */
MCode *mcp; /* Current MCode pointer (grows down). */
MCode *mclim; /* Lower limit for MCode memory + red zone. */
#ifdef LUA_USE_ASSERT
MCode *mcp_prev; /* Red zone overflow check. */
#endif
IRIns *ir; /* Copy of pointer to IR instructions/constants. */
jit_State *J; /* JIT compiler state. */
#if LJ_TARGET_X86ORX64
x86ModRM mrm; /* Fused x86 address operand. */
#endif
RegSet freeset; /* Set of free registers. */
RegSet modset; /* Set of registers modified inside the loop. */
RegSet weakset; /* Set of weakly referenced registers. */
RegSet phiset; /* Set of PHI registers. */
uint32_t flags; /* Copy of JIT compiler flags. */
int loopinv; /* Loop branch inversion (0:no, 1:yes, 2:yes+CC_P). */
int32_t evenspill; /* Next even spill slot. */
int32_t oddspill; /* Next odd spill slot (or 0). */
IRRef curins; /* Reference of current instruction. */
IRRef stopins; /* Stop assembly before hitting this instruction. */
IRRef orignins; /* Original T->nins. */
IRRef snapref; /* Current snapshot is active after this reference. */
IRRef snaprename; /* Rename highwater mark for snapshot check. */
SnapNo snapno; /* Current snapshot number. */
SnapNo loopsnapno; /* Loop snapshot number. */
IRRef fuseref; /* Fusion limit (loopref, 0 or FUSE_DISABLED). */
IRRef sectref; /* Section base reference (loopref or 0). */
IRRef loopref; /* Reference of LOOP instruction (or 0). */
BCReg topslot; /* Number of slots for stack check (unless 0). */
int32_t gcsteps; /* Accumulated number of GC steps (per section). */
GCtrace *T; /* Trace to assemble. */
GCtrace *parent; /* Parent trace (or NULL). */
MCode *mcbot; /* Bottom of reserved MCode. */
MCode *mctop; /* Top of generated MCode. */
MCode *mcloop; /* Pointer to loop MCode (or NULL). */
MCode *invmcp; /* Points to invertible loop branch (or NULL). */
MCode *flagmcp; /* Pending opportunity to merge flag setting ins. */
MCode *realign; /* Realign loop if not NULL. */
#ifdef RID_NUM_KREF
intptr_t krefk[RID_NUM_KREF];
#endif
IRRef1 phireg[RID_MAX]; /* PHI register references. */
uint16_t parentmap[LJ_MAX_JSLOTS]; /* Parent instruction to RegSP map. */
} ASMState;
#define IR(ref) (&as->ir[(ref)])
#define ASMREF_TMP1 REF_TRUE /* Temp. register. */
#define ASMREF_TMP2 REF_FALSE /* Temp. register. */
#define ASMREF_L REF_NIL /* Stores register for L. */
/* Check for variant to invariant references. */
#define iscrossref(as, ref) ((ref) < as->sectref)
/* Inhibit memory op fusion from variant to invariant references. */
#define FUSE_DISABLED (~(IRRef)0)
#define mayfuse(as, ref) ((ref) > as->fuseref)
#define neverfuse(as) (as->fuseref == FUSE_DISABLED)
#define canfuse(as, ir) (!neverfuse(as) && !irt_isphi((ir)->t))
#define opisfusableload(o) \
((o) == IR_ALOAD || (o) == IR_HLOAD || (o) == IR_ULOAD || \
(o) == IR_FLOAD || (o) == IR_XLOAD || (o) == IR_SLOAD || (o) == IR_VLOAD)
/* Sparse limit checks using a red zone before the actual limit. */
#define MCLIM_REDZONE 64
static LJ_NORET LJ_NOINLINE void asm_mclimit(ASMState *as)
{
lj_mcode_limiterr(as->J, (size_t)(as->mctop - as->mcp + 4*MCLIM_REDZONE));
}
static LJ_AINLINE void checkmclim(ASMState *as)
{
#ifdef LUA_USE_ASSERT
if (as->mcp + MCLIM_REDZONE < as->mcp_prev) {
IRIns *ir = IR(as->curins+1);
fprintf(stderr, "RED ZONE OVERFLOW: %p IR %04d %02d %04d %04d\n", as->mcp,
as->curins+1-REF_BIAS, ir->o, ir->op1-REF_BIAS, ir->op2-REF_BIAS);
lua_assert(0);
}
#endif
if (LJ_UNLIKELY(as->mcp < as->mclim)) asm_mclimit(as);
#ifdef LUA_USE_ASSERT
as->mcp_prev = as->mcp;
#endif
}
#ifdef RID_NUM_KREF
#define ra_iskref(ref) ((ref) < RID_NUM_KREF)
#define ra_krefreg(ref) ((Reg)(RID_MIN_KREF + (Reg)(ref)))
#define ra_krefk(as, ref) (as->krefk[(ref)])
static LJ_AINLINE void ra_setkref(ASMState *as, Reg r, intptr_t k)
{
IRRef ref = (IRRef)(r - RID_MIN_KREF);
as->krefk[ref] = k;
as->cost[r] = REGCOST(ref, ref);
}
#else
#define ra_iskref(ref) 0
#define ra_krefreg(ref) RID_MIN_GPR
#define ra_krefk(as, ref) 0
#endif
/* Arch-specific field offsets. */
static const uint8_t field_ofs[IRFL__MAX+1] = {
#define FLOFS(name, ofs) (uint8_t)(ofs),
IRFLDEF(FLOFS)
#undef FLOFS
0
};
/* -- Target-specific instruction emitter --------------------------------- */
#if LJ_TARGET_X86ORX64
#include "lj_emit_x86.h"
#elif LJ_TARGET_ARM
#include "lj_emit_arm.h"
#elif LJ_TARGET_ARM64
#include "lj_emit_arm64.h"
#elif LJ_TARGET_PPC
#include "lj_emit_ppc.h"
#elif LJ_TARGET_MIPS
#include "lj_emit_mips.h"
#else
#error "Missing instruction emitter for target CPU"
#endif
/* Generic load/store of register from/to stack slot. */
#define emit_spload(as, ir, r, ofs) \
emit_loadofs(as, ir, (r), RID_SP, (ofs))
#define emit_spstore(as, ir, r, ofs) \
emit_storeofs(as, ir, (r), RID_SP, (ofs))
/* -- Register allocator debugging ---------------------------------------- */
/* #define LUAJIT_DEBUG_RA */
#ifdef LUAJIT_DEBUG_RA
#include <stdio.h>
#include <stdarg.h>
#define RIDNAME(name) #name,
static const char *const ra_regname[] = {
GPRDEF(RIDNAME)
FPRDEF(RIDNAME)
VRIDDEF(RIDNAME)
NULL
};
#undef RIDNAME
static char ra_dbg_buf[65536];
static char *ra_dbg_p;
static char *ra_dbg_merge;
static MCode *ra_dbg_mcp;
static void ra_dstart(void)
{
ra_dbg_p = ra_dbg_buf;
ra_dbg_merge = NULL;
ra_dbg_mcp = NULL;
}
static void ra_dflush(void)
{
fwrite(ra_dbg_buf, 1, (size_t)(ra_dbg_p-ra_dbg_buf), stdout);
ra_dstart();
}
static void ra_dprintf(ASMState *as, const char *fmt, ...)
{
char *p;
va_list argp;
va_start(argp, fmt);
p = ra_dbg_mcp == as->mcp ? ra_dbg_merge : ra_dbg_p;
ra_dbg_mcp = NULL;
p += sprintf(p, "%08x \e[36m%04d ", (uintptr_t)as->mcp, as->curins-REF_BIAS);
for (;;) {
const char *e = strchr(fmt, '$');
if (e == NULL) break;
memcpy(p, fmt, (size_t)(e-fmt));
p += e-fmt;
if (e[1] == 'r') {
Reg r = va_arg(argp, Reg) & RID_MASK;
if (r <= RID_MAX) {
const char *q;
for (q = ra_regname[r]; *q; q++)
*p++ = *q >= 'A' && *q <= 'Z' ? *q + 0x20 : *q;
} else {
*p++ = '?';
lua_assert(0);
}
} else if (e[1] == 'f' || e[1] == 'i') {
IRRef ref;
if (e[1] == 'f')
ref = va_arg(argp, IRRef);
else
ref = va_arg(argp, IRIns *) - as->ir;
if (ref >= REF_BIAS)
p += sprintf(p, "%04d", ref - REF_BIAS);
else
p += sprintf(p, "K%03d", REF_BIAS - ref);
} else if (e[1] == 's') {
uint32_t slot = va_arg(argp, uint32_t);
p += sprintf(p, "[sp+0x%x]", sps_scale(slot));
} else if (e[1] == 'x') {
p += sprintf(p, "%08x", va_arg(argp, int32_t));
} else {
lua_assert(0);
}
fmt = e+2;
}
va_end(argp);
while (*fmt)
*p++ = *fmt++;
*p++ = '\e'; *p++ = '['; *p++ = 'm'; *p++ = '\n';
if (p > ra_dbg_buf+sizeof(ra_dbg_buf)-256) {
fwrite(ra_dbg_buf, 1, (size_t)(p-ra_dbg_buf), stdout);
p = ra_dbg_buf;
}
ra_dbg_p = p;
}
#define RA_DBG_START() ra_dstart()
#define RA_DBG_FLUSH() ra_dflush()
#define RA_DBG_REF() \
do { char *_p = ra_dbg_p; ra_dprintf(as, ""); \
ra_dbg_merge = _p; ra_dbg_mcp = as->mcp; } while (0)
#define RA_DBGX(x) ra_dprintf x
#else
#define RA_DBG_START() ((void)0)
#define RA_DBG_FLUSH() ((void)0)
#define RA_DBG_REF() ((void)0)
#define RA_DBGX(x) ((void)0)
#endif
/* -- Register allocator -------------------------------------------------- */
#define ra_free(as, r) rset_set(as->freeset, (r))
#define ra_modified(as, r) rset_set(as->modset, (r))
#define ra_weak(as, r) rset_set(as->weakset, (r))
#define ra_noweak(as, r) rset_clear(as->weakset, (r))
#define ra_used(ir) (ra_hasreg((ir)->r) || ra_hasspill((ir)->s))
/* Setup register allocator. */
static void ra_setup(ASMState *as)
{
Reg r;
/* Initially all regs (except the stack pointer) are free for use. */
as->freeset = RSET_INIT;
as->modset = RSET_EMPTY;
as->weakset = RSET_EMPTY;
as->phiset = RSET_EMPTY;
memset(as->phireg, 0, sizeof(as->phireg));
for (r = RID_MIN_GPR; r < RID_MAX; r++)
as->cost[r] = REGCOST(~0u, 0u);
}
/* Rematerialize constants. */
static Reg ra_rematk(ASMState *as, IRRef ref)
{
IRIns *ir;
Reg r;
if (ra_iskref(ref)) {
r = ra_krefreg(ref);
lua_assert(!rset_test(as->freeset, r));
ra_free(as, r);
ra_modified(as, r);
#if LJ_64
emit_loadu64(as, r, ra_krefk(as, ref));
#else
emit_loadi(as, r, ra_krefk(as, ref));
#endif
return r;
}
ir = IR(ref);
r = ir->r;
lua_assert(ra_hasreg(r) && !ra_hasspill(ir->s));
ra_free(as, r);
ra_modified(as, r);
ir->r = RID_INIT; /* Do not keep any hint. */
RA_DBGX((as, "remat $i $r", ir, r));
#if !LJ_SOFTFP
if (ir->o == IR_KNUM) {
emit_loadk64(as, r, ir);
} else
#endif
if (emit_canremat(REF_BASE) && ir->o == IR_BASE) {
ra_sethint(ir->r, RID_BASE); /* Restore BASE register hint. */
emit_getgl(as, r, jit_base);
} else if (emit_canremat(ASMREF_L) && ir->o == IR_KPRI) {
lua_assert(irt_isnil(ir->t)); /* REF_NIL stores ASMREF_L register. */
emit_getgl(as, r, cur_L);
#if LJ_64
} else if (ir->o == IR_KINT64) {
emit_loadu64(as, r, ir_kint64(ir)->u64);
#if LJ_GC64
} else if (ir->o == IR_KGC) {
emit_loadu64(as, r, (uintptr_t)ir_kgc(ir));
} else if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
emit_loadu64(as, r, (uintptr_t)ir_kptr(ir));
#endif
#endif
} else {
lua_assert(ir->o == IR_KINT || ir->o == IR_KGC ||
ir->o == IR_KPTR || ir->o == IR_KKPTR || ir->o == IR_KNULL);
emit_loadi(as, r, ir->i);
}
return r;
}
/* Force a spill. Allocate a new spill slot if needed. */
static int32_t ra_spill(ASMState *as, IRIns *ir)
{
int32_t slot = ir->s;
lua_assert(ir >= as->ir + REF_TRUE);
if (!ra_hasspill(slot)) {
if (irt_is64(ir->t)) {
slot = as->evenspill;
as->evenspill += 2;
} else if (as->oddspill) {
slot = as->oddspill;
as->oddspill = 0;
} else {
slot = as->evenspill;
as->oddspill = slot+1;
as->evenspill += 2;
}
if (as->evenspill > 256)
lj_trace_err(as->J, LJ_TRERR_SPILLOV);
ir->s = (uint8_t)slot;
}
return sps_scale(slot);
}
/* Release the temporarily allocated register in ASMREF_TMP1/ASMREF_TMP2. */
static Reg ra_releasetmp(ASMState *as, IRRef ref)
{
IRIns *ir = IR(ref);
Reg r = ir->r;
lua_assert(ra_hasreg(r) && !ra_hasspill(ir->s));
ra_free(as, r);
ra_modified(as, r);
ir->r = RID_INIT;
return r;
}
/* Restore a register (marked as free). Rematerialize or force a spill. */
static Reg ra_restore(ASMState *as, IRRef ref)
{
if (emit_canremat(ref)) {
return ra_rematk(as, ref);
} else {
IRIns *ir = IR(ref);
int32_t ofs = ra_spill(as, ir); /* Force a spill slot. */
Reg r = ir->r;
lua_assert(ra_hasreg(r));
ra_sethint(ir->r, r); /* Keep hint. */
ra_free(as, r);
if (!rset_test(as->weakset, r)) { /* Only restore non-weak references. */
ra_modified(as, r);
RA_DBGX((as, "restore $i $r", ir, r));
emit_spload(as, ir, r, ofs);
}
return r;
}
}
/* Save a register to a spill slot. */
static void ra_save(ASMState *as, IRIns *ir, Reg r)
{
RA_DBGX((as, "save $i $r", ir, r));
emit_spstore(as, ir, r, sps_scale(ir->s));
}
#define MINCOST(name) \
if (rset_test(RSET_ALL, RID_##name) && \
LJ_LIKELY(allow&RID2RSET(RID_##name)) && as->cost[RID_##name] < cost) \
cost = as->cost[RID_##name];
/* Evict the register with the lowest cost, forcing a restore. */
static Reg ra_evict(ASMState *as, RegSet allow)
{
IRRef ref;
RegCost cost = ~(RegCost)0;
lua_assert(allow != RSET_EMPTY);
if (RID_NUM_FPR == 0 || allow < RID2RSET(RID_MAX_GPR)) {
GPRDEF(MINCOST)
} else {
FPRDEF(MINCOST)
}
ref = regcost_ref(cost);
lua_assert(ra_iskref(ref) || (ref >= as->T->nk && ref < as->T->nins));
/* Preferably pick any weak ref instead of a non-weak, non-const ref. */
if (!irref_isk(ref) && (as->weakset & allow)) {
IRIns *ir = IR(ref);
if (!rset_test(as->weakset, ir->r))
ref = regcost_ref(as->cost[rset_pickbot((as->weakset & allow))]);
}
return ra_restore(as, ref);
}
/* Pick any register (marked as free). Evict on-demand. */
static Reg ra_pick(ASMState *as, RegSet allow)
{
RegSet pick = as->freeset & allow;
if (!pick)
return ra_evict(as, allow);
else
return rset_picktop(pick);
}
/* Get a scratch register (marked as free). */
static Reg ra_scratch(ASMState *as, RegSet allow)
{
Reg r = ra_pick(as, allow);
ra_modified(as, r);
RA_DBGX((as, "scratch $r", r));
return r;
}
/* Evict all registers from a set (if not free). */
static void ra_evictset(ASMState *as, RegSet drop)
{
RegSet work;
as->modset |= drop;
#if !LJ_SOFTFP
work = (drop & ~as->freeset) & RSET_FPR;
while (work) {
Reg r = rset_pickbot(work);
ra_restore(as, regcost_ref(as->cost[r]));
rset_clear(work, r);
checkmclim(as);
}
#endif
work = (drop & ~as->freeset);
while (work) {
Reg r = rset_pickbot(work);
ra_restore(as, regcost_ref(as->cost[r]));
rset_clear(work, r);
checkmclim(as);
}
}
/* Evict (rematerialize) all registers allocated to constants. */
static void ra_evictk(ASMState *as)
{
RegSet work;
#if !LJ_SOFTFP
work = ~as->freeset & RSET_FPR;
while (work) {
Reg r = rset_pickbot(work);
IRRef ref = regcost_ref(as->cost[r]);
if (emit_canremat(ref) && irref_isk(ref)) {
ra_rematk(as, ref);
checkmclim(as);
}
rset_clear(work, r);
}
#endif
work = ~as->freeset & RSET_GPR;
while (work) {
Reg r = rset_pickbot(work);
IRRef ref = regcost_ref(as->cost[r]);
if (emit_canremat(ref) && irref_isk(ref)) {
ra_rematk(as, ref);
checkmclim(as);
}
rset_clear(work, r);
}
}
#ifdef RID_NUM_KREF
/* Allocate a register for a constant. */
static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow)
{
/* First try to find a register which already holds the same constant. */
RegSet pick, work = ~as->freeset & RSET_GPR;
Reg r;
while (work) {
IRRef ref;
r = rset_pickbot(work);
ref = regcost_ref(as->cost[r]);
#if LJ_64
if (ref < ASMREF_L) {
if (ra_iskref(ref)) {
if (k == ra_krefk(as, ref))
return r;
} else {
IRIns *ir = IR(ref);
if ((ir->o == IR_KINT64 && k == (int64_t)ir_kint64(ir)->u64) ||
#if LJ_GC64
(ir->o == IR_KINT && k == ir->i) ||
(ir->o == IR_KGC && k == (intptr_t)ir_kgc(ir)) ||
((ir->o == IR_KPTR || ir->o == IR_KKPTR) &&
k == (intptr_t)ir_kptr(ir))
#else
(ir->o != IR_KINT64 && k == ir->i)
#endif
)
return r;
}
}
#else
if (ref < ASMREF_L &&
k == (ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i))
return r;
#endif
rset_clear(work, r);
}
pick = as->freeset & allow;
if (pick) {
/* Constants should preferably get unmodified registers. */
if ((pick & ~as->modset))
pick &= ~as->modset;
r = rset_pickbot(pick); /* Reduce conflicts with inverse allocation. */
} else {
r = ra_evict(as, allow);
}
RA_DBGX((as, "allock $x $r", k, r));
ra_setkref(as, r, k);
rset_clear(as->freeset, r);
ra_noweak(as, r);
return r;
}
/* Allocate a specific register for a constant. */
static void ra_allockreg(ASMState *as, intptr_t k, Reg r)
{
Reg kr = ra_allock(as, k, RID2RSET(r));
if (kr != r) {
IRIns irdummy;
irdummy.t.irt = IRT_INT;
ra_scratch(as, RID2RSET(r));
emit_movrr(as, &irdummy, r, kr);
}
}
#else
#define ra_allockreg(as, k, r) emit_loadi(as, (r), (k))
#endif
/* Allocate a register for ref from the allowed set of registers.
** Note: this function assumes the ref does NOT have a register yet!
** Picks an optimal register, sets the cost and marks the register as non-free.
*/
static Reg ra_allocref(ASMState *as, IRRef ref, RegSet allow)
{
IRIns *ir = IR(ref);
RegSet pick = as->freeset & allow;
Reg r;
lua_assert(ra_noreg(ir->r));
if (pick) {
/* First check register hint from propagation or PHI. */
if (ra_hashint(ir->r)) {
r = ra_gethint(ir->r);
if (rset_test(pick, r)) /* Use hint register if possible. */
goto found;
/* Rematerialization is cheaper than missing a hint. */
if (rset_test(allow, r) && emit_canremat(regcost_ref(as->cost[r]))) {
ra_rematk(as, regcost_ref(as->cost[r]));
goto found;
}
RA_DBGX((as, "hintmiss $f $r", ref, r));
}
/* Invariants should preferably get unmodified registers. */
if (ref < as->loopref && !irt_isphi(ir->t)) {
if ((pick & ~as->modset))
pick &= ~as->modset;
r = rset_pickbot(pick); /* Reduce conflicts with inverse allocation. */
} else {
/* We've got plenty of regs, so get callee-save regs if possible. */
if (RID_NUM_GPR > 8 && (pick & ~RSET_SCRATCH))
pick &= ~RSET_SCRATCH;
r = rset_picktop(pick);
}
} else {
r = ra_evict(as, allow);
}
found:
RA_DBGX((as, "alloc $f $r", ref, r));
ir->r = (uint8_t)r;
rset_clear(as->freeset, r);
ra_noweak(as, r);
as->cost[r] = REGCOST_REF_T(ref, irt_t(ir->t));
return r;
}
/* Allocate a register on-demand. */
static Reg ra_alloc1(ASMState *as, IRRef ref, RegSet allow)
{
Reg r = IR(ref)->r;
/* Note: allow is ignored if the register is already allocated. */
if (ra_noreg(r)) r = ra_allocref(as, ref, allow);
ra_noweak(as, r);
return r;
}
/* Add a register rename to the IR. */
static void ra_addrename(ASMState *as, Reg down, IRRef ref, SnapNo snapno)
{
IRRef ren;
lj_ir_set(as->J, IRT(IR_RENAME, IRT_NIL), ref, snapno);
ren = tref_ref(lj_ir_emit(as->J));
as->J->cur.ir[ren].r = (uint8_t)down;
as->J->cur.ir[ren].s = SPS_NONE;
}
/* Rename register allocation and emit move. */
static void ra_rename(ASMState *as, Reg down, Reg up)
{
IRRef ref = regcost_ref(as->cost[up] = as->cost[down]);
IRIns *ir = IR(ref);
ir->r = (uint8_t)up;
as->cost[down] = 0;
lua_assert((down < RID_MAX_GPR) == (up < RID_MAX_GPR));
lua_assert(!rset_test(as->freeset, down) && rset_test(as->freeset, up));
ra_free(as, down); /* 'down' is free ... */
ra_modified(as, down);
rset_clear(as->freeset, up); /* ... and 'up' is now allocated. */
ra_noweak(as, up);
RA_DBGX((as, "rename $f $r $r", regcost_ref(as->cost[up]), down, up));
emit_movrr(as, ir, down, up); /* Backwards codegen needs inverse move. */
if (!ra_hasspill(IR(ref)->s)) { /* Add the rename to the IR. */
ra_addrename(as, down, ref, as->snapno);
}
}
/* Pick a destination register (marked as free).
** Caveat: allow is ignored if there's already a destination register.
** Use ra_destreg() to get a specific register.
*/
static Reg ra_dest(ASMState *as, IRIns *ir, RegSet allow)
{
Reg dest = ir->r;
if (ra_hasreg(dest)) {
ra_free(as, dest);
ra_modified(as, dest);
} else {
if (ra_hashint(dest) && rset_test((as->freeset&allow), ra_gethint(dest))) {
dest = ra_gethint(dest);
ra_modified(as, dest);
RA_DBGX((as, "dest $r", dest));
} else {
dest = ra_scratch(as, allow);
}
ir->r = dest;
}
if (LJ_UNLIKELY(ra_hasspill(ir->s))) ra_save(as, ir, dest);
return dest;
}
/* Force a specific destination register (marked as free). */
static void ra_destreg(ASMState *as, IRIns *ir, Reg r)
{
Reg dest = ra_dest(as, ir, RID2RSET(r));
if (dest != r) {
lua_assert(rset_test(as->freeset, r));
ra_modified(as, r);
emit_movrr(as, ir, dest, r);
}
}
#if LJ_TARGET_X86ORX64
/* Propagate dest register to left reference. Emit moves as needed.
** This is a required fixup step for all 2-operand machine instructions.
*/
static void ra_left(ASMState *as, Reg dest, IRRef lref)
{
IRIns *ir = IR(lref);
Reg left = ir->r;
if (ra_noreg(left)) {
if (irref_isk(lref)) {
if (ir->o == IR_KNUM) {
/* FP remat needs a load except for +0. Still better than eviction. */
if (tvispzero(ir_knum(ir)) || !(as->freeset & RSET_FPR)) {
emit_loadk64(as, dest, ir);
return;
}
#if LJ_64
} else if (ir->o == IR_KINT64) {
emit_loadk64(as, dest, ir);
return;
#if LJ_GC64
} else if (ir->o == IR_KGC || ir->o == IR_KPTR || ir->o == IR_KKPTR) {
emit_loadk64(as, dest, ir);
return;
#endif
#endif
} else if (ir->o != IR_KPRI) {
lua_assert(ir->o == IR_KINT || ir->o == IR_KGC ||
ir->o == IR_KPTR || ir->o == IR_KKPTR || ir->o == IR_KNULL);
emit_loadi(as, dest, ir->i);
return;
}
}
if (!ra_hashint(left) && !iscrossref(as, lref))
ra_sethint(ir->r, dest); /* Propagate register hint. */
left = ra_allocref(as, lref, dest < RID_MAX_GPR ? RSET_GPR : RSET_FPR);
}
ra_noweak(as, left);
/* Move needed for true 3-operand instruction: y=a+b ==> y=a; y+=b. */
if (dest != left) {
/* Use register renaming if dest is the PHI reg. */
if (irt_isphi(ir->t) && as->phireg[dest] == lref) {
ra_modified(as, left);
ra_rename(as, left, dest);
} else {
emit_movrr(as, ir, dest, left);
}
}
}
#else
/* Similar to ra_left, except we override any hints. */
static void ra_leftov(ASMState *as, Reg dest, IRRef lref)
{
IRIns *ir = IR(lref);
Reg left = ir->r;
if (ra_noreg(left)) {
ra_sethint(ir->r, dest); /* Propagate register hint. */
left = ra_allocref(as, lref,
(LJ_SOFTFP || dest < RID_MAX_GPR) ? RSET_GPR : RSET_FPR);
}
ra_noweak(as, left);
if (dest != left) {
/* Use register renaming if dest is the PHI reg. */
if (irt_isphi(ir->t) && as->phireg[dest] == lref) {
ra_modified(as, left);
ra_rename(as, left, dest);
} else {
emit_movrr(as, ir, dest, left);
}
}
}
#endif
#if !LJ_64
/* Force a RID_RETLO/RID_RETHI destination register pair (marked as free). */
static void ra_destpair(ASMState *as, IRIns *ir)
{
Reg destlo = ir->r, desthi = (ir+1)->r;
/* First spill unrelated refs blocking the destination registers. */
if (!rset_test(as->freeset, RID_RETLO) &&
destlo != RID_RETLO && desthi != RID_RETLO)
ra_restore(as, regcost_ref(as->cost[RID_RETLO]));
if (!rset_test(as->freeset, RID_RETHI) &&
destlo != RID_RETHI && desthi != RID_RETHI)
ra_restore(as, regcost_ref(as->cost[RID_RETHI]));
/* Next free the destination registers (if any). */
if (ra_hasreg(destlo)) {
ra_free(as, destlo);
ra_modified(as, destlo);
} else {
destlo = RID_RETLO;
}
if (ra_hasreg(desthi)) {
ra_free(as, desthi);
ra_modified(as, desthi);
} else {
desthi = RID_RETHI;
}
/* Check for conflicts and shuffle the registers as needed. */
if (destlo == RID_RETHI) {
if (desthi == RID_RETLO) {
#if LJ_TARGET_X86
*--as->mcp = XI_XCHGa + RID_RETHI;
#else
emit_movrr(as, ir, RID_RETHI, RID_TMP);
emit_movrr(as, ir, RID_RETLO, RID_RETHI);
emit_movrr(as, ir, RID_TMP, RID_RETLO);
#endif
} else {
emit_movrr(as, ir, RID_RETHI, RID_RETLO);
if (desthi != RID_RETHI) emit_movrr(as, ir, desthi, RID_RETHI);
}
} else if (desthi == RID_RETLO) {
emit_movrr(as, ir, RID_RETLO, RID_RETHI);
if (destlo != RID_RETLO) emit_movrr(as, ir, destlo, RID_RETLO);
} else {
if (desthi != RID_RETHI) emit_movrr(as, ir, desthi, RID_RETHI);
if (destlo != RID_RETLO) emit_movrr(as, ir, destlo, RID_RETLO);
}
/* Restore spill slots (if any). */
if (ra_hasspill((ir+1)->s)) ra_save(as, ir+1, RID_RETHI);
if (ra_hasspill(ir->s)) ra_save(as, ir, RID_RETLO);
}
#endif
/* -- Snapshot handling --------- ----------------------------------------- */
/* Can we rematerialize a KNUM instead of forcing a spill? */
static int asm_snap_canremat(ASMState *as)
{
Reg r;
for (r = RID_MIN_FPR; r < RID_MAX_FPR; r++)
if (irref_isk(regcost_ref(as->cost[r])))
return 1;
return 0;
}
/* Check whether a sunk store corresponds to an allocation. */
static int asm_sunk_store(ASMState *as, IRIns *ira, IRIns *irs)
{
if (irs->s == 255) {
if (irs->o == IR_ASTORE || irs->o == IR_HSTORE ||
irs->o == IR_FSTORE || irs->o == IR_XSTORE) {
IRIns *irk = IR(irs->op1);
if (irk->o == IR_AREF || irk->o == IR_HREFK)
irk = IR(irk->op1);
return (IR(irk->op1) == ira);
}
return 0;
} else {
return (ira + irs->s == irs); /* Quick check. */
}
}
/* Allocate register or spill slot for a ref that escapes to a snapshot. */
static void asm_snap_alloc1(ASMState *as, IRRef ref)
{
IRIns *ir = IR(ref);
if (!irref_isk(ref) && (!(ra_used(ir) || ir->r == RID_SUNK))) {
if (ir->r == RID_SINK) {
ir->r = RID_SUNK;
#if LJ_HASFFI
if (ir->o == IR_CNEWI) { /* Allocate CNEWI value. */
asm_snap_alloc1(as, ir->op2);
if (LJ_32 && (ir+1)->o == IR_HIOP)
asm_snap_alloc1(as, (ir+1)->op2);
} else
#endif
{ /* Allocate stored values for TNEW, TDUP and CNEW. */
IRIns *irs;
lua_assert(ir->o == IR_TNEW || ir->o == IR_TDUP || ir->o == IR_CNEW);
for (irs = IR(as->snapref-1); irs > ir; irs--)
if (irs->r == RID_SINK && asm_sunk_store(as, ir, irs)) {
lua_assert(irs->o == IR_ASTORE || irs->o == IR_HSTORE ||
irs->o == IR_FSTORE || irs->o == IR_XSTORE);
asm_snap_alloc1(as, irs->op2);
if (LJ_32 && (irs+1)->o == IR_HIOP)
asm_snap_alloc1(as, (irs+1)->op2);
}
}
} else {
RegSet allow;
if (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT) {
IRIns *irc;
for (irc = IR(as->curins); irc > ir; irc--)
if ((irc->op1 == ref || irc->op2 == ref) &&
!(irc->r == RID_SINK || irc->r == RID_SUNK))
goto nosink; /* Don't sink conversion if result is used. */
asm_snap_alloc1(as, ir->op1);
return;
}
nosink:
allow = (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR;
if ((as->freeset & allow) ||
(allow == RSET_FPR && asm_snap_canremat(as))) {
/* Get a weak register if we have a free one or can rematerialize. */
Reg r = ra_allocref(as, ref, allow); /* Allocate a register. */
if (!irt_isphi(ir->t))
ra_weak(as, r); /* But mark it as weakly referenced. */
checkmclim(as);
RA_DBGX((as, "snapreg $f $r", ref, ir->r));
} else {
ra_spill(as, ir); /* Otherwise force a spill slot. */
RA_DBGX((as, "snapspill $f $s", ref, ir->s));
}
}
}
}
/* Allocate refs escaping to a snapshot. */
static void asm_snap_alloc(ASMState *as)
{
SnapShot *snap = &as->T->snap[as->snapno];
SnapEntry *map = &as->T->snapmap[snap->mapofs];
MSize n, nent = snap->nent;
for (n = 0; n < nent; n++) {
SnapEntry sn = map[n];
IRRef ref = snap_ref(sn);
if (!irref_isk(ref)) {
asm_snap_alloc1(as, ref);
if (LJ_SOFTFP && (sn & SNAP_SOFTFPNUM)) {
lua_assert(irt_type(IR(ref+1)->t) == IRT_SOFTFP);
asm_snap_alloc1(as, ref+1);
}
}
}
}
/* All guards for a snapshot use the same exitno. This is currently the
** same as the snapshot number. Since the exact origin of the exit cannot
** be determined, all guards for the same snapshot must exit with the same
** RegSP mapping.
** A renamed ref which has been used in a prior guard for the same snapshot
** would cause an inconsistency. The easy way out is to force a spill slot.
*/
static int asm_snap_checkrename(ASMState *as, IRRef ren)
{
SnapShot *snap = &as->T->snap[as->snapno];
SnapEntry *map = &as->T->snapmap[snap->mapofs];
MSize n, nent = snap->nent;
for (n = 0; n < nent; n++) {
SnapEntry sn = map[n];
IRRef ref = snap_ref(sn);
if (ref == ren || (LJ_SOFTFP && (sn & SNAP_SOFTFPNUM) && ++ref == ren)) {
IRIns *ir = IR(ref);
ra_spill(as, ir); /* Register renamed, so force a spill slot. */
RA_DBGX((as, "snaprensp $f $s", ref, ir->s));
return 1; /* Found. */
}
}
return 0; /* Not found. */
}
/* Prepare snapshot for next guard instruction. */
static void asm_snap_prep(ASMState *as)
{
if (as->curins < as->snapref) {
do {
if (as->snapno == 0) return; /* Called by sunk stores before snap #0. */
as->snapno--;
as->snapref = as->T->snap[as->snapno].ref;
} while (as->curins < as->snapref);
asm_snap_alloc(as);
as->snaprename = as->T->nins;
} else {
/* Process any renames above the highwater mark. */
for (; as->snaprename < as->T->nins; as->snaprename++) {
IRIns *ir = &as->T->ir[as->snaprename];
if (asm_snap_checkrename(as, ir->op1))
ir->op2 = REF_BIAS-1; /* Kill rename. */
}
}
}
/* -- Miscellaneous helpers ----------------------------------------------- */
/* Calculate stack adjustment. */
static int32_t asm_stack_adjust(ASMState *as)
{
if (as->evenspill <= SPS_FIXED)