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top_map.mrp
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top_map.mrp
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Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'top'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o top_map.ncd top.ngd top.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Sat Apr 04 22:06:15 2015
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 480 out of 18,224 2%
Number used as Flip Flops: 473
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 1,991 out of 9,112 21%
Number used as logic: 1,982 out of 9,112 21%
Number using O6 output only: 1,597
Number using O5 output only: 126
Number using O5 and O6: 259
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 9
Number with same-slice register load: 3
Number with same-slice carry load: 6
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 724 out of 2,278 31%
Number of MUXCYs used: 368 out of 4,556 8%
Number of LUT Flip Flop pairs used: 2,007
Number with an unused Flip Flop: 1,537 out of 2,007 76%
Number with an unused LUT: 16 out of 2,007 1%
Number of fully used LUT-FF pairs: 454 out of 2,007 22%
Number of unique control sets: 65
Number of slice register sites lost
to control set restrictions: 311 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 36 out of 232 15%
Number of LOCed IOBs: 36 out of 36 100%
IOB Latches: 7
Specific Feature Utilization:
Number of RAMB16BWERs: 16 out of 32 50%
Number of RAMB8BWERs: 21 out of 64 32%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 7 out of 248 2%
Number used as OLOGIC2s: 7
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.43
Peak Memory Usage: 463 MB
Total REAL time to MAP completion: 56 secs
Total CPU time to MAP completion: 54 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net _i000003/pulse is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net seven_seg/_n0050<0> is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network sw<7> has no load.
INFO:LIT:395 - The above info message is repeated 7 more times for the following
(max. 5 shown):
sw<6>,
sw<5>,
sw<4>,
sw<3>,
sw<2>
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
32 block(s) optimized away
1 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal "bg/N0" is sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND bg/XST_GND
VCC bg/XST_VCC
GND hero_down/XST_GND
VCC hero_down/XST_VCC
GND hero_left/XST_GND
VCC hero_left/XST_VCC
GND hero_main_0/XST_GND
VCC hero_main_0/XST_VCC
GND hero_main_1/XST_GND
VCC hero_main_1/XST_VCC
GND hero_right/XST_GND
VCC hero_right/XST_VCC
GND hero_up/XST_GND
VCC hero_up/XST_VCC
GND monster_down_0/XST_GND
VCC monster_down_0/XST_VCC
GND monster_down_1/XST_GND
VCC monster_down_1/XST_VCC
GND monster_left_0/XST_GND
VCC monster_left_0/XST_VCC
GND monster_left_1/XST_GND
VCC monster_left_1/XST_VCC
GND monster_right_0/XST_GND
VCC monster_right_0/XST_VCC
GND monster_right_1/XST_GND
VCC monster_right_1/XST_VCC
GND monster_up_0/XST_GND
VCC monster_up_0/XST_VCC
GND monster_up_1/XST_GND
VCC monster_up_1/XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| Led<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Led<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| an<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| an<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| an<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| an<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| btn<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| btn<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| btn<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| btn<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| clk_100MHz | IOB | INPUT | LVCMOS33 | | | | | | |
| hsync | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| power | IOB | INPUT | LVCMOS33 | | | | | | |
| segment<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OLATCH | | |
| segment<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_B<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_B<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_G<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_G<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_G<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_R<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_R<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_R<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vsync | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.