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yongbokyongbok
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target-mips: implement SAARI/SAAR registers
SAARI (Special Address Access Register Index) provides an index into the SAAR register to indicate whether the ITU or other block is being accessed. SAAR (Special Address Access Register) stores the base address where the ITU will be located, as well as the block size. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
1 parent a7f5415 commit c934049

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5 files changed

+103
-2
lines changed

5 files changed

+103
-2
lines changed

‎target-mips/cpu.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -368,6 +368,12 @@ struct CPUMIPSState {
368368
uint32_t CP0_BadInstr;
369369
uint32_t CP0_BadInstrP;
370370
int32_t CP0_Count;
371+
#define CP0SAARI_IDX 0
372+
uint32_t CP0_SAARI;
373+
#define CP0SAAR_BASE 12
374+
#define CP0SAAR_SIZE 1
375+
#define CP0SAAR_EN 0
376+
uint64_t CP0_SAAR[2];
371377
target_ulong CP0_EntryHi;
372378
#define CP0EnHi_EHINV 10
373379
target_ulong CP0_EntryHi_ASID_mask;
@@ -634,6 +640,7 @@ struct CPUMIPSState {
634640
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
635641
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
636642
int insn_flags; /* Supported instruction set */
643+
int saarp;
637644

638645
CPU_COMMON
639646

‎target-mips/helper.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env)
7070
DEF_HELPER_1(mfc0_tcschefback, tl, env)
7171
DEF_HELPER_1(mftc0_tcschefback, tl, env)
7272
DEF_HELPER_1(mfc0_count, tl, env)
73+
DEF_HELPER_1(mfc0_saar, tl, env)
74+
DEF_HELPER_1(mfhc0_saar, tl, env)
7375
DEF_HELPER_1(mftc0_entryhi, tl, env)
7476
DEF_HELPER_1(mftc0_status, tl, env)
7577
DEF_HELPER_1(mftc0_cause, tl, env)
@@ -133,6 +135,8 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
133135
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
134136
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
135137
DEF_HELPER_2(mtc0_count, void, env, tl)
138+
DEF_HELPER_2(mtc0_saar, void, env, tl)
139+
DEF_HELPER_2(mthc0_saar, void, env, tl)
136140
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
137141
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
138142
DEF_HELPER_2(mtc0_compare, void, env, tl)

‎target-mips/op_helper.c

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -852,6 +852,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env)
852852
return (int32_t)cpu_mips_get_count(env);
853853
}
854854

855+
target_ulong helper_mfc0_saar(CPUMIPSState *env)
856+
{
857+
if ((env->CP0_SAARI & 0x3f) < 2) {
858+
return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
859+
}
860+
return 0;
861+
}
862+
863+
target_ulong helper_mfhc0_saar(CPUMIPSState *env)
864+
{
865+
if ((env->CP0_SAARI & 0x3f) < 2) {
866+
return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
867+
}
868+
return 0;
869+
}
870+
855871
target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
856872
{
857873
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -1458,6 +1474,24 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
14581474
cpu_mips_store_count(env, arg1);
14591475
}
14601476

1477+
void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1478+
{
1479+
uint32_t target = env->CP0_SAARI & 0x3f;
1480+
if (target < 2) {
1481+
env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1482+
}
1483+
}
1484+
1485+
void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1486+
{
1487+
uint32_t target = env->CP0_SAARI & 0x3f;
1488+
if (target < 2) {
1489+
env->CP0_SAAR[target] =
1490+
(((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1491+
(env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1492+
}
1493+
}
1494+
14611495
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
14621496
{
14631497
target_ulong old, val, mask;

‎target-mips/translate.c

Lines changed: 57 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,6 +1438,7 @@ typedef struct DisasContext {
14381438
bool pw;
14391439
bool nan2008;
14401440
bool abs2008;
1441+
bool saar;
14411442
} DisasContext;
14421443

14431444
enum {
@@ -4845,6 +4846,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
48454846
goto cp0_unimplemented;
48464847
}
48474848
break;
4849+
case 9:
4850+
switch (sel) {
4851+
case 7:
4852+
CP0_CHECK(ctx->saar);
4853+
gen_helper_mfhc0_saar(arg, cpu_env);
4854+
rn = "SAAR";
4855+
break;
4856+
default:
4857+
goto cp0_unimplemented;
4858+
}
4859+
break;
48484860
case 17:
48494861
switch (sel) {
48504862
case 0:
@@ -4917,6 +4929,17 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
49174929
goto cp0_unimplemented;
49184930
}
49194931
break;
4932+
case 9:
4933+
switch (sel) {
4934+
case 7:
4935+
CP0_CHECK(ctx->saar);
4936+
gen_helper_mthc0_saar(cpu_env, arg);
4937+
rn = "SAAR";
4938+
break;
4939+
default:
4940+
goto cp0_unimplemented;
4941+
}
4942+
break;
49204943
case 17:
49214944
switch (sel) {
49224945
case 0:
@@ -5277,6 +5300,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
52775300
ctx->bstate = BS_STOP;
52785301
rn = "Count";
52795302
break;
5303+
case 6:
5304+
CP0_CHECK(ctx->saar);
5305+
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
5306+
rn = "SAARI";
5307+
break;
5308+
case 7:
5309+
CP0_CHECK(ctx->saar);
5310+
gen_helper_mfc0_saar(arg, cpu_env);
5311+
rn = "SAAR";
5312+
break;
52805313
/* 6,7 are implementation dependent */
52815314
default:
52825315
goto cp0_unimplemented;
@@ -5940,7 +5973,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
59405973
gen_helper_mtc0_count(cpu_env, arg);
59415974
rn = "Count";
59425975
break;
5943-
/* 6,7 are implementation dependent */
5976+
case 6:
5977+
CP0_CHECK(ctx->saar);
5978+
tcg_gen_andi_tl(arg, arg, 0x3f);
5979+
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SAARI));
5980+
rn = "SAARI";
5981+
break;
5982+
case 7:
5983+
CP0_CHECK(ctx->saar);
5984+
gen_helper_mtc0_saar(cpu_env, arg);
5985+
rn = "SAAR";
5986+
break;
59445987
default:
59455988
goto cp0_unimplemented;
59465989
}
@@ -7280,7 +7323,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
72807323
gen_helper_mtc0_count(cpu_env, arg);
72817324
rn = "Count";
72827325
break;
7283-
/* 6,7 are implementation dependent */
7326+
case 6:
7327+
CP0_CHECK(ctx->saar);
7328+
tcg_gen_andi_tl(arg, arg, 0x3f);
7329+
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SAARI));
7330+
rn = "SAARI";
7331+
break;
7332+
case 7:
7333+
CP0_CHECK(ctx->saar);
7334+
gen_helper_mtc0_saar(cpu_env, arg);
7335+
rn = "SAAR";
7336+
break;
72847337
default:
72857338
goto cp0_unimplemented;
72867339
}
@@ -20027,6 +20080,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
2002720080
ctx.pw = (env->CP0_Config3 >> CP0C3_PW) & 1;
2002820081
ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
2002920082
ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
20083+
ctx.saar = (bool) env->saarp;
2003020084
restore_cpu_state(env, &ctx);
2003120085
#ifdef CONFIG_USER_ONLY
2003220086
ctx.mem_idx = MIPS_HFLAG_UM;
@@ -20395,6 +20449,7 @@ void cpu_state_reset(CPUMIPSState *env)
2039520449
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
2039620450
env->msair = env->cpu_model->MSAIR;
2039720451
env->insn_flags = env->cpu_model->insn_flags;
20452+
env->saarp = env->cpu_model->SAARP;
2039820453

2039920454
#if defined(CONFIG_USER_ONLY)
2040020455
env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);

‎target-mips/translate_init.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ struct mips_def_t {
103103
int32_t CP0_PageGrain;
104104
int insn_flags;
105105
enum mips_mmu_types mmu_type;
106+
int32_t SAARP;
106107
};
107108

108109
/*****************************************************************************/

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