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target-mips: implement SAARI/SAAR registers
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SAARI (Special Address Access Register Index) provides an index into
the SAAR register to indicate whether the ITU or other block is being
accessed.
SAAR (Special Address Access Register) stores the base address where
the ITU will be located, as well as the block size.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
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yongbok committed Apr 26, 2017
1 parent a7f5415 commit c934049
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Showing 5 changed files with 103 additions and 2 deletions.
7 changes: 7 additions & 0 deletions target-mips/cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -368,6 +368,12 @@ struct CPUMIPSState {
uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP;
int32_t CP0_Count;
#define CP0SAARI_IDX 0
uint32_t CP0_SAARI;
#define CP0SAAR_BASE 12
#define CP0SAAR_SIZE 1
#define CP0SAAR_EN 0
uint64_t CP0_SAAR[2];
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
target_ulong CP0_EntryHi_ASID_mask;
Expand Down Expand Up @@ -634,6 +640,7 @@ struct CPUMIPSState {
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
int saarp;

CPU_COMMON

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4 changes: 4 additions & 0 deletions target-mips/helper.h
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env)
DEF_HELPER_1(mfc0_tcschefback, tl, env)
DEF_HELPER_1(mftc0_tcschefback, tl, env)
DEF_HELPER_1(mfc0_count, tl, env)
DEF_HELPER_1(mfc0_saar, tl, env)
DEF_HELPER_1(mfhc0_saar, tl, env)
DEF_HELPER_1(mftc0_entryhi, tl, env)
DEF_HELPER_1(mftc0_status, tl, env)
DEF_HELPER_1(mftc0_cause, tl, env)
Expand Down Expand Up @@ -133,6 +135,8 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
DEF_HELPER_2(mtc0_saar, void, env, tl)
DEF_HELPER_2(mthc0_saar, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
DEF_HELPER_2(mtc0_compare, void, env, tl)
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34 changes: 34 additions & 0 deletions target-mips/op_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -852,6 +852,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env)
return (int32_t)cpu_mips_get_count(env);
}

target_ulong helper_mfc0_saar(CPUMIPSState *env)
{
if ((env->CP0_SAARI & 0x3f) < 2) {
return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
}
return 0;
}

target_ulong helper_mfhc0_saar(CPUMIPSState *env)
{
if ((env->CP0_SAARI & 0x3f) < 2) {
return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
}
return 0;
}

target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
Expand Down Expand Up @@ -1458,6 +1474,24 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
cpu_mips_store_count(env, arg1);
}

void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
{
uint32_t target = env->CP0_SAARI & 0x3f;
if (target < 2) {
env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
}
}

void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
{
uint32_t target = env->CP0_SAARI & 0x3f;
if (target < 2) {
env->CP0_SAAR[target] =
(((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
(env->CP0_SAAR[target] & 0x00000000ffffffffULL);
}
}

void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val, mask;
Expand Down
59 changes: 57 additions & 2 deletions target-mips/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1438,6 +1438,7 @@ typedef struct DisasContext {
bool pw;
bool nan2008;
bool abs2008;
bool saar;
} DisasContext;

enum {
Expand Down Expand Up @@ -4845,6 +4846,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
case 9:
switch (sel) {
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mfhc0_saar(arg, cpu_env);
rn = "SAAR";
break;
default:
goto cp0_unimplemented;
}
break;
case 17:
switch (sel) {
case 0:
Expand Down Expand Up @@ -4917,6 +4929,17 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
case 9:
switch (sel) {
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mthc0_saar(cpu_env, arg);
rn = "SAAR";
break;
default:
goto cp0_unimplemented;
}
break;
case 17:
switch (sel) {
case 0:
Expand Down Expand Up @@ -5277,6 +5300,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->bstate = BS_STOP;
rn = "Count";
break;
case 6:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
rn = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mfc0_saar(arg, cpu_env);
rn = "SAAR";
break;
/* 6,7 are implementation dependent */
default:
goto cp0_unimplemented;
Expand Down Expand Up @@ -5940,7 +5973,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
/* 6,7 are implementation dependent */
case 6:
CP0_CHECK(ctx->saar);
tcg_gen_andi_tl(arg, arg, 0x3f);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SAARI));
rn = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
rn = "SAAR";
break;
default:
goto cp0_unimplemented;
}
Expand Down Expand Up @@ -7280,7 +7323,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
/* 6,7 are implementation dependent */
case 6:
CP0_CHECK(ctx->saar);
tcg_gen_andi_tl(arg, arg, 0x3f);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SAARI));
rn = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
rn = "SAAR";
break;
default:
goto cp0_unimplemented;
}
Expand Down Expand Up @@ -20027,6 +20080,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
ctx.pw = (env->CP0_Config3 >> CP0C3_PW) & 1;
ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
ctx.saar = (bool) env->saarp;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM;
Expand Down Expand Up @@ -20395,6 +20449,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
env->msair = env->cpu_model->MSAIR;
env->insn_flags = env->cpu_model->insn_flags;
env->saarp = env->cpu_model->SAARP;

#if defined(CONFIG_USER_ONLY)
env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
Expand Down
1 change: 1 addition & 0 deletions target-mips/translate_init.c
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Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,7 @@ struct mips_def_t {
int32_t CP0_PageGrain;
int insn_flags;
enum mips_mmu_types mmu_type;
int32_t SAARP;
};

/*****************************************************************************/
Expand Down

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