Implement RV64 bit manipulation instructions on 32-bit registers #1157

pavelkryukov · 2019-11-17T18:11:14Z

RISC-V Bit Manipulation instructions often have ".*W" companion which operate on 32-bit registers in 64-bit mode. Your goal is to implement these instructions using existing code.

pavelkryukov added enhancement Adds a new feature to simulation. 2 Small features, tests coverage, simple laboratory works S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA labels Nov 17, 2019

pavelkryukov added 3 Features of medium complexity or infrastructure enhancements 2 Small features, tests coverage, simple laboratory works and removed 2 Small features, tests coverage, simple laboratory works 3 Features of medium complexity or infrastructure enhancements labels Dec 1, 2019

pavelkryukov added good first issue Good task to start with MIPT-MIPS development 3 Features of medium complexity or infrastructure enhancements and removed 2 Small features, tests coverage, simple laboratory works labels Nov 10, 2020

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Implement RV64 bit manipulation instructions on 32-bit registers #1157

Implement RV64 bit manipulation instructions on 32-bit registers #1157

pavelkryukov commented Nov 17, 2019 •

edited

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Implement RV64 bit manipulation instructions on 32-bit registers #1157

Implement RV64 bit manipulation instructions on 32-bit registers #1157

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pavelkryukov commented Nov 17, 2019 • edited Loading

pavelkryukov commented Nov 17, 2019 •

edited

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