Perform cache line size study with variable cache miss latency

[pavelkryukov]

@alex19999 performed a study and found 1 / (1 + ax) dependency of IPC to cache line study.

However, in real life larger the large cache line size, the greater latency to get data from memory is. The low is linear, and we may consider that latency is 1 cycle to fetch 4 bytes of data.

The target is to study cache line size varying miss penalty latency, get new IPC dependency from cache line size, find a "sweet point" where IPC has a maximum, and provide analytic explanation if possible.

Use the report cited above as an example of report, and continue it under "Varying cache miss penalty" section.