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ddr3_debug.c
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ddr3_debug.c
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/*******************************************************************************
Copyright (C) 2016 Marvell International Ltd.
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the three
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
This program is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation, either version 2 of the License, or any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
********************************************************************************
Marvell GNU General Public License FreeRTOS Exception
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the Lesser
General Public License Version 2.1 plus the following FreeRTOS exception.
An independent module is a module which is not derived from or based on
FreeRTOS.
Clause 1:
Linking FreeRTOS statically or dynamically with other modules is making a
combined work based on FreeRTOS. Thus, the terms and conditions of the GNU
General Public License cover the whole combination.
As a special exception, the copyright holder of FreeRTOS gives you permission
to link FreeRTOS with independent modules that communicate with FreeRTOS solely
through the FreeRTOS API interface, regardless of the license terms of these
independent modules, and to copy and distribute the resulting combined work
under terms of your choice, provided that:
1. Every copy of the combined work is accompanied by a written statement that
details to the recipient the version of FreeRTOS used and an offer by yourself
to provide the FreeRTOS source code (including any modifications you may have
made) should the recipient request it.
2. The combined work is not itself an RTOS, scheduler, kernel or related
product.
3. The independent modules add significant and primary functionality to
FreeRTOS and do not merely extend the existing functionality already present in
FreeRTOS.
Clause 2:
FreeRTOS may not be used for any competitive or comparative purpose, including
the publication of any form of run time or compile time metric, without the
express permission of Real Time Engineers Ltd. (this is the norm within the
industry and is intended to ensure information accuracy).
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ddr3_init.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
u8 is_reg_dump = 0;
u8 debug_pbs = DEBUG_LEVEL_ERROR;
/*
* API to change flags outside of the lib
*/
#if defined(SILENT_LIB)
void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
{
/* do nothing */
}
#else /* SILENT_LIB */
/* Debug flags for other Training modules */
u8 debug_training_static = DEBUG_LEVEL_ERROR;
u8 debug_training = DEBUG_LEVEL_ERROR;
u8 debug_leveling = DEBUG_LEVEL_ERROR;
u8 debug_centralization = DEBUG_LEVEL_ERROR;
u8 debug_training_ip = DEBUG_LEVEL_ERROR;
u8 debug_training_bist = DEBUG_LEVEL_ERROR;
u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
u8 debug_training_access = DEBUG_LEVEL_ERROR;
u8 debug_training_device = DEBUG_LEVEL_ERROR;
#if defined(CONFIG_DDR4)
u8 debug_tap_tuning = DEBUG_LEVEL_ERROR;
u8 debug_calibration = DEBUG_LEVEL_ERROR;
u8 debug_ddr4_centralization = DEBUG_LEVEL_ERROR;
u8 debug_dm_tuning = DEBUG_LEVEL_ERROR;
#endif /* CONFIG_DDR4 */
void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
ddr3_hws_set_log_level(block, tm->debug_level);
};
void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
{
switch (block) {
case DEBUG_BLOCK_STATIC:
debug_training_static = level;
break;
case DEBUG_BLOCK_TRAINING_MAIN:
debug_training = level;
break;
case DEBUG_BLOCK_LEVELING:
debug_leveling = level;
break;
case DEBUG_BLOCK_CENTRALIZATION:
debug_centralization = level;
break;
case DEBUG_BLOCK_PBS:
debug_pbs = level;
break;
case DEBUG_BLOCK_ALG:
debug_training_hw_alg = level;
break;
case DEBUG_BLOCK_DEVICE:
debug_training_device = level;
break;
case DEBUG_BLOCK_ACCESS:
debug_training_access = level;
break;
case DEBUG_STAGES_REG_DUMP:
if (level == DEBUG_LEVEL_TRACE)
is_reg_dump = 1;
else
is_reg_dump = 0;
break;
#if defined(CONFIG_DDR4)
case DEBUG_TAP_TUNING_ENGINE:
debug_tap_tuning = level;
break;
case DEBUG_BLOCK_CALIBRATION:
debug_calibration = level;
break;
case DEBUG_BLOCK_DDR4_CENTRALIZATION:
debug_ddr4_centralization = level;
break;
#endif /* CONFIG_DDR4 */
case DEBUG_BLOCK_ALL:
default:
debug_training_static = level;
debug_training = level;
debug_leveling = level;
debug_centralization = level;
debug_pbs = level;
debug_training_hw_alg = level;
debug_training_access = level;
debug_training_device = level;
#if defined(CONFIG_DDR4)
debug_tap_tuning = level;
debug_calibration = level;
debug_ddr4_centralization = level;
#endif /* CONFIG_DDR4 */
}
}
#endif /* SILENT_LIB */
#if defined(DDR_VIEWER_TOOL)
static char *convert_freq(enum mv_ddr_freq freq);
#if defined(EXCLUDE_SWITCH_DEBUG)
u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
#endif /* EXCLUDE_SWITCH_DEBUG */
#endif /* DDR_VIEWER_TOOL */
struct hws_tip_config_func_db config_func_info[MAX_DEVICE_NUM];
u8 is_default_centralization = 0;
u8 is_tune_result = 0;
u8 is_validate_window_per_if = 0;
u8 is_validate_window_per_pup = 0;
u8 sweep_cnt = 1;
u32 is_bist_reset_bit = 1;
u8 is_run_leveling_sweep_tests;
static struct hws_xsb_info xsb_info[MAX_DEVICE_NUM];
/*
* Dump Dunit & Phy registers
*/
int ddr3_tip_reg_dump(u32 dev_num)
{
u32 if_id, reg_addr, data_value, bus_id;
u32 read_data[MAX_INTERFACE_NUM];
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
printf("-- dunit registers --\n");
for (reg_addr = 0x1400; reg_addr < 0x19f0; reg_addr += 4) {
printf("0x%x ", reg_addr);
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST,
if_id, reg_addr, read_data,
MASK_ALL_BITS));
printf("0x%x ", read_data[if_id]);
}
printf("\n");
}
printf("-- Phy registers --\n");
for (reg_addr = 0; reg_addr <= 0xff; reg_addr++) {
printf("0x%x ", reg_addr);
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0;
bus_id < octets_per_if_num;
bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_DATA, reg_addr,
&data_value));
printf("0x%x ", data_value);
}
for (bus_id = 0;
bus_id < octets_per_if_num;
bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_CONTROL, reg_addr,
&data_value));
printf("0x%x ", data_value);
}
}
printf("\n");
}
return MV_OK;
}
/*
* Register access func registration
*/
int ddr3_tip_init_config_func(u32 dev_num,
struct hws_tip_config_func_db *config_func)
{
if (config_func == NULL)
return MV_BAD_PARAM;
memcpy(&config_func_info[dev_num], config_func,
sizeof(struct hws_tip_config_func_db));
return MV_OK;
}
/*
* Get training result info pointer
*/
enum hws_result *ddr3_tip_get_result_ptr(u32 stage)
{
return training_result[stage];
}
/*
* Device info read
*/
int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr)
{
if (config_func_info[dev_num].tip_get_device_info_func != NULL) {
return config_func_info[dev_num].
tip_get_device_info_func((u8) dev_num, info_ptr);
}
return MV_FAIL;
}
#if defined(DDR_VIEWER_TOOL)
/*
* Convert freq to character string
*/
static char *convert_freq(enum mv_ddr_freq freq)
{
switch (freq) {
case MV_DDR_FREQ_LOW_FREQ:
return "MV_DDR_FREQ_LOW_FREQ";
#if !defined(CONFIG_DDR4)
case MV_DDR_FREQ_400:
return "400";
case MV_DDR_FREQ_533:
return "533";
#endif /* CONFIG_DDR4 */
case MV_DDR_FREQ_667:
return "667";
case MV_DDR_FREQ_800:
return "800";
case MV_DDR_FREQ_933:
return "933";
case MV_DDR_FREQ_1066:
return "1066";
#if !defined(CONFIG_DDR4)
case MV_DDR_FREQ_311:
return "311";
case MV_DDR_FREQ_333:
return "333";
case MV_DDR_FREQ_467:
return "467";
case MV_DDR_FREQ_850:
return "850";
case MV_DDR_FREQ_900:
return "900";
case MV_DDR_FREQ_360:
return "MV_DDR_FREQ_360";
case MV_DDR_FREQ_1000:
return "MV_DDR_FREQ_1000";
#endif /* CONFIG_DDR4 */
default:
return "Unknown Frequency";
}
}
/*
* Convert device ID to character string
*/
static char *convert_dev_id(u32 dev_id)
{
switch (dev_id) {
case 0x6800:
return "A38xx";
case 0x6900:
return "A39XX";
case 0xf400:
return "AC3";
case 0xfc00:
return "BC2";
default:
return "Unknown Device";
}
}
/*
* Convert device ID to character string
*/
static char *convert_mem_size(u32 dev_id)
{
switch (dev_id) {
case 0:
return "512 MB";
case 1:
return "1 GB";
case 2:
return "2 GB";
case 3:
return "4 GB";
case 4:
return "8 GB";
default:
return "wrong mem size";
}
}
int print_device_info(u8 dev_num)
{
struct ddr3_device_info info_ptr;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
CHECK_STATUS(ddr3_tip_get_device_info(dev_num, &info_ptr));
printf("=== DDR setup START===\n");
printf("\tDevice ID: %s\n", convert_dev_id(info_ptr.device_id));
printf("\tDDR3 CK delay: %d\n", info_ptr.ck_delay);
print_topology(tm);
printf("=== DDR setup END===\n");
return MV_OK;
}
void hws_ddr3_tip_sweep_test(int enable)
{
if (enable) {
is_validate_window_per_if = 1;
is_validate_window_per_pup = 1;
debug_training = DEBUG_LEVEL_TRACE;
} else {
is_validate_window_per_if = 0;
is_validate_window_per_pup = 0;
}
}
#endif /* DDR_VIEWER_TOOL */
char *ddr3_tip_convert_tune_result(enum hws_result tune_result)
{
switch (tune_result) {
case TEST_FAILED:
return "FAILED";
case TEST_SUCCESS:
return "PASS";
case NO_TEST_DONE:
return "NOT COMPLETED";
default:
return "Un-KNOWN";
}
}
/*
* Print log info
*/
int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
{
u32 if_id = 0;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
#if defined(DDR_VIEWER_TOOL)
if ((is_validate_window_per_if != 0) ||
(is_validate_window_per_pup != 0)) {
u32 is_pup_log = 0;
enum mv_ddr_freq freq;
freq = tm->interface_params[first_active_if].memory_freq;
is_pup_log = (is_validate_window_per_pup != 0) ? 1 : 0;
printf("===VALIDATE WINDOW LOG START===\n");
printf("DDR Frequency: %s ======\n", convert_freq(freq));
/* print sweep windows */
ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
#if defined(EXCLUDE_SWITCH_DEBUG)
if (is_run_leveling_sweep_tests == 1) {
ddr3_tip_run_leveling_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
ddr3_tip_run_leveling_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
}
#endif /* EXCLUDE_SWITCH_DEBUG */
ddr3_tip_print_all_pbs_result(dev_num);
ddr3_tip_print_wl_supp_result(dev_num);
printf("===VALIDATE WINDOW LOG END ===\n");
CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
ddr3_tip_reg_dump(dev_num);
}
#endif /* DDR_VIEWER_TOOL */
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("IF %d Status:\n", if_id));
if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tInit Controller: %s\n",
ddr3_tip_convert_tune_result
(training_result[INIT_CONTROLLER]
[if_id])));
}
if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tLow freq Config: %s\n",
ddr3_tip_convert_tune_result
(training_result[SET_LOW_FREQ]
[if_id])));
}
if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tLoad Pattern: %s\n",
ddr3_tip_convert_tune_result
(training_result[LOAD_PATTERN]
[if_id])));
}
if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tMedium freq Config: %s\n",
ddr3_tip_convert_tune_result
(training_result[SET_MEDIUM_FREQ]
[if_id])));
}
if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tWL: %s\n",
ddr3_tip_convert_tune_result
(training_result[WRITE_LEVELING]
[if_id])));
}
if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tLoad Pattern: %s\n",
ddr3_tip_convert_tune_result
(training_result[LOAD_PATTERN_2]
[if_id])));
}
if (mask_tune_func & READ_LEVELING_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tRL: %s\n",
ddr3_tip_convert_tune_result
(training_result[READ_LEVELING]
[if_id])));
}
if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tWL Supp: %s\n",
ddr3_tip_convert_tune_result
(training_result[WRITE_LEVELING_SUPP]
[if_id])));
}
if (mask_tune_func & PBS_RX_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tPBS RX: %s\n",
ddr3_tip_convert_tune_result
(training_result[PBS_RX]
[if_id])));
}
if (mask_tune_func & PBS_TX_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tPBS TX: %s\n",
ddr3_tip_convert_tune_result
(training_result[PBS_TX]
[if_id])));
}
if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tTarget freq Config: %s\n",
ddr3_tip_convert_tune_result
(training_result[SET_TARGET_FREQ]
[if_id])));
}
if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tWL TF: %s\n",
ddr3_tip_convert_tune_result
(training_result[WRITE_LEVELING_TF]
[if_id])));
}
#if !defined(CONFIG_DDR4)
if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tRL TF: %s\n",
ddr3_tip_convert_tune_result
(training_result[READ_LEVELING_TF]
[if_id])));
}
#endif /* CONFIG_DDR4 */
if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tWL TF Supp: %s\n",
ddr3_tip_convert_tune_result
(training_result
[WRITE_LEVELING_SUPP_TF]
[if_id])));
}
if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tCentr RX: %s\n",
ddr3_tip_convert_tune_result
(training_result[CENTRALIZATION_RX]
[if_id])));
}
if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tVREF_CALIBRATION: %s\n",
ddr3_tip_convert_tune_result
(training_result[VREF_CALIBRATION]
[if_id])));
}
if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tCentr TX: %s\n",
ddr3_tip_convert_tune_result
(training_result[CENTRALIZATION_TX]
[if_id])));
}
#if defined(CONFIG_DDR4)
if (mask_tune_func & SW_READ_LEVELING_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tSW RL TF: %s\n",
ddr3_tip_convert_tune_result
(training_result[SW_READ_LEVELING]
[if_id])));
}
if (mask_tune_func & RECEIVER_CALIBRATION_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tRX CAL: %s\n",
ddr3_tip_convert_tune_result
(training_result[RECEIVER_CALIBRATION]
[if_id])));
}
if (mask_tune_func & WL_PHASE_CORRECTION_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tWL PHASE CORRECT: %s\n",
ddr3_tip_convert_tune_result
(training_result[WL_PHASE_CORRECTION]
[if_id])));
}
if (mask_tune_func & DQ_VREF_CALIBRATION_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tDQ VREF CAL: %s\n",
ddr3_tip_convert_tune_result
(training_result[DQ_VREF_CALIBRATION]
[if_id])));
}
if (mask_tune_func & DQ_MAPPING_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("\tDQ MAP: %s\n",
ddr3_tip_convert_tune_result
(training_result[DQ_MAPPING]
[if_id])));
}
#endif /* CONFIG_DDR4 */
}
return MV_OK;
}
#if !defined(EXCLUDE_DEBUG_PRINTS)
/*
* Print stability log info
*/
int ddr3_tip_print_stability_log(u32 dev_num)
{
u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0;
u32 reg_data;
#if defined(CONFIG_DDR4)
u32 reg_data1;
#endif /* CONFIG_DDR4 */
u32 read_data[MAX_INTERFACE_NUM];
unsigned int max_cs = mv_ddr_cs_num_get();
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
/* Title print */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
printf("Title: I/F# , Tj, Calibration_n0, Calibration_p0, Calibration_n1, Calibration_p1, Calibration_n2, Calibration_p2,");
for (csindex = 0; csindex < max_cs; csindex++) {
printf("CS%d , ", csindex);
printf("\n");
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
#if defined(CONFIG_DDR4)
printf("DminTx, AreaTx, DminRx, AreaRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, CenTx, CenRx, Vref, DQVref,");
for (idx = 0; idx < 11; idx++)
printf("DC-Pad%d,", idx);
#else /* CONFIG_DDR4 */
printf("VWTx, VWRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, Cen_tx, Cen_rx, Vref, DQVref,");
#endif /* CONFIG_DDR4 */
printf("\t\t");
for (idx = 0; idx < 11; idx++)
printf("PBSTx-Pad%d,", idx);
printf("\t\t");
for (idx = 0; idx < 11; idx++)
printf("PBSRx-Pad%d,", idx);
}
}
printf("\n");
/* Data print */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
printf("Data: %d,%d,", if_id,
(config_func_info[dev_num].tip_get_temperature != NULL)
? (config_func_info[dev_num].
tip_get_temperature(dev_num)) : (0));
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x14c8,
read_data, MASK_ALL_BITS));
printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
((read_data[if_id] & 0xfc00) >> 10));
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x17c8,
read_data, MASK_ALL_BITS));
printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
((read_data[if_id] & 0xfc00) >> 10));
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1dc8,
read_data, MASK_ALL_BITS));
printf("%d,%d,", ((read_data[if_id] & 0x3f0000) >> 16),
((read_data[if_id] & 0xfc00000) >> 22));
for (csindex = 0; csindex < max_cs; csindex++) {
printf("CS%d , ", csindex);
for (bus_id = 0; bus_id < MAX_BUS_NUM; bus_id++) {
printf("\n");
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
#if defined(CONFIG_DDR4)
/* DminTx, areaTX */
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
RESULT_PHY_REG +
csindex, ®_data);
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
dmin_phy_reg_table
[csindex * 5 + bus_id][0],
DDR_PHY_CONTROL,
dmin_phy_reg_table
[csindex * 5 + bus_id][1],
®_data1);
printf("%d,%d,", 2 * (reg_data1 & 0xFF),
reg_data);
/* DminRx, areaRX */
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
RESULT_PHY_REG +
csindex + 4, ®_data);
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
dmin_phy_reg_table
[csindex * 5 + bus_id][0],
DDR_PHY_CONTROL,
dmin_phy_reg_table
[csindex * 5 + bus_id][1],
®_data1);
printf("%d,%d,", 2 * (reg_data1 >> 8),
reg_data);
#else /* CONFIG_DDR4 */
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
RESULT_PHY_REG +
csindex, ®_data);
printf("%d,%d,", (reg_data & 0x1f),
((reg_data & 0x3e0) >> 5));
#endif /* CONFIG_DDR4 */
/* WL */
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
WL_PHY_REG(csindex),
®_data);
printf("%d,%d,%d,",
(reg_data & 0x1f) +
((reg_data & 0x1c0) >> 6) * 32,
(reg_data & 0x1f),
(reg_data & 0x1c0) >> 6);
/* RL */
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST,
if_id,
RD_DATA_SMPL_DLYS_REG,
read_data, MASK_ALL_BITS));
read_data[if_id] =
(read_data[if_id] &
(0x1f << (8 * csindex))) >>
(8 * csindex);
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_DATA,
RL_PHY_REG(csindex),
®_data);
printf("%d,%d,%d,%d,",
(reg_data & 0x1f) +
((reg_data & 0x1c0) >> 6) * 32 +
read_data[if_id] * 64,
(reg_data & 0x1f),
((reg_data & 0x1c0) >> 6),
read_data[if_id]);
/* Centralization */
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_DATA,
CTX_PHY_REG(csindex),
®_data);
printf("%d,", (reg_data & 0x3f));
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_DATA,
CRX_PHY_REG(csindex),
®_data);
printf("%d,", (reg_data & 0x1f));
/* Vref */
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_DATA,
PAD_CFG_PHY_REG,
®_data);
printf("%d,", (reg_data & 0x7));
/* DQVref */
/* Need to add the Read Function from device */
printf("%d,", 0);
#if defined(CONFIG_DDR4)
printf("\t\t");
for (idx = 0; idx < 11; idx++) {
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
0xd0 + 12 * csindex +
idx, ®_data);
printf("%d,", (reg_data & 0x3f));
}
#endif /* CONFIG_DDR4 */
printf("\t\t");
for (idx = 0; idx < 11; idx++) {
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
0x10 +
16 * csindex +
idx, ®_data);
printf("%d,", (reg_data & 0x3f));
}
printf("\t\t");
for (idx = 0; idx < 11; idx++) {
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
0x50 +
16 * csindex +
idx, ®_data);
printf("%d,", (reg_data & 0x3f));
}
}
}
}
printf("\n");
return MV_OK;
}
#endif /* EXCLUDE_DEBUG_PRINTS */
/*
* Register XSB information
*/
int ddr3_tip_register_xsb_info(u32 dev_num, struct hws_xsb_info *xsb_info_table)
{
memcpy(&xsb_info[dev_num], xsb_info_table, sizeof(struct hws_xsb_info));
return MV_OK;
}
/*
* Read ADLL Value
*/
int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 reg_addr, u32 mask)
{
u32 data_value;
u32 if_id = 0, bus_id = 0;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
/*
* multi CS support - reg_addr is calucalated in calling function
* with CS offset
*/
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0; bus_id < octets_per_if_num;
bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id,
DDR_PHY_DATA, reg_addr,
&data_value));
pup_values[if_id *
octets_per_if_num + bus_id] =
data_value & mask;
}
}
return 0;
}
/*
* Write ADLL Value
*/
int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 reg_addr)
{
u32 if_id = 0, bus_id = 0;
u32 data;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
/*
* multi CS support - reg_addr is calucalated in calling function
* with CS offset
*/
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0; bus_id < octets_per_if_num;
bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
data = pup_values[if_id *
octets_per_if_num +
bus_id];
CHECK_STATUS(ddr3_tip_bus_write(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
reg_addr, data));
}
}
return 0;
}
/**
* Read Phase Value
*/
int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
int reg_addr, u32 mask)
{
u32 data_value;
u32 if_id = 0, bus_id = 0;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
/* multi CS support - reg_addr is calucalated in calling function with CS offset */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST,
bus_id,
DDR_PHY_DATA, reg_addr,
&data_value));
pup_values[if_id * octets_per_if_num + bus_id] = data_value & mask;
}
}
return 0;
}
/**
* Write Leveling Value
*/
int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr)
{
u32 if_id = 0, bus_id = 0;
u32 data;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
/* multi CS support - reg_addr is calucalated in calling function with CS offset */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0 ; bus_id < octets_per_if_num ; bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
data = pup_values[if_id * octets_per_if_num + bus_id] +
pup_ph_values[if_id * octets_per_if_num + bus_id];
CHECK_STATUS(ddr3_tip_bus_write(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST,
bus_id,