Nanomips into llvm16 #37
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Note that halfword load and store are not being selected at the moment.
UImm12 offset was not getting correctly set and Imm9 instructions were never getting selected. There was no pattern for selecting Imm9 anyextending loads (fixed).
Change-Id: I2fbdb326bd20cba3a8fd825dd1f7f7291c34436e
nanoMIPS mnemonics can have an optional architectural suffix to disambiguate multiple instructions which have the same mnemonic. As per the ISA, this suffix is enclosed in square brackets, for example: li[48]. The assembly parser must tokenize the suffix along with the mnemonic as one token. Change-Id: I240d7de279800650c6b36600a8bbfd83559ae4d5
Change-Id: I2dbd5e00ce450cf966f60d836a9b42ff954925d5
Change-Id: If77b00b39437aeb736603f0de240613aec52594d
Change-Id: Ifa98c5c333b9f332a9c8c5aed824c3fefdeb2036
GNU assembler supports this syntax Change-Id: Iec7fe84c7f1c50886e4edaa69f9f79489a998d72
Change-Id: I47302764c3e4005f9e7609fdf49c85f039978ecc
Change-Id: If5dc329ea6fae1a80cc58223164e598a61f4c35c
Change-Id: Ib239b18b5fe2d2e91e82dd19e31d4d4a27cf0d97
The erstwhile default which assumes that the general purpose register set is always under high pressure leads to better allocation on average than the general MIPS model which allows free allocation of up to 28 registers. Revert to earlier behaviour for now, to be looked in to along with scheduling changes. Change-Id: I2e8b04edf49552a591f4f65cd33aef652a44e88e
Change-Id: I8fee60e432e8619a79a95c1ca0142de36f242184
Change-Id: I0b36e83828d5f8641ddf70fb7b1b56c3d77235ad
Change-Id: Iea67daf6e020de023b8b6c76e60af75b2d2e49dd
The assembler dialect in the parser class is only set up when parsing assembly files. For inline assembly, it must be obtained from AsmInfo in order to correctly reflect the ISA mode. Change-Id: Iea23bcbc365fe127d1f2a0ba113db6a46012286e
Change-Id: Ic38cc32a089b7682a9cd77169e3db28ecb56667d
Inheritance structure of ParserMatchClass determines the order of instructions in MatchTable. Inherit 25-bit call operand from 10-bit call operand in order to prioritize it. This is required for balc-stubs optimization in the linker. Change-Id: I3c96d1f61862e76936e5b444bbe6280d031ed6b1
* R_NANOMIPS_TRAMP needed to inhibit stub optimization * R_NANOMIPS_NONE backend handling was missing. Added for sake of completeness. Change-Id: I3382994a7a67edc6fbe13a5ac1622934ad05da16
Change-Id: Ie09b2dc1f7041c33ba67525a3e6e59144eed5af0
Typical branch target is represented as a symbol and the assembler emits a relocation that the linker resolves to the final branch address. For immediate operands as well, we can treat the operand as a target address and emit a relocation that the linker can resolve to reach that address. This patch brings integrated assembler's handling of immediate operands in line with GNU assembler. Change-Id: Ic72fe65cb5f5617b844bd0f7ef9803be0d17d28e
* Add support for converting .shword and .sbyte data directives to R_NANOMIPS_SIGNED_[8|16] relocations. * Maps expressions with 1-bit right-shift to R_NANOMIPS_ASHIFTR_1 Change-Id: I2294313664f8eb1cfd2052f39c86e5328b0648d5
* Parse and ignore .jumptable directive * Parse and ignore R_NANOMIPS_JUMPTABLE_LOAD relocation This is to facilitate the compiler to enable jump-table compression regardless of whether it uses integrated or external assembler. It does not have any impact on object encoding generated by integrated assembler, but allows the same generated assembly to be handled by either assemblers. Change-Id: I8f9ed12c7acf5cef11fada62f230ce92cd363750
Native MTTR/MFTR instructions should only accept COP registers, that is simple numbered registers as the second operand. Translate the incoming registers from the aliases to the correct format. Change-Id: I778f374feff3ea9022905314c0c2e262b1909f3c
* Disable linker relaxation by default to match GNU assembler * Disable PC-relative addressing by default to match GNU assembler * Don't emit directives to enable PC-relative addressing and linker relaxations unconditionally in assembly file. Instead check subtarget features to decide when these must be enabled. * Test-suite updates to match new defaults Change-Id: I54f32c77edd7f8ef0352bc6e87ec86ca7c4cec02
* Use cc1as as the external assembler when compiling LTO with -fintegrated-as * When using nanomips-elf-as as external assembler for LTO, pass option -mlegacyregs to work around different MTTR/MFTR operand constraints. Change-Id: Ic2540162637dfa76cfe243ac3ab127e259f0e9a9
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@nikolaperic @milica-lazarevic what is the status of this? |
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This PR is ready to be merged. |
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