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rshim.c
3165 lines (2663 loc) · 84.4 KB
/
rshim.c
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// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
/*
* Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved.
*
*/
#include <arpa/inet.h>
#include <getopt.h>
#include <netinet/in.h>
#include <pthread.h>
#include <signal.h>
#include <stdio.h>
#include <sys/epoll.h>
#include <sys/mount.h>
#include <sys/param.h>
#include <sys/poll.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/timerfd.h>
#include <sys/time.h>
#include <unistd.h>
#include "rshim.h"
/* Maximum number of devices supported (currently it's limited to 64). */
#define RSHIM_MAX_DEV 64
/* RShim timer interval in milliseconds. */
#define RSHIM_TIMER_INTERVAL 1
/* Cycles to poll the network initialization before timeout. */
#define RSHIM_NET_INIT_DELAY (60000 / RSHIM_TIMER_INTERVAL)
/* Reserve some space to indicate full. */
#define RSHIM_FIFO_SPACE_RESERV 3
/* Keepalive period in milliseconds. */
static int rshim_keepalive_period = 300;
/* Keepalive magic number. */
#define RSHIM_KEEPALIVE_MAGIC_NUM 0x5089836482ULL
/* Circular buffer macros. */
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), ((head)+1), (size))
#define CIRC_SPACE_TO_END(head, tail, size) \
({int end = (size) - 1 - (head); \
int n = (end + (tail)) & ((size)-1); \
n <= end ? n : end+1; })
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & ((size)-1))
#define CIRC_CNT_TO_END(head, tail, size) \
({int end = (size) - (tail); \
int n = ((head) + end) & ((size)-1); \
n < end ? n : end; })
#define read_empty(bd, chan) \
(CIRC_CNT((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE) == 0)
#define read_full(bd, chan) \
(CIRC_SPACE((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE) == 0)
#define read_space(bd, chan) \
CIRC_SPACE((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_cnt(bd, chan) \
CIRC_CNT((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_cnt_to_end(bd, chan) \
CIRC_CNT_TO_END((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_data_ptr(bd, chan) \
((bd)->read_fifo[chan].data + \
((bd)->read_fifo[chan].tail & (READ_FIFO_SIZE - 1)))
#define read_consume_bytes(bd, chan, nbytes) \
((bd)->read_fifo[chan].tail = \
((bd)->read_fifo[chan].tail + (nbytes)) & (READ_FIFO_SIZE - 1))
#define read_space_to_end(bd, chan) \
CIRC_SPACE_TO_END((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_space_offset(bd, chan) \
((bd)->read_fifo[chan].head & (READ_FIFO_SIZE - 1))
#define read_space_ptr(bd, chan) \
((bd)->read_fifo[chan].data + read_space_offset(bd, (chan)))
#define read_add_bytes(bd, chan, nbytes) \
((bd)->read_fifo[chan].head = \
((bd)->read_fifo[chan].head + (nbytes)) & (READ_FIFO_SIZE - 1))
#define read_reset(bd, chan) \
((bd)->read_fifo[chan].head = (bd)->read_fifo[chan].tail = 0)
#define write_empty(bd, chan) \
(CIRC_CNT((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE) == 0)
#define write_full(bd, chan) \
(CIRC_SPACE((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE) == 0)
#define write_space(bd, chan) \
CIRC_SPACE((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_cnt(bd, chan) \
CIRC_CNT((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_cnt_to_end(bd, chan) \
CIRC_CNT_TO_END((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_data_offset(bd, chan) \
((bd)->write_fifo[chan].tail & (WRITE_FIFO_SIZE - 1))
#define write_data_ptr(bd, chan) \
((bd)->write_fifo[chan].data + write_data_offset(bd, (chan)))
#define write_consume_bytes(bd, chan, nbytes) \
((bd)->write_fifo[chan].tail = \
((bd)->write_fifo[chan].tail + (nbytes)) & (WRITE_FIFO_SIZE - 1))
#define write_space_to_end(bd, chan) \
CIRC_SPACE_TO_END((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_space_ptr(bd, chan) \
((bd)->write_fifo[chan].data + \
((bd)->write_fifo[chan].head & (WRITE_FIFO_SIZE - 1)))
#define write_add_bytes(bd, chan, nbytes) \
((bd)->write_fifo[chan].head = \
((bd)->write_fifo[chan].head + (nbytes)) & (WRITE_FIFO_SIZE - 1))
#define write_reset(bd, chan) \
((bd)->write_fifo[chan].head = (bd)->write_fifo[chan].tail = 0)
/*
* Tile-to-host bits (UART 0 scratchpad).
*/
/*
* Output write pointer mask. Note that this is the maximum size; the
* write pointer may be smaller if requested by the host.
*/
#define CONS_RSHIM_T2H_OUT_WPTR_MASK 0x3FF
/* Tile is done mask. */
#define CONS_RSHIM_T2H_DONE_MASK 0x400
/*
* Input read pointer mask. Note that this is the maximum size; the read
* pointer may be smaller if requested by the host.
*/
#define CONS_RSHIM_T2H_IN_RPTR_MASK 0x1FF800
/* Input read pointer shift. */
#define CONS_RSHIM_T2H_IN_RPTR_SHIFT 11
/* Tile is done mask. */
#define CONS_RSHIM_T2H_DONE_MASK 0x400
/* Number of words to send as sync-data (calculated by packet MTU). */
#define TMFIFO_MAX_SYNC_WORDS (1536 / 8)
/* Terminal characteristics for newly created consoles. */
#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
static struct termios init_console_termios = {
.c_iflag = INLCR | ICRNL,
.c_oflag = OPOST | ONLCR,
.c_cflag = B115200 | HUPCL | CLOCAL | CREAD | CS8,
.c_lflag = ISIG | ICANON | ECHOE | ECHOK | ECHOCTL | ECHOKE | IEXTEN,
.c_cc = INIT_C_CC,
};
/* RShim global mutex. */
static pthread_mutex_t rshim_mutex = PTHREAD_MUTEX_INITIALIZER;
/* RShim mutex for global fd read/write. */
static pthread_mutex_t rshim_fd_mutex = PTHREAD_MUTEX_INITIALIZER;
/* Current timer ticks. */
static int rshim_timer_ticks;
/* File handler for the worker function. */
static int rshim_work_fd[2];
/* Current RShim backend name. */
static char *rshim_backend_name;
/* Global epoll handler. */
int rshim_epoll_fd;
/* Static rshim index (/dev/rshim<index>) and device name. */
int rshim_static_index = -1;
char *rshim_static_dev_name;
/* Default configuration file. */
const char *rshim_cfg_file = DEFAULT_RSHIM_CONFIG_FILE;
static int rshim_display_level = 0;
static int rshim_boot_timeout = 150;
int rshim_drop_mode = -1;
int rshim_usb_reset_delay = 1;
bool rshim_has_usb_reset_delay = false;
int rshim_pcie_reset_delay = 5;
bool rshim_has_pcie_reset_delay = false;
int rshim_pcie_enable_vfio = 1;
int rshim_pcie_enable_uio = 1;
int rshim_pcie_intr_poll_interval = 10; /* Interrupt polling in milliseconds */
/* Array of devices and device names. */
rshim_backend_t *rshim_devs[RSHIM_MAX_DEV];
char *rshim_dev_names[RSHIM_MAX_DEV];
char *rshim_blocked_dev_names[RSHIM_MAX_DEV];
/* Bitmask of the used rshim device id. */
#if RSHIM_MAX_DEV > 64
#error Need to fix the size of rshim_dev_bitmask.
#endif
uint64_t rshim_dev_bitmask;
bool rshim_no_net = false;
int rshim_log_level = LOG_NOTICE;
bool rshim_daemon_mode = true;
volatile bool rshim_run = true;
static uint32_t rshim_timer_interval = RSHIM_TIMER_INTERVAL;
static void rshim_fifo_msg_update_checksum(rshim_tmfifo_msg_hdr_t *hdr);
/* Global lock / unlock. */
void rshim_lock(void)
{
pthread_mutex_lock(&rshim_mutex);
}
int rshim_trylock(void)
{
return pthread_mutex_trylock(&rshim_mutex);
}
void rshim_unlock(void)
{
pthread_mutex_unlock(&rshim_mutex);
}
static int rshim_fd_full_read(int fd, void *data, int len)
{
char *buf = (char *)data;
int cc, total = 0;
pthread_mutex_lock(&rshim_fd_mutex);
while (len > 0) {
cc = read(fd, buf, len);
if (cc < 0) {
if (errno == EINTR || errno == EAGAIN) {
usleep(1000);
continue;
}
pthread_mutex_unlock(&rshim_fd_mutex);
return -1;
}
if (cc == 0)
break;
buf += cc;
total += cc;
len -= cc;
}
pthread_mutex_unlock(&rshim_fd_mutex);
return total;
}
static int rshim_fd_full_write(int fd, void *data, int len)
{
int total = 0;
char *buf = (char *)data;
pthread_mutex_lock(&rshim_fd_mutex);
while (len > 0) {
ssize_t written = write(fd, buf, len);
if (written < 0) {
if (errno == EINTR || errno == EAGAIN) {
usleep(1000);
continue;
}
RSHIM_ERR("fd write error %d\n", (int)written);
pthread_mutex_unlock(&rshim_fd_mutex);
return written;
}
total += written;
buf += written;
len -= written;
}
pthread_mutex_unlock(&rshim_fd_mutex);
return total;
}
/* Wake up the epoll loop or worker function. */
void rshim_work_signal(rshim_backend_t *bd)
{
uint8_t index = (uint8_t)-1;
bool update = true;
if (bd) {
if (__sync_bool_compare_and_swap(&bd->work_pending, false, true))
index = (uint8_t)bd->index;
else
update = false;
}
if (update)
rshim_fd_full_write(rshim_work_fd[1], &index, sizeof(index));
}
/*
* Read some bytes from RShim.
*
* The provided buffer size should be multiple of 8 bytes. If not, the
* leftover bytes (which presumably were sent as NUL bytes by the sender)
* will be discarded.
*/
static ssize_t rshim_read_default(rshim_backend_t *bd, int devtype,
char *buf, size_t count)
{
int rc, total = 0, avail = 0;
uint64_t reg;
/* Read is only supported for RShim TMFIFO. */
if (devtype != RSH_DEV_TYPE_TMFIFO) {
RSHIM_ERR("bad devtype %d\n", devtype);
return -EINVAL;
}
while (total < count) {
if (avail == 0) {
reg = 0;
rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_sts, ®, RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(reg))
break;
avail = reg & RSH_TM_TILE_TO_HOST_STS__COUNT_MASK;
if (avail == 0)
break;
}
rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_data, ®, RSHIM_REG_SIZE_8B);
if (rc < 0)
break;
/*
* Convert it to little endian before sending to RShim. The other side
* should decode it as little endian as well which is usually the default
* case.
*/
reg = le64toh(reg);
if (total + sizeof(reg) <= count) {
*(uint64_t *)buf = reg;
buf += sizeof(reg);
total += sizeof(reg);
} else {
/* Copy the rest data which is less than 8 bytes. */
memcpy(buf, ®, count - total);
total = count;
break;
}
avail--;
}
return total;
}
/*
* Write some bytes to the RShim backend.
*
* If count is not multiple of 8-bytes, the data will be padded to 8-byte
* aligned which is required by RShim HW.
*/
static ssize_t rshim_write_delayed(rshim_backend_t *bd, int devtype,
const uint8_t *buf, size_t count)
{
int size_addr, size_mask, data_addr, max_size;
uint8_t pad_buf[sizeof(uint64_t)] = { 0 };
int rc, avail = 0, byte_cnt = 0;
time_t t0, t1;
uint64_t reg;
switch (devtype) {
case RSH_DEV_TYPE_TMFIFO:
if (bd->is_boot_open || bd->drop_mode)
return count;
size_addr = bd->regs->tm_htt_sts;
size_mask = RSH_TM_HOST_TO_TILE_STS__COUNT_MASK;
data_addr = bd->regs->tm_htt_data;
max_size = RSH_TM_FIFO_SIZE;
break;
case RSH_DEV_TYPE_BOOT:
size_addr = bd->regs->boot_fifo_count;
size_mask = bd->regs->boot_fifo_count_mask;
data_addr = bd->regs->boot_fifo_data;
max_size = RSH_BOOT_FIFO_SIZE;
break;
default:
RSHIM_ERR("bad devtype %d\n", devtype);
return -EINVAL;
}
while (byte_cnt < count) {
/* Check the boot cancel condition. */
if (devtype == RSH_DEV_TYPE_BOOT && !bd->boot_work_buf)
break;
/* Add padding if less than 8 bytes left. */
if (byte_cnt + sizeof(uint64_t) > count) {
memcpy(pad_buf, buf, count - byte_cnt);
buf = (const uint8_t *)pad_buf;
}
time(&t0);
while (avail <= 0) {
/* Calculate available space in words. */
rc = bd->read_rshim(bd, RSHIM_CHANNEL, size_addr, ®, RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(reg)) {
RSHIM_ERR("rshim%d read_rshim error addr=0x%x, reg=0x%lx, rc=%d\n",
bd->index, size_addr, (long unsigned int)reg, rc);
usleep(10000);
return count;
}
avail = max_size - (int)(reg & size_mask) - RSHIM_FIFO_SPACE_RESERV;
if (avail > 0)
break;
if (devtype == RSH_DEV_TYPE_BOOT)
goto done;
time(&t1);
if (difftime(t1, t0) > 3) {
if (devtype == RSH_DEV_TYPE_TMFIFO && bd->is_booting)
return count;
else
return -ETIMEDOUT;
}
}
reg = *(uint64_t *)buf;
/*
* Convert to little endian before sending to RShim. The
* receiving side should call le64toh() to convert it back.
*/
reg = htole64(reg);
rc = bd->write_rshim(bd, RSHIM_CHANNEL, data_addr, reg, RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("write_rshim error %d\n", rc);
break;
}
byte_cnt += sizeof(reg);
if (buf == pad_buf)
break;
buf += sizeof(reg);
avail--;
}
/* Return number shouldn't count the padded bytes. */
done:
return (byte_cnt > count) ? count : byte_cnt;
}
static ssize_t rshim_write_default(rshim_backend_t *bd, int devtype,
const char *buf, size_t count)
{
int rc;
switch (devtype) {
case RSH_DEV_TYPE_TMFIFO:
if (bd->is_boot_open)
return count;
/* Set the flag so there is only one outstanding request. */
bd->spin_flags |= RSH_SFLG_WRITING;
/* Wake up the worker. */
bd->fifo_work_buf = (uint8_t *)buf;
bd->fifo_work_buf_len = count;
bd->fifo_work_devtype = devtype;
bd->has_fifo_work = 1;
rshim_work_signal(bd);
return 0;
case RSH_DEV_TYPE_BOOT:
bd->boot_work_buf_len = count;
bd->boot_work_buf_actual_len = 0;
bd->boot_work_buf = (uint8_t *)buf;
rshim_work_signal(bd);
rc = pthread_cond_wait(&bd->boot_write_complete_cond, &bd->mutex);
/* Cancel the request if interrupted. */
if (rc)
bd->boot_work_buf = NULL;
return bd->boot_work_buf_actual_len;
default:
RSHIM_ERR("bad devtype %d\n", devtype);
return -EINVAL;
}
}
/* Boot file operations routines */
/*
* Wait for boot to complete, if necessary. Return 0 if the boot is done
* and it's safe to continue, an error code if something went wrong. Note
* that this routine must be called with the device mutex held. If it
* returns successfully, the mutex will still be held (although it may have
* been dropped and reacquired); if it returns unsuccessfully the mutex
* will have been dropped.
*/
static int wait_for_boot_done(rshim_backend_t *bd)
{
struct timespec ts;
int rc;
if (!bd->has_reprobe || bd->skip_boot_reset) {
bd->is_booting = 0;
return 0;
}
clock_gettime(CLOCK_REALTIME, &ts);
ts.tv_sec += 20;
if (!bd->has_rshim || bd->is_booting) {
while (bd->is_booting) {
RSHIM_INFO("boot write, waiting for re-probe\n");
/*
* FIXME: might we want a timeout here, too? If the reprobe takes a very
* long time, something's probably wrong. Maybe a couple of minutes?
*/
rc = pthread_cond_timedwait(&bd->boot_complete_cond, &bd->mutex, &ts);
if (rc) {
RSHIM_DBG("Failed to detect re-probe, continues anyway.\n");
bd->is_booting = 0;
return 0;
}
/*
* On some systems the USB up event comes too early while the system
* is not fully ready yet. Add a delay here to avoid race codition.
*/
if (!bd->is_booting && bd->has_reprobe)
sleep(bd->reset_delay);
}
if (!bd->has_rshim)
return -ENODEV;
}
return 0;
}
static int rshim_reg_indirect_wait(rshim_backend_t *bd, uint64_t resp_count)
{
int rc, retries = 1000;
uint64_t count;
while (retries--) {
rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &count, RSHIM_REG_SIZE_8B);
if (rc)
return rc;
if (count != resp_count)
return 0;
}
RSHIM_DBG("Rshim byte access widget timeout\n");
return -1;
}
static int rshim_mmio_write_common(rshim_backend_t *bd, uintptr_t pa,
uint8_t size, uint64_t data)
{
uint64_t reg, resp_count;
bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, ®, RSHIM_REG_SIZE_8B);
reg |= 0x1ULL << bd->regs->device_mstr_priv_lvl_shift;
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, reg, RSHIM_REG_SIZE_8B);
bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &resp_count, RSHIM_REG_SIZE_8B);
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_data_first_word, data, RSHIM_REG_SIZE_8B);
reg = (((uint64_t)pa & RSH_MEM_ACC_CTL__ADDRESS_RMASK) <<
RSH_MEM_ACC_CTL__ADDRESS_SHIFT) |
(((uint64_t)size & RSH_MEM_ACC_CTL__SIZE_RMASK) <<
RSH_MEM_ACC_CTL__SIZE_SHIFT) |
(1ULL << RSH_MEM_ACC_CTL__WRITE_SHIFT) |
(1ULL << RSH_MEM_ACC_CTL__SEND_SHIFT);
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_ctl, reg, RSHIM_REG_SIZE_8B);
return rshim_reg_indirect_wait(bd, resp_count);
}
static int rshim_mmio_read_common(rshim_backend_t *bd, uintptr_t pa,
uint8_t size, uint64_t *data)
{
uint64_t reg, resp_count;
bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, ®, RSHIM_REG_SIZE_8B);
reg |= 0x1ULL << bd->regs->device_mstr_priv_lvl_shift;
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, reg, RSHIM_REG_SIZE_8B);
bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &resp_count, RSHIM_REG_SIZE_8B);
reg = (((uint64_t)pa & RSH_MEM_ACC_CTL__ADDRESS_RMASK) <<
RSH_MEM_ACC_CTL__ADDRESS_SHIFT) |
(((uint64_t)size & RSH_MEM_ACC_CTL__SIZE_RMASK) <<
RSH_MEM_ACC_CTL__SIZE_SHIFT) |
(1ULL << RSH_MEM_ACC_CTL__SEND_SHIFT);
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_ctl, reg, RSHIM_REG_SIZE_8B);
if (rshim_reg_indirect_wait(bd, resp_count))
return -1;
bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_data_first_word, ®, RSHIM_REG_SIZE_8B);
*data = reg;
return 0;
}
int rshim_mmio_write32(rshim_backend_t *bd, uintptr_t addr, uint32_t value)
{
return rshim_mmio_write_common(bd, addr, RSH_MEM_ACC_CTL__SIZE_VAL_SZ4,
value);
}
int rshim_mmio_read32(rshim_backend_t *bd, uintptr_t addr, uint32_t *data)
{
uint64_t reg;
if (rshim_mmio_read_common(bd, addr, RSH_MEM_ACC_CTL__SIZE_VAL_SZ4, ®)) {
return -1;
} else {
*data = (uint32_t)reg;
return 0;
}
}
static bool rshim_is_livefish(rshim_backend_t *bd)
{
uint32_t yu_boot = 0, boot_status;
int rc;
/* No need to check livefish mode for pcie rshim driver. */
if (!strncmp(bd->dev_name, "pcie", 4) && strncmp(bd->dev_name + 4, "-lf", 3))
return false;
/*
* A value of 1 in yu_boot.boot_status indicates a successful FW
* boot, any other value indicates livefish mode.
*/
rc = rshim_mmio_read32(bd, RSHIM_YU_BASE_ADDR + YU_BOOT, &yu_boot);
boot_status = (yu_boot >> 17) & 3;
RSHIM_DBG("yu_boot_status: %d\n", boot_status);
return (!rc && boot_status != 1);
}
/*
* Write to the RShim reset control register.
*/
int rshim_reset_control(rshim_backend_t *bd)
{
uint64_t reg, val;
uint8_t shift;
int rc;
rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control, ®, RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(reg)) {
RSHIM_ERR("failed to read rshim reset control error %d\n", rc);
return rc;
}
val = RSH_RESET_CONTROL__RESET_CHIP_VAL_KEY;
shift = RSH_RESET_CONTROL__RESET_CHIP_SHIFT;
reg &= ~((uint64_t) RSH_RESET_CONTROL__RESET_CHIP_MASK);
reg |= (val << shift);
/*
* The reset of the ARM can be blocked when the DISABLED bit
* is set. The big assumption is that the DISABLED bit would
* be hold high for a short period and only the platform code
* can reset that bit. Thus the ARM reset can be delayed and
* in theory this should not impact the behavior of the RShim
* driver.
*/
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control, reg, RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("failed to write rshim reset control error %d\n", rc);
return rc;
}
if (bd->ver_id == RSHIM_BLUEFIELD_2 && bd->rev_id == BLUEFIELD_REV0 &&
rshim_is_livefish(bd)) {
RSHIM_DBG("Apply reset type 13\n");
/* yu.reset_mode_control.reset_mode_control.sw_reset_event_activation13 */
rshim_mmio_write32(bd, RSHIM_YU_BASE_ADDR + YU_RESET_ACTIVATION_13, 1);
}
return 0;
}
int rshim_boot_open(rshim_backend_t *bd)
{
int rc;
pthread_mutex_lock(&bd->mutex);
if (bd->drop_mode) {
RSHIM_INFO("rshim is in drop mode\n");
pthread_mutex_unlock(&bd->mutex);
return -EINVAL;
}
if (bd->locked_mode) {
RSHIM_ERR("rshim is in locked mode\n");
pthread_mutex_unlock(&bd->mutex);
return -EPERM;
}
if (bd->is_boot_open) {
RSHIM_INFO("can't boot, boot file already open\n");
pthread_mutex_unlock(&bd->mutex);
return -EBUSY;
}
if (!bd->has_rshim) {
pthread_mutex_unlock(&bd->mutex);
return -ENODEV;
}
RSHIM_INFO("rshim%d boot open\n", bd->index);
bd->is_booting = 1;
bd->boot_rem_cnt = 0;
/*
* Before we reset the chip, make sure we don't have any
* outstanding writes, and flush the write and read FIFOs. (Note
* that we can't have any outstanding reads, since we kill those
* upon release of the TM FIFO file.)
*/
if (bd->cancel)
bd->cancel(bd, RSH_DEV_TYPE_TMFIFO, true);
/* Reset the TmFifo. */
rshim_fifo_reset(bd);
/* Set RShim (external) boot mode. */
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control,
RSH_BOOT_CONTROL__BOOT_MODE_VAL_NONE, RSHIM_REG_SIZE_8B);
if (rc) {
RSHIM_ERR("boot_open: error %d writing boot control\n", rc);
bd->is_booting = 0;
pthread_mutex_unlock(&bd->mutex);
return rc;
}
bd->is_boot_open = 1;
/*
* Disable the watchdog. The channel and offset are the same on all
* the BlueField SoC so far.
*/
bd->write_rshim(bd, RSH_MMIO_ADDRESS_SPACE__CHANNEL_VAL_WDOG1,
bd->regs->arm_wdg_control_wcs, 0, RSHIM_REG_SIZE_8B);
if (bd->skip_boot_reset)
goto boot_open_done;
/* SW reset. */
rc = rshim_reset_control(bd);
/*
* Note that occasionally, we get various errors on writing to
* the reset register. This appears to be caused by the chip
* actually resetting before the response goes out, or perhaps by
* our noticing the device unplug before we've seen the response.
* Either way, the chip _does_ actually reset, so we just ignore
* the error. Should we ever start getting these errors without
* the chip being reset, we'll have to figure out how to handle
* this more intelligently. (One potential option is to not reset
* directly, but to set up a down counter to do the reset, but that
* seems kind of kludgy, especially since Tile software might also
* be trying to use the down counter.)
*/
if (rc && rc != -EPROTO && rc != -ESHUTDOWN &&
rc != -ETIMEDOUT && rc != -EPIPE) {
RSHIM_ERR("boot_open: error %d writing reset control\n", rc);
bd->is_boot_open = 0;
pthread_mutex_unlock(&bd->mutex);
return rc;
}
if (rc)
RSHIM_ERR("boot_open: got error %d on reset write\n", rc);
boot_open_done:
rshim_ref(bd);
/* Add a small delay for the reset. */
if (!bd->has_reprobe)
usleep(500000);
pthread_mutex_unlock(&bd->mutex);
if (!bd->has_reprobe)
sleep(bd->reset_delay);
time(&bd->boot_write_time);
return 0;
}
int rshim_boot_write(rshim_backend_t *bd, const char *user_buffer, size_t count,
int (*copy_in)(void *dest, const void *src, int count))
{
int rc = 0, whichbuf = 0, len;
time_t tm;
size_t bytes_written = 0;
pthread_mutex_lock(&bd->mutex);
if (bd->is_in_boot_write) {
pthread_mutex_unlock(&bd->mutex);
return -EBUSY;
}
rc = wait_for_boot_done(bd);
if (rc) {
RSHIM_ERR("boot_write: wait for boot failed, err %d\n", rc);
pthread_mutex_unlock(&bd->mutex);
return rc;
}
/*
* We're going to drop the mutex while we wait for any outstanding
* write to complete; this keeps another thread from getting in here
* while we do that.
*/
bd->is_in_boot_write = 1;
while (count + bd->boot_rem_cnt >= sizeof(uint64_t)) {
size_t buf_bytes = MIN(BOOT_BUF_SIZE,
(count + bd->boot_rem_cnt) & (-((size_t)8)));
char *buf = bd->boot_buf[whichbuf];
whichbuf ^= 1;
/* Copy the previous remaining data first. */
if (bd->boot_rem_cnt)
memcpy(buf, &bd->boot_rem_data, bd->boot_rem_cnt);
rc = copy_in(buf + bd->boot_rem_cnt, user_buffer,
buf_bytes - bd->boot_rem_cnt);
if (rc < 0)
break;
rc = bd->write(bd, RSH_DEV_TYPE_BOOT, buf, buf_bytes);
if (rc > bd->boot_rem_cnt) {
len = rc - bd->boot_rem_cnt;
count -= len;
user_buffer += len;
bytes_written += len;
bd->boot_rem_cnt = 0;
} else if (rc == 0) {
time(&tm);
if (difftime(tm, bd->boot_write_time) > bd->boot_timeout) {
rc = -ETIMEDOUT;
RSHIM_INFO("rshim%d boot timeout\n", bd->index);
} else {
rc = -EINTR;
}
break;
}
time(&bd->boot_write_time);
if (rc != buf_bytes)
break;
}
/* Buffer the remaining data. */
if (count + bd->boot_rem_cnt < sizeof(bd->boot_rem_data)) {
rc = copy_in((uint8_t *)&bd->boot_rem_data + bd->boot_rem_cnt,
user_buffer, count);
bd->boot_rem_cnt += count;
bytes_written += count;
}
bd->is_in_boot_write = 0;
pthread_mutex_unlock(&bd->mutex);
if (bytes_written > 0 || count == 0)
return bytes_written;
else
return rc;
}
void rshim_boot_release(rshim_backend_t *bd)
{
int rc;
pthread_mutex_lock(&bd->mutex);
/* Restore the boot mode register. */
rc = bd->write_rshim(bd, RSHIM_CHANNEL,
bd->regs->boot_control,
RSH_BOOT_CONTROL__BOOT_MODE_VAL_EMMC,
RSHIM_REG_SIZE_8B);
if (rc)
RSHIM_ERR("couldn't set boot_control, err %d\n", rc);
/* Flush the leftover data with zeros padded. */
if (bd->boot_rem_cnt) {
memset((uint8_t *)&bd->boot_rem_data + bd->boot_rem_cnt, 0,
sizeof(uint64_t) - bd->boot_rem_cnt);
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_fifo_data,
bd->boot_rem_data, RSHIM_REG_SIZE_8B);
}
bd->is_boot_open = 0;
bd->boot_rem_cnt = 0;
rshim_work_signal(bd);
pthread_mutex_unlock(&bd->mutex);
RSHIM_INFO("rshim%d boot close\n", bd->index);
rshim_deref(bd);
}
/* FIFO common routines */
/*
* Signal an error on the FIFO, and wake up anyone who might need to know
* about it.
*/
static void rshim_fifo_err(rshim_backend_t *bd, int err)
{
int i;
bd->tmfifo_error = err;
pthread_cond_broadcast(&bd->fifo_write_complete_cond);
for (i = 0; i < TMFIFO_MAX_CHAN; i++) {
pthread_cond_broadcast(&bd->read_fifo[i].operable);
pthread_cond_broadcast(&bd->write_fifo[i].operable);
}
}
static int rshim_fifo_tx_avail(rshim_backend_t *bd)
{
uint64_t word;
int rc, max_size, avail;
/* Get FIFO max size. */
max_size = RSH_TM_FIFO_SIZE;
/* Calculate available size. */
rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_htt_sts, &word, RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(word)) {
RSHIM_ERR("rshim%d read_rshim error %d\n", bd->index, rc);
usleep(10000);
return -1;
}
avail = max_size - (int)(word & RSH_TM_HOST_TO_TILE_STS__COUNT_MASK) -
RSHIM_FIFO_SPACE_RESERV;
return avail;
}
int rshim_fifo_sync(rshim_backend_t *bd, bool drop_rx)
{
rshim_tmfifo_msg_hdr_t hdr;
int i, avail, rc;
time_t t0, t1;
uint64_t reg;
/* Clear pending network Rx/Tx state. */
bd->net_rx_len = 0;
bd->net_tx_len = 0;
/* Sync the Tx FIFO by sending padding zeros. */
avail = rshim_fifo_tx_avail(bd);
if (avail < 0)
return avail;
hdr.data = 0;
hdr.type = VIRTIO_ID_NET;
rshim_fifo_msg_update_checksum(&hdr);
for (i = 0; i < avail; i++) {
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_htt_data,
hdr.data, RSHIM_REG_SIZE_8B);
if (rc)
return rc;
}
/* Drain the Rx FIFO until no more data in one second. */
if (drop_rx) {
avail = 0;
time(&t0);
do {
reg = 0;
rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_sts, ®, RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(reg))
break;
avail = reg & RSH_TM_TILE_TO_HOST_STS__COUNT_MASK;
if (avail == 0) {