forked from MiSTer-devel/Minimig-AGA_MiSTer
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files.qip
26 lines (26 loc) · 1.44 KB
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files.qip
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set_global_assignment -name QIP_FILE rtl/tg68k/TG68K.qip
set_global_assignment -name QIP_FILE rtl/fx68k/fx68k.qip
set_global_assignment -name QIP_FILE rtl/ram.qip
set_global_assignment -name QIP_FILE rtl/agnus.qip
set_global_assignment -name QIP_FILE rtl/cia.qip
set_global_assignment -name QIP_FILE rtl/gayle.qip
set_global_assignment -name QIP_FILE rtl/paula.qip
set_global_assignment -name QIP_FILE rtl/denise.qip
set_global_assignment -name QIP_FILE rtl/fpga-toccata/toccata.qip
set_global_assignment -name VERILOG_FILE rtl/gary.v
set_global_assignment -name VERILOG_FILE rtl/rtg.v
set_global_assignment -name VERILOG_FILE rtl/akiko.v
set_global_assignment -name VERILOG_FILE rtl/fastchip.v
set_global_assignment -name VERILOG_FILE rtl/userio.v
set_global_assignment -name VERILOG_FILE rtl/cart.v
set_global_assignment -name VERILOG_FILE rtl/amiga_clk.v
set_global_assignment -name VERILOG_FILE rtl/minimig_syscontrol.v
set_global_assignment -name VERILOG_FILE rtl/minimig_sram_bridge.v
set_global_assignment -name VERILOG_FILE rtl/minimig_m68k_bridge.v
set_global_assignment -name VERILOG_FILE rtl/minimig_bankmapper.v
set_global_assignment -name VERILOG_FILE rtl/minimig.v
set_global_assignment -name VERILOG_FILE rtl/cpu_wrapper.v
set_global_assignment -name VERILOG_FILE hps_ext.v
set_global_assignment -name VERILOG_FILE rtl/cdda.v
set_global_assignment -name SDC_FILE Minimig.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Minimig.sv