SMS Core Fails "X-Scroll Latchtime" Test

[ajgowans]

The SMS core fails the "X-Scroll Latchtime" test in the attached VDPTEST rom. You can compare to the same test run on a PAL SMS2, also attached.

I have attached the full test results for the MiSTer and PAL SMS2, and also the Mega SG which may be of interest.

VDPTEST.sms.zip
SMS Test Mega SG (15-Oct-2021).zip
SMS Test PAL MS2 (15-Oct-2021).zip
SMS Test MiSTer (29-Sep-2021).zip

[dentnz]

Found the source code for the VDP test rom here: https://www.smspower.org/Homebrew/SMSVDPTest-SMS

Zip contains source.

[dentnz]

Importantly: XScroll is latched between HClock -18 & -17 (HCount 0xF3), HClock -15 & -14 (HCount 0xF5 & 0xF6) on MD.

[birdybro]

https://github.com/MiSTer-devel/SMS_MiSTer/blob/master/rtl/vdp.vhd#L404

Maybe this is the source of the issue?

https://www.intel.com/content/www/us/en/docs/programmable/683082/22-1/recommended-clock-gating-methods.html

To generate a gated clock with the recommended technique, use a register that triggers on the inactive edge of the clock. With this configuration, only one input of the gate changes at a time, preventing glitches or spikes on the output. If the clock is active on the rising edge, use an AND gate. Conversely, for a clock that is active on the falling edge, use an OR gate to gate the clock and register

I'll test and see...