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ksz_ptp_9897.c
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ksz_ptp_9897.c
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/**
* Microchip PTP common code
*
* Copyright (c) 2015-2018 Microchip Technology Inc.
* Tristram Ha <Tristram.Ha@microchip.com>
*
* Copyright (c) 2009-2015 Micrel, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define CURRENT_UTC_OFFSET 37 /* 1 Jan 2017 */
#if 0
#define NO_PPS_DETECT
#endif
#if 0
#define DBG_MSG_DROP
#endif
static int mhz_gpo;
static int pps_gpo = DEFAULT_PPS_GPO + 1;
#define FMT_NSEC_SIZE 12
static char *format_nsec(char *str, u32 nsec)
{
u32 nsec0;
u32 nsec1;
u32 nsec2;
char str0[4];
nsec0 = nsec % 1000;
nsec1 = (nsec / 1000) % 1000;
nsec2 = (nsec / 1000000) % 1000;
sprintf(str0, "%03u", nsec0);
if (nsec2)
sprintf(str, "%3u.%03u.%s", nsec2, nsec1, str0);
else if (nsec1)
sprintf(str, " %3u.%s", nsec1, str0);
else
sprintf(str, " %3u", nsec0);
return str;
} /* format_nsec */
struct pseudo_iphdr {
__u8 ttl;
__u8 protocol;
__be16 tot_len;
__be32 saddr;
__be32 daddr;
};
struct pseudo_ip6hdr {
__be16 payload_len;
__u8 hop_limit;
__u8 nexthdr;
struct in6_addr saddr;
struct in6_addr daddr;
};
static u32 timestamp_val(u32 timestamp, u8 *sec)
{
*sec = timestamp >> 30;
timestamp <<= 2;
timestamp >>= 2;
return timestamp;
} /* timestamp_val */
static void calc_diff(struct ksz_ptp_time *prev, struct ksz_ptp_time *cur,
struct ksz_ptp_time *result)
{
struct ksz_ptp_time diff;
int prev_nsec = prev->nsec;
int cur_nsec = cur->nsec;
if (prev->sec < 0)
prev_nsec = -prev_nsec;
if (cur->sec < 0)
cur_nsec = -cur_nsec;
diff.sec = cur->sec - prev->sec;
diff.nsec = cur_nsec - prev_nsec;
if (diff.nsec >= NANOSEC_IN_SEC) {
diff.nsec -= NANOSEC_IN_SEC;
diff.sec++;
} else if (diff.nsec <= -NANOSEC_IN_SEC) {
diff.nsec += NANOSEC_IN_SEC;
diff.sec--;
}
if (diff.sec > 0 && diff.nsec < 0) {
diff.nsec += NANOSEC_IN_SEC;
diff.sec--;
} else if (diff.sec < 0 && diff.nsec > 0) {
diff.nsec -= NANOSEC_IN_SEC;
diff.sec++;
}
if (diff.nsec < 0 && diff.sec < 0)
diff.nsec = -diff.nsec;
result->sec = diff.sec;
result->nsec = diff.nsec;
} /* calc_diff */
static void calc_udiff(struct ptp_utime *prev, struct ptp_utime *cur,
struct ksz_ptp_time *result)
{
struct ksz_ptp_time t1;
struct ksz_ptp_time t2;
if (prev->sec > (1UL << 31) || cur->sec > (1UL << 31)) {
s64 t3;
s64 t4;
s64 diff;
s32 rem;
t3 = (u64) prev->sec * NANOSEC_IN_SEC + prev->nsec;
t4 = (u64) cur->sec * NANOSEC_IN_SEC + cur->nsec;
diff = t4 - t3;
t3 = div_s64_rem(diff, NSEC_PER_SEC, &rem);
result->sec = (s32) t3;
result->nsec = rem;
return;
}
t1.sec = prev->sec;
t1.nsec = prev->nsec;
t2.sec = cur->sec;
t2.nsec = cur->nsec;
calc_diff(&t1, &t2, result);
} /* calc_udiff */
static void ptp_write_index(struct ptp_info *ptp, int shift, u8 unit)
{
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
#ifndef USE_OLD_PTP_UNIT_INDEX
u32 index = sw->cached.ptp_unit_index;
index &= ~(PTP_UNIT_M << shift);
index |= (u32) unit << shift;
sw->cached.ptp_unit_index = index;
sw->reg->w32(sw, REG_PTP_UNIT_INDEX__4, index);
#else
sw->reg->w32(sw, REG_PTP_UNIT_INDEX__4, unit);
#endif
} /* ptp_write_index */
static void add_nsec(struct ptp_utime *t, u32 nsec)
{
t->nsec += nsec;
if (t->nsec >= NANOSEC_IN_SEC) {
t->nsec -= NANOSEC_IN_SEC;
t->sec++;
}
} /* add_nsec */
static void sub_nsec(struct ptp_utime *t, u32 nsec)
{
if (t->nsec < nsec) {
t->nsec += NANOSEC_IN_SEC;
t->sec--;
}
t->nsec -= nsec;
} /* sub_nsec */
static void update_ts(struct ptp_ts *ts, u32 cur_sec)
{
int sec;
u8 sec_chk;
ts->t.nsec = timestamp_val(ts->timestamp, &sec_chk);
if (ts->timestamp)
sec = (cur_sec - sec_chk) & 3;
else
sec = 0;
if (sec >= 2)
sec -= 4;
ts->t.sec = cur_sec - sec;
} /* update_ts */
#define INIT_NSEC 40
#define MIN_CYCLE_NSEC 8
#define MIN_GAP_NSEC 120
#define PULSE_NSEC 8
static int check_cascade(struct ptp_info *ptp, int first, int total,
u16 *repeat, u32 sec, u32 nsec)
{
struct ptp_output *cur;
struct ptp_output *next;
struct ptp_output *prev;
int diff;
int i;
int tso;
int min_cnt;
int cnt;
tso = first;
cur = &ptp->outputs[tso];
next = &ptp->outputs[first + total];
next->start = cur->start;
add_nsec(&next->start, cur->iterate);
for (i = 0; i < total; i++, tso++) {
cur = &ptp->outputs[tso];
cur->stop = cur->start;
add_nsec(&cur->stop, cur->len);
next = &ptp->outputs[tso + 1];
calc_udiff(&cur->stop, &next->start, &cur->gap);
if ((cur->gap.sec < 0 || (!cur->gap.sec && cur->gap.nsec < 0))
&& (i < total - 1 || 1 != *repeat)) {
dbg_msg("gap too small: %d=%d\n", i, cur->gap.nsec);
return 1;
}
}
if (1 == *repeat)
goto check_cascade_done;
min_cnt = *repeat;
tso = first + 1;
for (i = 1; i < total; i++, tso++) {
cur = &ptp->outputs[tso];
prev = &ptp->outputs[tso - 1];
if (cur->iterate < prev->iterate) {
diff = prev->iterate - cur->iterate;
cnt = prev->gap.nsec / diff + 1;
} else if (cur->iterate > prev->iterate) {
diff = cur->iterate - prev->iterate;
cnt = cur->gap.nsec / diff + 1;
} else
cnt = *repeat;
if (min_cnt > cnt)
min_cnt = cnt;
}
if (*repeat > min_cnt)
*repeat = min_cnt;
prev = &ptp->outputs[first + tso];
for (cnt = 0; cnt < *repeat; cnt++) {
tso = first;
for (i = 0; i < total; i++, tso++) {
cur = &ptp->outputs[tso];
next = &ptp->outputs[tso + 1];
dbg_msg("%d: %d:%9d %d %d:%9d %d: %d:%9d\n",
i, cur->start.sec, cur->start.nsec, cur->len,
cur->gap.sec, cur->gap.nsec, cur->iterate,
cur->stop.sec, cur->stop.nsec);
if (cur->stop.sec > next->start.sec ||
(cur->stop.sec == next->start.sec &&
cur->stop.nsec > next->stop.nsec))
dbg_msg("> %d %d:%9d %d:%9d\n", i,
cur->stop.sec, cur->stop.nsec,
next->start.sec, next->start.nsec);
add_nsec(&cur->start, cur->iterate);
cur->stop = cur->start;
add_nsec(&cur->stop, cur->len);
if (!i)
prev->start = cur->start;
}
dbg_msg("%d:%9d\n", prev->start.sec, prev->start.nsec);
}
check_cascade_done:
tso = first;
cur = &ptp->outputs[tso];
if (cur->trig.sec >= sec)
return 0;
for (i = 0; i < total; i++, tso++) {
cur = &ptp->outputs[tso];
cur->trig.sec += sec;
add_nsec(&cur->trig, nsec);
}
return 0;
}
#define MAX_DRIFT_CORR 6250000
#define LOW_DRIFT_CORR 2499981
#define MAX_U32_S 32
#define MAX_DIVIDER_S 31
static u32 drift_in_sec(u32 abs_offset, u64 interval64)
{
u64 drift64;
drift64 = abs_offset;
drift64 *= NANOSEC_IN_SEC;
drift64 = div64_u64(drift64, interval64);
return (u32) drift64;
}
static u32 clk_adjust_val(int diff, u32 interval)
{
u32 adjust;
u32 rem;
u64 adjust64;
if (0 == diff)
return 0;
if (diff < 0)
adjust = -diff;
else
adjust = diff;
/* 2^32 * adjust * 1000000000 / interval / 25000000 */
if (interval != NANOSEC_IN_SEC)
adjust = drift_in_sec(adjust, interval);
if (adjust >= MAX_DRIFT_CORR)
adjust = 0x3fffffff;
else {
adjust64 = 1LL << 32;
adjust64 *= adjust;
adjust64 = div_u64_rem(adjust64, 25000000, &rem);
adjust = (u32) adjust64;
if (adjust >= 0x40000000)
adjust = 0x3fffffff;
}
if (diff < 0)
adjust |= PTP_RATE_DIR;
return adjust;
} /* clk_adjust_val */
static void ptp_tso_off(struct ptp_info *ptp, u8 tso, u16 tso_bit)
{
ptp->reg->tx_off(ptp, tso);
ptp->tso_intr &= ~tso_bit;
ptp->tso_used &= ~tso_bit;
if (ptp->tso_sys & tso_bit) {
printk(KERN_INFO "tso %d off!\n", tso);
ptp->tso_sys &= ~tso_bit;
}
ptp->tso_dev[tso] = NULL;
} /* ptp_tso_off */
static inline void ptp_tx_reset(struct ptp_info *ptp, u8 tso, u32 *ctrl_ptr)
{
u32 ctrl;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
if (!ctrl_ptr) {
ctrl_ptr = &ctrl;
ptp_write_index(ptp, PTP_TOU_INDEX_S, tso);
*ctrl_ptr = sw->reg->r32(sw, REG_PTP_CTRL_STAT__4);
}
*ctrl_ptr &= ~TS_RESET;
*ctrl_ptr |= TRIG_RESET;
sw->reg->w32(sw, REG_PTP_CTRL_STAT__4, *ctrl_ptr);
*ctrl_ptr &= ~TRIG_RESET;
sw->reg->w32(sw, REG_PTP_CTRL_STAT__4, *ctrl_ptr);
} /* ptp_tx_reset */
static inline void ptp_gpo_reset(struct ptp_info *ptp, int gpo, u8 tso,
u32 *ctrl_ptr)
{
ptp_tx_reset(ptp, tso, ctrl_ptr);
ptp->cascade_gpo[gpo].tso &= ~(1 << tso);
} /* ptp_gpo_reset */
/* -------------------------------------------------------------------------- */
static void ptp_acquire(struct ptp_info *ptp)
{
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
sw->ops->acquire(sw);
} /* ptp_acquire */
static void ptp_release(struct ptp_info *ptp)
{
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
sw->ops->release(sw);
} /* ptp_release */
static void get_ptp_time(struct ptp_info *ptp, struct ptp_utime *t)
{
u16 data;
u16 subnsec;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
data = sw->cached.ptp_clk_ctrl;
data |= PTP_READ_TIME;
sw_w16(sw, REG_PTP_CLK_CTRL, data);
do {
u8 buf[12];
u16 *w_ptr;
u32 *d_ptr;
sw_r(sw, REG_PTP_RTC_SUB_NANOSEC__2, buf, 10);
w_ptr = (u16 *) buf;
subnsec = be16_to_cpu(*w_ptr);
++w_ptr;
d_ptr = (u32 *) w_ptr;
t->nsec = be32_to_cpu(*d_ptr);
++d_ptr;
t->sec = be32_to_cpu(*d_ptr);
} while (0);
#if 1
if (subnsec > PTP_RTC_SUB_NANOSEC_M)
printk(" ?%x ", subnsec);
#endif
subnsec &= PTP_RTC_SUB_NANOSEC_M;
add_nsec(t, subnsec * 8);
} /* get_ptp_time */
static void set_ptp_time(struct ptp_info *ptp, struct ptp_utime *t)
{
u16 data;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
data = sw->cached.ptp_clk_ctrl;
sw_w16(sw, REG_PTP_RTC_SUB_NANOSEC__2, 0);
sw_w32(sw, REG_PTP_RTC_NANOSEC, t->nsec);
sw_w32(sw, REG_PTP_RTC_SEC, t->sec);
data |= PTP_LOAD_TIME;
sw_w16(sw, REG_PTP_CLK_CTRL, data);
} /* set_ptp_time */
static void adjust_ptp_time(struct ptp_info *ptp, int add, u32 sec, u32 nsec,
int adj_hack)
{
u16 ctrl;
u16 adj = 0;
u32 val = nsec;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ctrl = sw->cached.ptp_clk_ctrl;
if (add)
ctrl |= PTP_STEP_DIR;
else
ctrl &= ~PTP_STEP_DIR;
sw->cached.ptp_clk_ctrl = ctrl;
if (adj_hack) {
adj = ctrl;
ctrl &= ~PTP_CLK_ADJ_ENABLE;
}
ctrl |= PTP_STEP_ADJ;
sw_w32(sw, REG_PTP_RTC_SEC, sec);
do {
if (nsec > NANOSEC_IN_SEC - 1)
nsec = NANOSEC_IN_SEC - 1;
sw_w32(sw, REG_PTP_RTC_NANOSEC, nsec);
sw_w16(sw, REG_PTP_CLK_CTRL, ctrl);
val -= nsec;
nsec = val;
} while (val);
if (adj_hack && (adj & PTP_CLK_ADJ_ENABLE))
sw_w16(sw, REG_PTP_CLK_CTRL, adj);
} /* adjust_ptp_time */
static void adjust_sync_time(struct ptp_info *ptp, int diff, u32 interval,
u32 duration)
{
u32 adjust;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
adjust = clk_adjust_val(diff, interval);
adjust |= PTP_TMP_RATE_ENABLE;
sw_w32(sw, REG_PTP_RATE_DURATION, duration);
sw_w32(sw, REG_PTP_SUBNANOSEC_RATE, adjust);
} /* adjust_sync_time */
static void ptp_rx_reset(struct ptp_info *ptp, u8 tsi, u32 *ctrl_ptr)
{
u32 ctrl;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
if (!ctrl_ptr) {
ctrl_ptr = &ctrl;
ptp_write_index(ptp, PTP_TSI_INDEX_S, tsi);
*ctrl_ptr = sw->reg->r32(sw, REG_PTP_CTRL_STAT__4);
}
*ctrl_ptr &= ~TRIG_RESET;
*ctrl_ptr |= TS_RESET;
sw->reg->w32(sw, REG_PTP_CTRL_STAT__4, *ctrl_ptr);
*ctrl_ptr &= ~TS_RESET;
sw->reg->w32(sw, REG_PTP_CTRL_STAT__4, *ctrl_ptr);
} /* ptp_rx_reset */
static void ptp_rx_off(struct ptp_info *ptp, u8 tsi)
{
u32 ctrl;
u16 tsi_bit = (1 << tsi);
u32 ts_intr = 0;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ptp_write_index(ptp, PTP_TSI_INDEX_S, tsi);
ctrl = sw_r32(sw, REG_PTP_CTRL_STAT__4);
ctrl &= ~(TRIG_RESET | TS_RESET);
/* Disable previous timestamp interrupt. */
if (ptp->ts_intr & tsi_bit) {
ptp->ts_intr &= ~tsi_bit;
ctrl &= ~TS_INT_ENABLE;
ts_intr = tsi_bit;
}
/* Disable previous timestamp detection. */
ctrl &= ~TS_ENABLE;
sw_w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
/*
* Need to turn off cascade mode if it is used previously; otherwise,
* event counter keeps increasing.
*/
if (ptp->cascade_rx & tsi_bit) {
ptp_rx_reset(ptp, tsi, &ctrl);
sw_w32(sw, REG_TS_CTRL_STAT__4, 0);
ptp->cascade_rx &= ~tsi_bit;
}
if (ts_intr)
sw_w32(sw, REG_PTP_INT_STATUS__4, ts_intr);
} /* ptp_rx_off */
static inline void ptp_rx_intr(struct ptp_info *ptp, u16 tsi_bit, u32 *ctrl)
{
ptp->ts_intr |= tsi_bit;
*ctrl |= TS_INT_ENABLE;
} /* ptp_rx_intr */
static inline void ptp_rx_on(struct ptp_info *ptp, u8 tsi, int intr)
{
u32 ctrl;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ctrl = sw->reg->r32(sw, REG_PTP_CTRL_STAT__4);
ctrl &= ~(TRIG_RESET | TS_RESET);
/* Enable timestamp interrupt. */
if (intr)
ptp_rx_intr(ptp, (1 << tsi), &ctrl);
ctrl |= TS_ENABLE;
sw->reg->w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
} /* ptp_rx_on */
static void ptp_rx_restart(struct ptp_info *ptp, u8 tsi)
{
u32 ctrl;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ptp_write_index(ptp, PTP_TSI_INDEX_S, tsi);
ctrl = sw_r32(sw, REG_PTP_CTRL_STAT__4);
ctrl &= ~(TRIG_RESET | TS_RESET);
ctrl &= ~TS_ENABLE;
sw_w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
ctrl |= TS_ENABLE;
sw_w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
} /* ptp_rx_restart */
static u32 ts_event_gpi(u8 gpi, u8 event)
{
u32 ctrl;
u32 data;
ctrl = event;
ctrl <<= TS_DETECT_S;
data = gpi & TS_GPI_M;
data <<= TS_GPI_S;
ctrl |= data;
return ctrl;
}
static u32 ts_cascade(int prev)
{
u32 ctrl;
ctrl = prev & TS_CASCADE_UPS_M;
ctrl <<= TS_CASCADE_UPS_S;
ctrl |= TS_CASCADE_ENABLE;
return ctrl;
}
static void ptp_rx_event(struct ptp_info *ptp, u8 tsi, u8 gpi, u8 event,
int intr)
{
u32 ctrl;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
/* Config pattern. */
ptp_write_index(ptp, PTP_TSI_INDEX_S, tsi);
ctrl = ts_event_gpi(gpi, event);
sw_w32(sw, REG_TS_CTRL_STAT__4, ctrl);
/* Enable timestamp detection. */
ptp_rx_on(ptp, tsi, intr);
} /* ptp_rx_event */
static void ptp_rx_cascade_event(struct ptp_info *ptp, u8 first, u8 total,
u8 gpi, u8 event, int intr)
{
int last;
int tsi;
u32 ctrl;
u32 tail;
int i;
int prev;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
last = (first + total - 1) % MAX_TIMESTAMP_UNIT;
tsi = last;
tail = TS_CASCADE_TAIL;
for (i = 1; i < total; i++) {
ptp_write_index(ptp, PTP_TSI_INDEX_S, tsi);
prev = tsi - 1;
if (prev < 0)
prev = MAX_TIMESTAMP_UNIT - 1;
ctrl = ts_event_gpi(gpi, event);
ctrl |= ts_cascade(prev);
ctrl |= tail;
ptp->cascade_rx |= (1 << tsi);
sw_w32(sw, REG_TS_CTRL_STAT__4, ctrl);
/* Enable timestamp interrupt. */
if (intr) {
ctrl = sw_r32(sw, REG_PTP_CTRL_STAT__4);
ptp_rx_intr(ptp, (1 << tsi), &ctrl);
sw_w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
}
--tsi;
if (tsi < 0)
tsi = MAX_TIMESTAMP_UNIT - 1;
tail = 0;
}
ptp_write_index(ptp, PTP_TSI_INDEX_S, first);
ctrl = ts_event_gpi(gpi, event);
ctrl |= ts_cascade(last);
ptp->cascade_rx |= (1 << first);
sw_w32(sw, REG_TS_CTRL_STAT__4, ctrl);
/* Enable timestamp detection. */
ptp_rx_on(ptp, first, intr);
} /* ptp_rx_cascade_event */
static u32 ptp_get_event_cnt(struct ptp_info *ptp, u8 tsi, void *ptr)
{
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ptp_write_index(ptp, PTP_TSI_INDEX_S, tsi);
return sw_r32(sw, REG_TS_CTRL_STAT__4);
} /* ptp_get_event_cnt */
static void ptp_get_events(struct ptp_info *ptp, u32 reg_ns, size_t len,
void *buf, void *ptr)
{
int i;
u32 *data = buf;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
sw_r(sw, reg_ns, buf, len);
for (i = 0; i < len / sizeof(u32); i++)
data[i] = be32_to_cpu(data[i]);
} /* ptp_get_events */
static void ptp_read_event_func(struct ptp_info *ptp, u8 tsi, void *ptr,
u32 (*get_event_cnt)(struct ptp_info *ptp, u8 tsi, void *ptr),
void (*get_events)(struct ptp_info *ptp, u32 reg_ns, size_t len,
void *buf, void *ptr))
{
u32 ctrl;
u16 tsi_bit = (1 << tsi);
u8 buf[96];
u32 *d_ptr;
u32 reg_ns;
struct ptp_utime t;
u32 sub;
int max_ts;
int num;
int i;
int edge;
struct ptp_event *event = &ptp->events[tsi];
int last = event->num;
ctrl = get_event_cnt(ptp, tsi, ptr);
num = (ctrl >> TS_EVENT_DETECT_S) & TS_EVENT_DETECT_M;
max_ts = (num <= event->max) ? num : event->max;
if (event->num >= max_ts)
return;
i = event->num;
reg_ns = REG_TS_EVENT_0_NANOSEC + TS_EVENT_SAMPLE * i;
get_events(ptp, reg_ns, 12 * (max_ts - event->num), buf, ptr);
d_ptr = (u32 *) buf;
for (; i < max_ts; i++) {
t.nsec = (*d_ptr);
++d_ptr;
t.sec = (*d_ptr);
++d_ptr;
sub = (*d_ptr) & TS_EVENT_SUB_NANOSEC_M;
++d_ptr;
edge = ((t.nsec >> TS_EVENT_EDGE_S) & TS_EVENT_EDGE_M);
#if 0
printk("edge: %d=%x %x\n", i, event->event, edge);
#endif
t.nsec &= TS_EVENT_NANOSEC_M;
add_nsec(&t, sub * 8);
#if 1
/*
* THa 2011/10/06
* Unit sometimes detects rising edge when it is configured to detect falling
* edge only. This happens in the case of hooking up the output pin to an
* input pin and using two units running opposite cycle in cascade mode. The
* 8 ns switch pulse before the cycle is too short to detect properly,
* resulting in missing edges.
* When detecting events directly from the output pin, the minimum pulse time
* is 24 ns for proper detection without missing any edge.
*/
if (event->event < 2 && edge != event->event)
edge = event->event;
#endif
event->edge |= edge << i;
event->t[i] = t;
}
event->num = max_ts;
/* Indicate there is new event. */
if (event->num > last)
ptp->ts_status |= tsi_bit;
} /* ptp_read_event_func */
static void ptp_read_event(struct ptp_info *ptp, u8 tsi)
{
ptp_read_event_func(ptp, tsi, NULL, ptp_get_event_cnt,
ptp_get_events);
} /* ptp_read_event */
static u32 trig_cascade(int prev)
{
u32 ctrl;
ctrl = prev & TRIG_CASCADE_UPS_M;
ctrl <<= TRIG_CASCADE_UPS_S;
return ctrl;
}
static void ptp_tx_off(struct ptp_info *ptp, u8 tso)
{
u32 ctrl;
u16 tso_bit = (1 << tso);
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ptp_write_index(ptp, PTP_TOU_INDEX_S, tso);
/* Disable previous trigger out if not already completed. */
ctrl = sw_r32(sw, REG_PTP_CTRL_STAT__4);
ctrl &= ~(TRIG_RESET | TS_RESET);
if (ctrl & TRIG_ENABLE) {
ctrl &= ~TRIG_ENABLE;
sw_w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
}
/*
* Using cascade mode previously need to reset the trigger output so
* that an errorneous output will not be generated during next
* cascade mode setup.
*/
if (ptp->cascade_tx & tso_bit) {
ptp_gpo_reset(ptp, ptp->outputs[tso].gpo, tso, &ctrl);
ptp->cascade_tx &= ~tso_bit;
} else {
ctrl = sw_r32(sw, REG_TRIG_CTRL__4);
if (ctrl & TRIG_CASCADE_ENABLE) {
ctrl &= ~TRIG_CASCADE_ENABLE;
ctrl &= ~TRIG_CASCADE_TAIL;
ctrl |= trig_cascade(TRIG_CASCADE_UPS_M);
sw_w32(sw, REG_TRIG_CTRL__4, ctrl);
}
}
} /* ptp_tx_off */
static void ptp_tx_on(struct ptp_info *ptp, u8 tso)
{
u32 ctrl;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ctrl = sw->reg->r32(sw, REG_PTP_CTRL_STAT__4);
ctrl &= ~(TRIG_RESET | TS_RESET);
ctrl |= TRIG_ENABLE;
sw->reg->w32(sw, REG_PTP_CTRL_STAT__4, ctrl);
} /* ptp_tx_on */
static void ptp_tx_trigger_time(struct ptp_info *ptp, u8 tso, u32 sec, u32 nsec)
{
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
sw_w32(sw, REG_TRIG_TARGET_SEC, sec);
sw_w32(sw, REG_TRIG_TARGET_NANOSEC, nsec);
} /* ptp_tx_trigger_time */
static u32 trig_event_gpo(u8 gpo, u8 event)
{
u32 ctrl;
u32 data;
ctrl = event & TRIG_PATTERN_M;
ctrl <<= TRIG_PATTERN_S;
data = gpo & TRIG_GPO_M;
data <<= TRIG_GPO_S;
ctrl |= data;
return ctrl;
}
static void ptp_tx_event(struct ptp_info *ptp, u8 tso, u8 gpo, u8 event,
u32 pulse, u32 cycle, u16 cnt, u32 sec, u32 nsec, u32 iterate,
int intr, int now, int opt)
{
u32 ctrl;
u32 pattern = 0;
u16 tso_bit = (1 << tso);
struct ptp_output *cur = &ptp->outputs[tso];
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
/* Hardware immediately keeps level high on new GPIO if not reset. */
if (cur->level && gpo != cur->gpo)
ptp_gpo_reset(ptp, cur->gpo, tso, NULL);
ptp_write_index(ptp, PTP_TOU_INDEX_S, tso);
/* Config pattern. */
ctrl = trig_event_gpo(gpo, event);
if (intr)
ctrl |= TRIG_NOTIFY;
if (now)
ctrl |= TRIG_NOW;
if (opt)
ctrl |= TRIG_EDGE;
ctrl |= trig_cascade(TRIG_CASCADE_UPS_M);
sw_w32(sw, REG_TRIG_CTRL__4, ctrl);
/* Config pulse width. */
if (TRIG_REG_OUTPUT == event) {
pattern = pulse & TRIG_BIT_PATTERN_M;
cur->level = 0;
if (cnt) {
u32 reg;
reg = cnt - 1;
reg %= 16;
while (reg) {
pulse >>= 1;
reg--;
}
if (pulse & 1)
cur->level = 1;
}
pulse = 0;
} else if (event >= TRIG_NEG_PULSE) {
if (0 == pulse)
pulse = 1;
else if (pulse > TRIG_PULSE_WIDTH_M)
pulse = TRIG_PULSE_WIDTH_M;
sw_w24(sw, REG_TRIG_PULSE_WIDTH__4 + 1, pulse);
}
/* Config cycle width. */
if (event >= TRIG_NEG_PERIOD) {
u32 data = cnt;
int min_cycle = pulse * PULSE_NSEC + MIN_CYCLE_NSEC;
if (cycle < min_cycle)
cycle = min_cycle;
sw_w32(sw, REG_TRIG_CYCLE_WIDTH, cycle);
/* Config trigger count. */
data <<= TRIG_CYCLE_CNT_S;
pattern |= data;
sw_w32(sw, REG_TRIG_CYCLE_CNT, pattern);
}
cur->len = 0;
if (event >= TRIG_NEG_PERIOD) {
if (cnt)
cur->len += cycle * cnt;
else
cur->len += 0xF0000000;
} else if (event >= TRIG_NEG_PULSE)
cur->len += pulse * PULSE_NSEC;
else
cur->len += MIN_CYCLE_NSEC;
cur->start.sec = sec;
cur->start.nsec = nsec;
cur->iterate = iterate;
cur->trig = cur->start;
cur->stop = cur->start;
add_nsec(&cur->stop, cur->len);
cur->gpo = gpo;
switch (event) {
case TRIG_POS_EDGE:
case TRIG_NEG_PULSE:
case TRIG_NEG_PERIOD:
cur->level = 1;
break;
case TRIG_REG_OUTPUT:
break;
default:
cur->level = 0;
break;
}
if (ptp->cascade)
return;
/*
* Need to reset after completion. Otherwise, this output pattern
* does not behave consistently in cascade mode.
*/
if (TRIG_NEG_EDGE == event)
ptp->cascade_tx |= tso_bit;
ptp->cascade_gpo[gpo].total = 0;
if (cur->level)
ptp->cascade_gpo[gpo].tso |= tso_bit;
else
ptp->cascade_gpo[gpo].tso &= ~tso_bit;
/* Config trigger time. */
ptp_tx_trigger_time(ptp, tso, sec, nsec);
/* Enable trigger. */
ptp_tx_on(ptp, tso);
} /* ptp_tx_event */
static void ptp_pps_event(struct ptp_info *ptp, u8 gpo, u32 sec)
{
u32 pattern;
u32 ctrl;
u32 nsec;
u32 pulse = (20000000 / 8); /* 20 ms */
u32 cycle = 1000000000;
u16 cnt = 0;
u8 tso = ptp->pps_tso;
u8 event = TRIG_POS_PERIOD;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
ptp_tx_off(ptp, tso);
/* Config pattern. */
ctrl = trig_event_gpo(gpo, event);
ctrl |= TRIG_NOTIFY;
ctrl |= TRIG_NOW;
ctrl |= trig_cascade(TRIG_CASCADE_UPS_M);
sw_w32(sw, REG_TRIG_CTRL__4, ctrl);
/* Config pulse width. */
if (pulse > TRIG_PULSE_WIDTH_M)
pulse = TRIG_PULSE_WIDTH_M;
sw_w24(sw, REG_TRIG_PULSE_WIDTH__4 + 1, pulse);
/* Config cycle width. */
sw_w32(sw, REG_TRIG_CYCLE_WIDTH, cycle);
/* Config trigger count. */
pattern = cnt;
pattern <<= TRIG_CYCLE_CNT_S;
sw_w32(sw, REG_TRIG_CYCLE_CNT, pattern);
/* Config trigger time. */
if (ptp->pps_offset >= 0)
nsec = ptp->pps_offset;
else {
nsec = NANOSEC_IN_SEC + ptp->pps_offset;
sec--;
}
ptp_tx_trigger_time(ptp, tso, sec, nsec);
/* Enable trigger. */
ptp_tx_on(ptp, tso);
} /* ptp_pps_event */
static void cfg_10MHz(struct ptp_info *ptp, u8 tso, u8 gpo, u32 sec, u32 nsec)
{
u32 pattern;
u32 ctrl;
u32 pulse = 6;
u32 cycle = 200;
u16 cnt = 0;
u8 event = TRIG_POS_PERIOD;
struct ksz_sw *sw = container_of(ptp, struct ksz_sw, ptp_hw);
/* Config pattern. */
ctrl = trig_event_gpo(gpo, event);
ctrl |= TRIG_NOTIFY;
if (1 == tso)
ctrl |= TRIG_EDGE;
ctrl |= trig_cascade(TRIG_CASCADE_UPS_M);
sw_w32(sw, REG_TRIG_CTRL__4, ctrl);
/* Config pulse width. */
if (pulse > TRIG_PULSE_WIDTH_M)
pulse = TRIG_PULSE_WIDTH_M;
sw_w32(sw, REG_TRIG_PULSE_WIDTH__4 + 0, pulse);