The PLL interface is accessed at APB Base address 0x1a100000. Nine 32-bit registers are used to control the PLL and the clock divisors.
| OFFSET | Register | Description |
|---|---|---|
| 0x0 | CTL | PLL Configuutation Control |
| 0x4 | DIV | PLL Divisor Control |
| 0x8 | FRAC | PLL Fractional Control |
| 0xC | SS1 | PLL Spread Spectrum Control 1 |
| 0x10 | SS2 | PLL Spread Spectrum Control 2 |
| 0x14 | SOC | SOC Clock Divisor |
| 0x18 | PERIPH | Peripheral Clock Divisor |
| 0x1C | FPGA | FPGA Clock Divisor |
| 0x20 | REF | Reference Clock Divisor |
Default Value = 0x300103
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| LOCK | 31 | PLL Lock 1 = Locked, 0 = Not Locked | ||
| PDDP | 25 | RW | 1 | PLL Divisor Power Down 1=Power Down, 0=Normal Operation |
| PD | 24 | RW | 1 | PLL Power Down 1=Power Down, 0=Normal Operation |
| MODE | 17:16 | RW | 0 | MODE 0=Normal, 1=Fractional, 2=SpreadSpectrum, 3=Reserved |
| DM | 13:8 | RW | 1 | Reference Clock Divisor values = 1-63 |
| RESET | 1 | RW | 1 | PLL Reset 1 = Reset, 0 = Normal operation |
| BYPASS | 0 | RW | 1 | PLL/Divisor Bypass, 1 = all clocks are Reference Clock |
Default Value = 0xA00004
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| DN | 26:16 | RW | 0xa0 | PLL Feedback Divisor (0xa0 = PLL at 1.6GHz) |
| DP | 2:0 | RW | 0x4 | PLL Output Divisor (0x4 = 400MHz CLK0) |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| FRAC | 23:0 | RW | 0x00 | PLL Fractional part of DN |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| SRATE | 10:0 | RW | 0x00 | PLL Spread Spectrum Triangle modulation Frequency |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| SSLOPE | 23:0 | RW | 0x00 | PLL Spread Spectrum Step |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| S_DIV | 9:0 | RW | 0x00 | SOC clock Divisor 0,1 = 1 |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| P_DIV | 9:0 | RW | 0x00 | Peripheral clock Divisor 0,1 = 1 |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| F_DIV | 9:0 | RW | 0x00 | FPGA clock Divisor 0,1 = 1 |
Default Value = 0x0
| Field | Bits | Type | Default | Description |
|---|---|---|---|---|
| R_DIV | 9:0 | RW | 0x28 | Reference clock Divisor 0x28=250KHz Refclock |