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makefile
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makefile
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# Project makefile
# Toolchain options
# ============================================================================
# These options configure the compiler and linker
CFLAGS := -Wall -Wextra -ansi -g -MMD -D DEBUG_OUTPUT -D VERBOSE_OUTPUT
LDFLAGS := -lm
# Note that we're using -Wextra, this means that lots of warnings which aren't
# necessarily bad will show up, but before dismissing a warning, you should be
# sure it's really not important. They're there for a reason.
# File list generation
# ============================================================================
# Generates lists of all the C files that need to be compiled and generates
# thier object file counterparts.
SRCFILES := $(shell find . -name "*.c")
OBJFILES := $(SRCFILES:.c=.o)
# Recipes
# ============================================================================
# Default recipe, compiles the program
all: lqip
# Main recipe for the program, puts all the obejct files through the linker
# and adds any required libraries.
lqip: $(OBJFILES)
gcc $(LDFLAGS) $(OBJFILES) -o lqip
# Object file recipe, tells make how to compile the C sources into object
# files.
%.o: %.c
gcc $(CFLAGS) -c $< -o $@
# Cleaning recipie, removes all build files from the source directory, good
# for ensuring that evey file gets built from scratch to check for build
# errors.
clean:
rm -vf lqip
rm -vf *.o *.d
rm -vf placeholders.yaml placeholders.enc listing.txt
# PHONY recipes, these are the command-like targets, and will always be run.
.PHONY: all clean
# This disables the built-in rules that make uses to build files it already
# knows about.
.SUFFIXES:
# Include the header-generated dependencies
# These are generated by GCC's -MMD option, and will tell make about which
# headers are required by which source files.
include $(wildcard *.d)