/
emit_x64.dasc
2541 lines (2463 loc) · 82.2 KB
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emit_x64.dasc
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#include "moar.h"
#include <dasm_proto.h>
#include <dasm_x86.h>
#include "emit.h"
#ifdef _MSC_VER
#pragma warning( disable : 4129 )
#endif
/**
* CONVENTIONS
* Much of this file contains snippets of assembly code, which are concatenated
* at runtime in order to form a single executable routine. It is essential for
* the correctness of the result that each of the snippets behaves
* nicely. Because you can't be expected to know what that is, it is documented
* here.
* REGISTERS:
* Register and calling conventions differ between POSIX and windows
* systems. The registers rax, rcx, rdx, r8, r9, r10 and r11 are caller-saved,
* meaning that you are free to overwrrite them, and functions you may call are
* free to do thesame. Hence you should save their values on stack, if you wish
* to keep them after calling. In contrast, rbx, rsp, rbp, and r12-r15 are
* callee-saved, meaning that their values before entering and after returning
* from a function must be the same. POSIX also makes rdi and rsi caller-saved,
* windows makes them callee-saved. For this reason we avoid using them. The
* first 4 (windows) or 6 (POSIX) function call arguments are placed in
* registers. These registers sets are not the same between windows and POSIX,
* but they're always caller-saved.
* To deal with the ambiguity, register names have been aliased.
* + RV stands for 'return value', and is aliased to rax
* + TMP1-6 are the 6 shared caller-saved registers
* + ARG1-4 are (different) aliases for argument registers
* + TC, CU, WORK are registers that hold interpreter variables; these are callee-
* saved registers set up at entry and restored at exit
* + TMP5 (r10) is also aliased as FUNCTION; it never conflicts with an argument
* register, and neither does TMP6.
* + The suffixes d, w, and b stand for the 4, 2, and 1 byte-width value of the
* registers.
* Note that the current convention for function calls is to load the function
* pointer as a 64 bit value in a register from the machine code, and call on
* that register. This is not ideal, but call doesn't natively take 64 bit
* values, and it is neccesary to ensure that the function lives within 32 bits
* distance from the function otherwise. Other methods are being considered.
* LABELS:
* Don't use dynamic labels in this code, unless they have been passed to you
* from outside. Dynamic labels need to be allocated and not conflict, hence
* just picking one is typically unsafe. You are allowed to use in a snippet
* the local labels 1-5; the labels 6-9 are reserved by special constructs like
* THROWISH_PRE and INVOKISH.
* WRITE BARRIERS:
* Use of write barriers is tricky, because they may involve a function call, and
* that may or may not mean you have to store your temporaries on the stack.
* Hence, a write barrier (MVM_ASSIGN_REF) is split into two parts:
* + check_wb (root, value, label)
* + hit_wb (root)
* You should have the label parameter point somewhere after hit_wb, and save
* and restore your temporaries around the hib_wb.
**/
|.arch x64
|.actionlist actions
|.section code, data
|.globals MVM_JIT_LABEL_
/* type declarations */
|.type REGISTER, MVMRegister
|.type FRAME, MVMFrame
|.type ARGCTX, MVMArgProcContext
|.type CALLSITEPTR, MVMCallsite*
|.type CAPTURE, MVMCallCapture
|.type CAPTUREBODY, MVMCallCaptureBody
|.type ARGPROCCONTEXT, MVMArgProcContext
|.type STATICFRAME, MVMStaticFrame
|.type P6OPAQUE, MVMP6opaque
|.type P6OBODY, MVMP6opaqueBody
|.type MVMITER, MVMIter
|.type MVMINSTANCE, MVMInstance
|.type MVMACTIVEHANDLERS, MVMActiveHandler
|.type OBJECT, MVMObject
|.type STOOGE, MVMObjectStooge
|.type COLLECTABLE, MVMCollectable
|.type STABLE, MVMSTable
|.type REPR, MVMREPROps
|.type STRING, MVMString*
|.type OBJECTPTR, MVMObject*
|.type CONTAINERSPEC, MVMContainerSpec
|.type STORAGESPEC, MVMStorageSpec
|.type HLLCONFIG, MVMHLLConfig;
|.type SCREFBODY, MVMSerializationContextBody
|.type NFGSYNTH, MVMNFGSynthetic
|.type CODE, MVMCode
|.type U8, MVMuint8
|.type U16, MVMuint16
|.type U32, MVMuint32
|.type U64, MVMuint64
/* Static allocation of relevant types to registers. I pick
* callee-save registers for efficiency. It is likely we'll be calling
* quite a C functions, and this saves us the trouble of storing
* them. Moreover, C compilers preferentially do not use callee-saved
* registers, and so in most cases, these won't be touched at all. */
|.type TC, MVMThreadContext, r14
/* Alternative base pointer. I'll be using this often, so picking rbx
* here rather than the extended registers will lead to smaller
* bytecode */
|.type WORK, MVMRegister, rbx
|.type CU, MVMCompUnit, r13
const MVMint32 MVM_jit_support(void) {
#ifdef __i386__
/* Usually, this file should only be compiled only on a amd64
platform; but when compiling 'fat' or 'universal' binaries, we
may compile it for other platform. In this case we use the
runtime check to disable the JIT */
return 0;
#else
return 1;
#endif
}
const unsigned char * MVM_jit_actions(void) {
return actions;
}
const unsigned int MVM_jit_num_globals(void) {
return MVM_JIT_LABEL__MAX;
}
/* C Call argument registers */
|.if WIN32
|.define ARG1, rcx
|.define ARG2, rdx
|.define ARG3, r8
|.define ARG4, r9
|.else
|.define ARG1, rdi
|.define ARG2, rsi
|.define ARG3, rdx
|.define ARG4, rcx
|.define ARG5, r8
|.define ARG6, r9
|.endif
/* C call argument registers for floating point */
|.if WIN32
|.define ARG1F, xmm0
|.define ARG2F, xmm1
|.define ARG3F, xmm2
|.define ARG4F, xmm3
|.else
|.define ARG1F, xmm0
|.define ARG2F, xmm1
|.define ARG3F, xmm2
|.define ARG4F, xmm3
|.define ARG5F, xmm4
|.define ARG6F, xmm5
|.define ARG7F, xmm6
|.define ARG8F, xmm7
|.endif
/* Special register for the function to be invoked
* (chosen because it isn't involved in argument passing
* and volatile) */
|.define FUNCTION, r10
/* all-purpose temporary registers */
|.define TMP1, rcx
|.define TMP2, rdx
|.define TMP3, r8
|.define TMP4, r9
|.define TMP5, r10
|.define TMP6, r11
/* same, but 32 bits wide */
|.define TMP1d, ecx
|.define TMP2d, edx
|.define TMP3d, r8d
|.define TMP4d, r9d
|.define TMP5d, r10d
|.define TMP6d, r11d
/* and 16 bits wide */
|.define TMP1w, cx
|.define TMP2w, dx
|.define TMP3w, r8w
|.define TMP4w, r9w
|.define TMP5w, r10w
|.define TMP6w, r11w
/* and 8 bits for good measure */
|.define TMP1b, cl
|.define TMP2b, dl
|.define TMP3b, r8b
|.define TMP4b, r9b
|.define TMP5b, r10b
|.define TMP6b, r11b
/* return value */
|.define RV, rax
|.define RVd, eax
|.define RVF, xmm0
|.macro callp, funcptr
|.data
|5:
|.dword (MVMuint32)((uintptr_t)(funcptr)), (MVMuint32)((uintptr_t)(funcptr) >> 32);
|.code
| call qword [<5];
|.endmacro
|.macro check_wb, root, ref, lbl;
| test word COLLECTABLE:root->flags, MVM_CF_SECOND_GEN;
| jz lbl;
| test ref, ref;
| jz lbl;
| test word COLLECTABLE:ref->flags, MVM_CF_SECOND_GEN;
| jnz lbl;
|.endmacro;
|.macro hit_wb, obj
| mov ARG2, obj;
| mov ARG1, TC;
| callp &MVM_gc_write_barrier_hit;
|.endmacro
|.macro get_spesh_slot, reg, idx;
| mov reg, TC->cur_frame;
| mov reg, FRAME:reg->effective_spesh_slots;
| mov reg, OBJECTPTR:reg[idx];
|.endmacro
|.macro get_vmnull, reg
| mov reg, TC->instance;
| mov reg, MVMINSTANCE:reg->VMNull;
|.endmacro
|.macro get_cur_op, reg
| mov reg, TC->interp_cur_op
| mov reg, [reg]
|.endmacro
|.macro get_string, reg, idx
|| MVM_cu_ensure_string_decoded(tc, jg->sg->sf->body.cu, idx);
| mov reg, CU->body.strings;
| mov reg, STRING:reg[idx];
|.endmacro
|.macro is_type_object, reg
| test word OBJECT:reg->header.flags, MVM_CF_TYPE_OBJECT
|.endmacro
|.macro gc_sync_point
| cmp qword TC->gc_status, 0;
| je >1;
| mov ARG1, TC;
| callp &MVM_gc_enter_from_interrupt;
|1:
|.endmacro
|.macro throw_adhoc, msg
| mov ARG1, TC;
| mov64 ARG2, (uintptr_t)(msg);
| callp &MVM_exception_throw_adhoc;
|.endmacro
|.define FRAME_NR, dword [rbp-0x20]
/* A function prologue is always the same in x86 / x64, because
* we do not provide variable arguments, instead arguments are provided
* via a frame. All JIT entry points receive a prologue. */
void MVM_jit_emit_prologue(MVMThreadContext *tc, MVMJitGraph *jg,
dasm_State **Dst) {
|.code
/* Setup stack */
| push rbp; // nb, this aligns the stack to 16 bytes again
| mov rbp, rsp;
/* allocate stack space: 0x100 bytes = 256 bytes
*
* layout: [ a: 0x20 | b: 0x40 | c: 0xa0 | d: 0x20 ]
* a: space for 4 callee-save registers
* b: small scratch space
* c: space for stack arguments to c calls
* d: reserve space for GPR registers to c calls (win64) or more space for
* stack arguments (posix) */
| sub rsp, 0x100;
/* save callee-save registers */
| mov [rbp-0x8], TC;
| mov [rbp-0x10], CU;
| mov [rbp-0x18], WORK;
/* store the current frame number for cheap comparisons */
| mov TMP6d, dword TC:ARG1->current_frame_nr;
| mov FRAME_NR, TMP6d;
/* setup special frame variables */
| mov TC, ARG1;
| mov CU, ARG2;
| mov TMP6, TC->cur_frame;
| mov WORK, FRAME:TMP6->work;
/* ARG3 contains our 'entry label' */
| jmp ARG3
}
/* And a function epilogue is also always the same */
void MVM_jit_emit_epilogue(MVMThreadContext *tc, MVMJitGraph *jg,
dasm_State **Dst) {
| ->exit:
| mov RV, 0;
| ->out:
/* restore callee-save registers */
| mov TC, [rbp-0x8];
| mov CU, [rbp-0x10];
| mov WORK, [rbp-0x18];
/* Restore stack */
| mov rsp, rbp;
| pop rbp;
| ret;
}
static MVMuint64 try_emit_gen2_ref(MVMThreadContext *tc, MVMJitGraph *jg,
MVMObject *obj, MVMint16 reg,
dasm_State **Dst) {
if (!(obj->header.flags & MVM_CF_SECOND_GEN))
return 0;
| mov64 TMP1, (uintptr_t)obj;
| mov WORK[reg], TMP1;
return 1;
}
static MVMint64 fits_in_32_bit(MVMint64 number) {
/* Used to determine if a 64 bit integer can be safely used as a
* 32 bit constant for immediate mode access */
return (number >= INT32_MIN) && (number <= INT32_MAX);
}
/* compile per instruction, can't really do any better yet */
void MVM_jit_emit_primitive(MVMThreadContext *tc, MVMJitGraph *jg,
MVMJitPrimitive * prim, dasm_State **Dst) {
MVMSpeshIns *ins = prim->ins;
MVMuint16 op = ins->info->opcode;
MVM_jit_log(tc, "emit opcode: <%s>\n", ins->info->name);
/* Quite a few of these opcodes are copies. Ultimately, I want to
* move copies to their own node (MVMJitCopy or such), and reduce
* the number of copies (and thereby increase the efficiency), but
* currently that isn't really feasible. */
switch (op) {
case MVM_OP_const_i64_16:
case MVM_OP_const_i64_32: {
MVMint32 reg = ins->operands[0].reg.orig;
/* Upgrade to 64 bit */
MVMint64 val = (op == MVM_OP_const_i64_16 ? (MVMint64)ins->operands[1].lit_i16 :
(MVMint64)ins->operands[1].lit_i32);
| mov qword WORK[reg], val;
break;
}
case MVM_OP_const_i64: {
MVMint32 reg = ins->operands[0].reg.orig;
MVMint64 val = ins->operands[1].lit_i64;
| mov64 TMP1, val;
| mov WORK[reg], TMP1;
break;
}
case MVM_OP_const_n64: {
MVMint16 reg = ins->operands[0].reg.orig;
MVMint64 valbytes = ins->operands[1].lit_i64;
MVM_jit_log(tc, "store const %f\n", ins->operands[1].lit_n64);
| mov64 TMP1, valbytes;
| mov WORK[reg], TMP1;
break;
}
case MVM_OP_inf:
case MVM_OP_neginf:
case MVM_OP_nan: {
MVMint16 reg = ins->operands[0].reg.orig;
MVMRegister tmp;
if (op == MVM_OP_nan)
tmp.n64 = MVM_num_nan(tc);
else if (op == MVM_OP_inf)
tmp.n64 = MVM_num_posinf(tc);
else if (op == MVM_OP_neginf)
tmp.n64 = MVM_num_neginf(tc);
| mov64 TMP1, tmp.i64;
| mov WORK[reg], TMP1;
break;
}
case MVM_OP_const_s: {
MVMint16 reg = ins->operands[0].reg.orig;
MVMuint32 idx = ins->operands[1].lit_str_idx;
MVMStaticFrame *sf = jg->sg->sf;
MVMString * s = MVM_cu_string(tc, sf->body.cu, idx);
if (!try_emit_gen2_ref(tc, jg, (MVMObject*)s, reg, Dst)) {
| get_string TMP1, idx;
| mov WORK[reg], TMP1;
}
break;
}
case MVM_OP_null: {
MVMint16 reg = ins->operands[0].reg.orig;
| get_vmnull TMP1;
| mov WORK[reg], TMP1;
break;
}
case MVM_OP_getwhat:
case MVM_OP_getwho: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 obj = ins->operands[1].reg.orig;
| mov TMP1, WORK[obj];
| mov TMP1, OBJECT:TMP1->st;
if (op == MVM_OP_getwho) {
| mov TMP1, STABLE:TMP1->WHO;
| get_vmnull TMP2;
| test TMP1, TMP1;
| cmovz TMP1, TMP2;
} else {
| mov TMP1, STABLE:TMP1->WHAT;
}
| mov WORK[dst], TMP1;
break;
}
case MVM_OP_getlex:
case MVM_OP_sp_getlex_o:
case MVM_OP_sp_getlex_ins: {
MVMuint16 *lexical_types;
MVMStaticFrame * sf = jg->sg->sf;
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 idx = ins->operands[1].lex.idx;
MVMint16 out = ins->operands[1].lex.outers;
MVMint16 i;
| mov TMP6, TC->cur_frame;
for (i = 0; i < out; i++) {
/* I'm going to skip compiling the check whether the outer
* node really exists, because if the code has run N times
* correctly, then the outer frame must have existed then,
* and since this chain is static, it should still exist
* now. If it doesn't exist, that means we crash.
*
* NB: inlining /might/ make this all wrong! But, if that
* happens, the interpreter will panic even without JIT */
| mov TMP6, FRAME:TMP6->outer;
sf = sf->body.outer;
}
/* get array of lexicals */
| mov TMP5, FRAME:TMP6->env;
/* read value */
| mov TMP5, REGISTER:TMP5[idx];
/* it seems that if at runtime, if the outer frame has been inlined,
* this /could/ be wrong. But if that is so, the interpreted instruction
* would also be wrong, because it'd refer to the wrong lexical. */
lexical_types = (!out && jg->sg->lexical_types ?
jg->sg->lexical_types :
sf->body.lexical_types);
MVM_jit_log(tc, "Lexical type of register: %d\n", lexical_types[idx]);
if (lexical_types[idx] == MVM_reg_obj) {
MVM_jit_log(tc, "Emit lex vifivy check\n");
/* if it is zero, check if we need to auto-vivify */
| test TMP5, TMP5;
| jnz >1;
/* setup args */
| mov ARG1, TC;
| mov ARG2, TMP6;
| mov ARG3, idx;
| callp &MVM_frame_vivify_lexical;
/* use return value for the result */
| mov TMP5, RV;
|1:
}
/* store the value */
| mov WORK[dst], TMP5;
break;
}
case MVM_OP_sp_getlexvia_o:
case MVM_OP_sp_getlexvia_ins: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 idx = ins->operands[1].lit_ui16;
MVMint16 out = ins->operands[2].lit_ui16;
MVMint16 via = ins->operands[3].reg.orig;
MVMint16 i;
/* Resolve the frame. */
| mov TMP6, WORK[via];
| mov TMP6, CODE:TMP6->body.outer;
for (i = 1; i < out; i++) /* From 1 as we are already at outer */
| mov TMP6, FRAME:TMP6->outer;
/* get array of lexicals */
| mov TMP5, FRAME:TMP6->env;
/* read value */
| mov TMP5, REGISTER:TMP5[idx];
if (op == MVM_OP_sp_getlexvia_o) {
MVM_jit_log(tc, "Emit lex vifivy check for via code-ref lookup\n");
/* if it is zero, check if we need to auto-vivify */
| test TMP5, TMP5;
| jnz >1;
/* setup args */
| mov ARG1, TC;
| mov ARG2, TMP6;
| mov ARG3, idx;
| callp &MVM_frame_vivify_lexical;
/* use return value for the result */
| mov TMP5, RV;
|1:
}
/* store the value */
| mov WORK[dst], TMP5;
break;
}
case MVM_OP_getlex_no:
case MVM_OP_sp_getlex_no: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMuint32 idx = ins->operands[1].lit_str_idx;
| mov ARG1, TC;
| get_string ARG2, idx;
| mov ARG3, MVM_reg_obj;
| callp &MVM_frame_find_lexical_by_name;
| test RV, RV;
| jz >1;
| mov RV, [RV];
|1:
| mov WORK[dst], RV;
break;
}
case MVM_OP_bindlex: {
MVMuint16 *lexical_types;
MVMStaticFrame *sf = jg->sg->sf;
MVMint16 idx = ins->operands[0].lex.idx;
MVMint16 out = ins->operands[0].lex.outers;
MVMint16 src = ins->operands[1].reg.orig;
MVMint16 i;
| mov TMP1, TC->cur_frame;
for (i = 0; i < out; i++) {
| mov TMP1, FRAME:TMP1->outer;
sf = sf->body.outer;
}
lexical_types = (!out && jg->sg->lexical_types ?
jg->sg->lexical_types :
sf->body.lexical_types);
| mov TMP2, FRAME:TMP1->env;
| mov TMP3, WORK[src];
| mov REGISTER:TMP2[idx], TMP3;
if (lexical_types[idx] == MVM_reg_obj ||
lexical_types[idx] == MVM_reg_str) {
| check_wb TMP1, TMP3, >2;
| hit_wb TMP1;
|2:
}
break;
}
case MVM_OP_sp_getarg_o:
case MVM_OP_sp_getarg_n:
case MVM_OP_sp_getarg_s:
case MVM_OP_sp_getarg_i: {
MVMint32 reg = ins->operands[0].reg.orig;
MVMuint16 idx = ins->operands[1].callsite_idx;
| mov TMP1, TC->cur_frame;
| mov TMP1, FRAME:TMP1->params.args;
| mov TMP1, REGISTER:TMP1[idx];
| mov WORK[reg], TMP1;
break;
}
case MVM_OP_sp_p6oget_i:
case MVM_OP_sp_p6oget_n:
case MVM_OP_sp_p6oget_s:
case MVM_OP_sp_p6oget_o:
case MVM_OP_sp_p6ogetvc_o:
case MVM_OP_sp_p6ogetvt_o: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 obj = ins->operands[1].reg.orig;
MVMint16 offset = ins->operands[2].lit_i16;
MVMint16 body = offsetof(MVMP6opaque, body);
/* load address and object */
| mov TMP1, WORK[obj];
| lea TMP2, [TMP1 + (offset + body)];
| mov TMP4, P6OPAQUE:TMP1->body.replaced;
| lea TMP5, [TMP4 + offset];
| test TMP4, TMP4;
| cmovnz TMP2, TMP5;
/* TMP2 now contains address of item */
if (op == MVM_OP_sp_p6oget_o) {
| mov TMP3, [TMP2];
| test TMP3, TMP3;
/* Check if object doesn't point to NULL */
| jnz >3;
/* Otherwise load VMNull */
| get_vmnull TMP3;
|3:
} else if (op == MVM_OP_sp_p6ogetvt_o) {
/* vivify as type object */
MVMint16 spesh_idx = ins->operands[3].lit_i16;
| mov TMP3, [TMP2];
/* check for null */
| test TMP3, TMP3;
| jnz >4;
/* if null, vivify as type object from spesh slot */
| get_spesh_slot TMP3, spesh_idx;
/* need to hit write barrier? */
| check_wb TMP1, TMP3, >3;
| mov qword [rbp-0x28], TMP2; // address
| mov qword [rbp-0x30], TMP3; // value
| hit_wb WORK[obj]; // write barrier for header
| mov TMP3, qword [rbp-0x30];
| mov TMP2, qword [rbp-0x28];
|3:
/* store vivified type value in memory location */
| mov qword [TMP2], TMP3;
|4:
} else if (op == MVM_OP_sp_p6ogetvc_o) {
MVMint16 spesh_idx = ins->operands[3].lit_i16;
| mov TMP3, [TMP2];
| test TMP3, TMP3;
| jnz >4;
/* vivify as clone */
| mov ARG1, TC;
| get_spesh_slot ARG2, spesh_idx;
| callp &MVM_repr_clone;
| mov TMP3, RV;
/* reload object and address */
| mov TMP1, WORK[obj];
| lea TMP2, [TMP1 + (offset + body)];
| mov TMP4, P6OPAQUE:TMP1->body.replaced;
| lea TMP5, [TMP4 + offset];
| test TMP4, TMP4;
| cmovnz TMP2, TMP5;
/* assign with write barrier */
| check_wb TMP1, TMP3, >3;
| mov qword [rbp-0x28], TMP2; // address
| mov qword [rbp-0x30], TMP3; // value
| hit_wb WORK[obj]; // write barrier for header
| mov TMP3, qword [rbp-0x30];
| mov TMP2, qword [rbp-0x28];
|3:
| mov qword [TMP2], TMP3;
/* done */
|4:
} else {
/* the regular case */
| mov TMP3, [TMP2];
}
/* store in local register */
| mov WORK[dst], TMP3;
break;
}
case MVM_OP_sp_bind_i64:
case MVM_OP_sp_bind_n:
case MVM_OP_sp_bind_s:
case MVM_OP_sp_bind_o: {
MVMint16 obj = ins->operands[0].reg.orig;
MVMint16 offset = ins->operands[1].lit_i16;
MVMint16 val = ins->operands[2].reg.orig;
| mov TMP1, WORK[obj]; // object
| mov TMP2, WORK[val]; // value
if (op == MVM_OP_sp_bind_o || op == MVM_OP_sp_bind_s) {
/* check if we should hit write barrier */
| check_wb TMP1, TMP2, >2;
/* note: it is uneccesary to store pointers, because they
can just be loaded from memory */
| hit_wb WORK[obj];
| mov TMP1, aword WORK[obj]; // reload object
| mov TMP2, aword WORK[val]; // reload value
|2: // done
}
| mov qword [TMP1+offset], TMP2; // store value into body
break;
}
case MVM_OP_sp_get_i64:
case MVM_OP_sp_get_n:
case MVM_OP_sp_get_s:
case MVM_OP_sp_get_o: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 obj = ins->operands[1].reg.orig;
MVMint16 offset = ins->operands[2].lit_i16;
| mov TMP1, WORK[obj]; // object
| mov TMP2, qword [TMP1+offset]; // get value from body
| mov WORK[dst], TMP2;
break;
}
case MVM_OP_sp_deref_bind_i64:
case MVM_OP_sp_deref_bind_n: {
MVMint16 obj = ins->operands[0].reg.orig;
MVMint16 val = ins->operands[1].reg.orig;
MVMint16 offset = ins->operands[2].lit_i16;
| mov TMP1, WORK[obj]; // object
| mov TMP2, WORK[val]; // value
| mov TMP1, qword [TMP1+offset]; // find address of target
| mov qword [TMP1], TMP2;
break;
}
case MVM_OP_sp_deref_get_i64:
case MVM_OP_sp_deref_get_n: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 obj = ins->operands[1].reg.orig;
MVMint16 offset = ins->operands[2].lit_i16;
| mov TMP1, WORK[obj]; // object
| mov TMP3, qword [TMP1+offset]; // get value pointer from body
| mov TMP2, qword [TMP3]; // deref the pointer
| mov WORK[dst], TMP2;
break;
}
case MVM_OP_sp_p6obind_i:
case MVM_OP_sp_p6obind_n:
case MVM_OP_sp_p6obind_s:
case MVM_OP_sp_p6obind_o: {
MVMint16 obj = ins->operands[0].reg.orig;
MVMint16 offset = ins->operands[1].lit_i16;
MVMint16 val = ins->operands[2].reg.orig;
| mov TMP1, WORK[obj]; // object
| mov TMP2, WORK[val]; // value
| lea TMP3, P6OPAQUE:TMP1->body; // body
| cmp qword P6OBODY:TMP3->replaced, 0;
| je >1;
| mov TMP3, P6OBODY:TMP3->replaced; // replaced object body
|1:
if (op == MVM_OP_sp_p6obind_o || op == MVM_OP_sp_p6obind_s) {
/* check if we should hit write barrier */
| check_wb TMP1, TMP2, >2;
| mov qword [rbp-0x28], TMP2; // store value
| mov qword [rbp-0x30], TMP3; // store body pointer
| hit_wb WORK[obj];
| mov TMP3, qword [rbp-0x30]; // restore body pointer
| mov TMP2, qword [rbp-0x28]; // restore value
|2: // done
}
| mov [TMP3+offset], TMP2; // store value into body
break;
}
case MVM_OP_getwhere:
case MVM_OP_set: {
MVMint32 reg1 = ins->operands[0].reg.orig;
MVMint32 reg2 = ins->operands[1].reg.orig;
| mov TMP1, WORK[reg2];
| mov WORK[reg1], TMP1;
break;
}
case MVM_OP_sp_getspeshslot: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 spesh_idx = ins->operands[1].lit_i16;
| get_spesh_slot TMP1, spesh_idx;
| mov WORK[dst], TMP1;
break;
}
case MVM_OP_setdispatcher: {
MVMint16 src = ins->operands[0].reg.orig;
| mov TMP1, aword WORK[src];
| mov aword TC->cur_dispatcher, TMP1;
break;
}
case MVM_OP_takedispatcher: {
MVMint16 dst = ins->operands[0].reg.orig;
| mov TMP1, aword TC->cur_dispatcher;
| cmp TMP1, 0;
| je >2;
| mov TMP2, aword TC->cur_dispatcher_for;
| cmp TMP2, 0;
| je >1;
| mov TMP3, TC->cur_frame;
| mov TMP3, FRAME:TMP3->code_ref;
| cmp TMP2, TMP3;
| jne >2;
|1:
| mov aword WORK[dst], TMP1;
| mov aword TC->cur_dispatcher, NULL;
| jmp >3;
|2:
| get_vmnull TMP1;
| mov aword WORK[dst], TMP1;
|3:
break;
}
case MVM_OP_curcode: {
MVMint16 dst = ins->operands[0].reg.orig;
| mov TMP1, TC->cur_frame;
| mov TMP1, aword FRAME:TMP1->code_ref;
| mov aword WORK[dst], TMP1;
break;
}
case MVM_OP_getcode: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMuint16 idx = ins->operands[1].coderef_idx;
| mov TMP1, aword CU->body.coderefs;
| mov TMP1, aword OBJECTPTR:TMP1[idx];
| mov aword WORK[dst], TMP1;
break;
}
case MVM_OP_callercode: {
MVMint16 dst = ins->operands[0].reg.orig;
| mov TMP1, TC->cur_frame;
| mov TMP1, aword FRAME:TMP1->caller;
| test TMP1, TMP1;
| jz >1;
| mov TMP1, aword FRAME:TMP1->code_ref;
|1:
| mov aword WORK[dst], TMP1;
break;
}
case MVM_OP_hllboxtype_n:
case MVM_OP_hllboxtype_s:
case MVM_OP_hllboxtype_i: {
MVMint16 dst = ins->operands[0].reg.orig;
| mov TMP1, CU->body.hll_config;
if (op == MVM_OP_hllboxtype_n) {
| mov TMP1, aword HLLCONFIG:TMP1->num_box_type;
} else if (op == MVM_OP_hllboxtype_s) {
| mov TMP1, aword HLLCONFIG:TMP1->str_box_type;
} else {
| mov TMP1, aword HLLCONFIG:TMP1->int_box_type;
}
| mov aword WORK[dst], TMP1;
break;
}
case MVM_OP_null_s: {
MVMint16 dst = ins->operands[0].reg.orig;
| mov qword WORK[dst], 0;
break;
}
case MVM_OP_isnull_s: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 src = ins->operands[1].reg.orig;
| mov TMP1, WORK[src];
| test TMP1, TMP1;
| setz TMP2b;
| movzx TMP2, TMP2b;
| mov qword WORK[dst], TMP2;
break;
}
case MVM_OP_add_i:
case MVM_OP_sub_i:
case MVM_OP_bor_i:
case MVM_OP_band_i:
case MVM_OP_bxor_i: {
MVMint32 reg_a = ins->operands[0].reg.orig;
MVMint32 reg_b = ins->operands[1].reg.orig;
MVMint32 reg_c = ins->operands[2].reg.orig;
MVMSpeshFacts *operand_facts = MVM_spesh_get_facts(tc, jg->sg, ins->operands[2]);
if (reg_a == reg_b) {
if (operand_facts->flags & MVM_SPESH_FACT_KNOWN_VALUE &&
fits_in_32_bit(operand_facts->value.i)) {
MVMint64 value = operand_facts->value.i;
MVM_jit_log(tc, "accumulator for %s stayed in memory and "
" constant value %"PRId64" used\n", ins->info->name, value);
switch(ins->info->opcode) {
case MVM_OP_add_i:
| add qword WORK[reg_a], qword value;
break;
case MVM_OP_sub_i:
| sub qword WORK[reg_a], qword value;
break;
case MVM_OP_bor_i:
| or qword WORK[reg_a], qword value;
break;
case MVM_OP_band_i:
| and qword WORK[reg_a], qword value;
break;
case MVM_OP_bxor_i:
| xor qword WORK[reg_a], qword value;
break;
}
} else {
MVM_jit_log(tc, "accumulator for %s stayed in memory\n", ins->info->name);
| mov rax, WORK[reg_c];
switch(ins->info->opcode) {
case MVM_OP_add_i:
| add WORK[reg_a], rax;
break;
case MVM_OP_sub_i:
| sub WORK[reg_a], rax;
break;
case MVM_OP_bor_i:
| or WORK[reg_a], rax;
break;
case MVM_OP_band_i:
| and WORK[reg_a], rax;
break;
case MVM_OP_bxor_i:
| xor WORK[reg_a], rax;
break;
}
}
} else {
if (operand_facts->flags & MVM_SPESH_FACT_KNOWN_VALUE &&
fits_in_32_bit(operand_facts->value.i)) {
MVMint64 value = operand_facts->value.i;
MVM_jit_log(tc, "constant value %"PRId64" used for %s\n",
value, ins->info->name);
| mov rax, WORK[reg_b];
switch(ins->info->opcode) {
case MVM_OP_add_i:
| add rax, qword value;
break;
case MVM_OP_sub_i:
| sub rax, qword value;
break;
case MVM_OP_bor_i:
| or rax, qword value;
break;
case MVM_OP_band_i:
| and rax, qword value;
break;
case MVM_OP_bxor_i:
| xor rax, qword value;
break;
}
| mov WORK[reg_a], rax;
} else {
| mov rax, WORK[reg_b];
switch(ins->info->opcode) {
case MVM_OP_add_i:
| add rax, WORK[reg_c];
break;
case MVM_OP_sub_i:
| sub rax, WORK[reg_c];
break;
case MVM_OP_bor_i:
| or rax, WORK[reg_c];
break;
case MVM_OP_band_i:
| and rax, WORK[reg_c];
break;
case MVM_OP_bxor_i:
| xor rax, WORK[reg_c];
break;
}
| mov WORK[reg_a], rax;
}
}
break;
}
case MVM_OP_mul_i:
case MVM_OP_blshift_i:
case MVM_OP_brshift_i: {
MVMint32 reg_a = ins->operands[0].reg.orig;
MVMint32 reg_b = ins->operands[1].reg.orig;
MVMint32 reg_c = ins->operands[2].reg.orig;
| mov rax, WORK[reg_b];
switch(ins->info->opcode) {
case MVM_OP_mul_i:
| imul rax, WORK[reg_c];
break;
case MVM_OP_blshift_i:
| mov cl, byte WORK[reg_c];
| shl rax, cl;
break;
case MVM_OP_brshift_i:
| mov cl, byte WORK[reg_c];
| shr rax, cl;
break;
}
| mov WORK[reg_a], rax;
break;
}
case MVM_OP_div_i: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 a = ins->operands[1].reg.orig;
MVMint16 b = ins->operands[2].reg.orig;
| mov rax, WORK[a];
| mov rcx, WORK[b];
| cmp rcx, 0;
| jnz >1;
| throw_adhoc "Division by zero";
|1:
/* either num < 0, or denom < 0, but not both */
| setl dh;
| cmp rax, 0;
| setl dl;
| xor dl, dh;
| movzx r8d, dl;
| cqo;
| idiv rcx;
| test rdx, rdx;
| setnz cl;
| and r8b, cl;
/* r8 = bias = (modulo != 0) & ((num < 0) ^ (denom < 0)) */
| sub rax, r8;
| mov WORK[dst], rax;
break;
}
case MVM_OP_mod_i: {
MVMint16 dst = ins->operands[0].reg.orig;
MVMint16 a = ins->operands[1].reg.orig;
MVMint16 b = ins->operands[2].reg.orig;
| mov rax, WORK[a];
| mov rcx, WORK[b];
| cmp rcx, 0;
| jnz >1;
| throw_adhoc "Division by zero";
|1: