PSRAM support for M5Stack Fire

[phoddie]

I recently noticed that the M5 Stack Fire has a PSRAM chip. Now that PSRAM works on M5Stack Core2 it seems worth trying to get it working on M5Stack Fire also. The ESP32 in M5Stack Fire I have is a revision 1, which requires some extra settings to use the PSRAM. I've put together the changes to support that base, in part, on the work done here.

It seems to work! But, I've always found the M5Stack Fire to be a bit fragile and the revision 1 changes have lots of options: I'm not sure I've set them all correctly.

I'd appreciate it if some other M5Stack Fire users could give it a try. I think @washishi and @stc1988 may both have access to M5Stack Fire hardware.

To try this, you need need to change just two files:

1. In m5stack_fire/manifest.json, update the build section. Here's what it looks like before editing:

moddable/build/devices/esp32/targets/m5stack_fire/manifest.json

Lines 2 to 5 in 2420f19

	"build": {
	"SDKCONFIGPATH": "./sdkconfig",
	"PARTITIONS_FILE": "./sdkconfig/partitions.csv"
	},

Add this line:

		"C_FLAGS_SUBPLATFORM": "-mfix-esp32-psram-cache-issue"

2. Replace the contents of m5stack_fire/sdkconfig/sdkconfig.defaults with the following

sdkconfig.defaults

CONFIG_ESPTOOLPY_FLASHSIZE_1MB=n
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=n
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=n
CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y
CONFIG_ESPTOOLPY_FLASHSIZE_16MB=n
CONFIG_ESPTOOLPY_FLASHSIZE="8MB"

CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_ESP32_REV_MIN_0=n
CONFIG_ESP32_REV_MIN_1=y
CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP32_SPIRAM_SUPPORT=y

#
# SPI RAM config
#
CONFIG_SPIRAM_TYPE_AUTO=y
# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
CONFIG_SPIRAM_SIZE=-1
CONFIG_SPIRAM_SPEED_40M=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_BOOT_INIT=y
# CONFIG_SPIRAM_IGNORE_NOTFOUND is not set
# CONFIG_SPIRAM_USE_MEMMAP is not set
# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
CONFIG_SPIRAM_USE_MALLOC=y
CONFIG_SPIRAM_MEMTEST=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
# CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY is not set
CONFIG_SPIRAM_CACHE_WORKAROUND=y

#
# SPIRAM cache workaround debugging
#
CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW=y
# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST is not set
# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS is not set
# end of SPIRAM cache workaround debugging

CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set

#
# PSRAM clock and cs IO for ESP32-DOWD
#
CONFIG_D0WD_PSRAM_CLK_IO=17
CONFIG_D0WD_PSRAM_CS_IO=16
# end of PSRAM clock and cs IO for ESP32-DOWD

#
# PSRAM clock and cs IO for ESP32-D2WD
#
CONFIG_D2WD_PSRAM_CLK_IO=9
CONFIG_D2WD_PSRAM_CS_IO=10
# end of PSRAM clock and cs IO for ESP32-D2WD

#
# PSRAM clock and cs IO for ESP32-PICO
#
CONFIG_PICO_PSRAM_CS_IO=10
# end of PSRAM clock and cs IO for ESP32-PICO

# CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN is not set
CONFIG_SPIRAM_SPIWP_SD3_PIN=7
# CONFIG_SPIRAM_2T_MODE is not set
# end of SPI RAM config

If you have applied the changes correctly, the Instruments panel in xsbug should show about 4,400,000 bytes of free system memory (!!) when running the helloworld example.

I've recently learned that there is at least one revision of the M5Stack Fire hardware. It uses different display. It wonder if it might also use a different ESP32 (revision 3, for example). The revision 1 workarounds should still be safe on revision 3 hardware. It would be good to confirm that.

If you can help verify that these changes work reliably on M5Stack Fire, we can merge them so they are available to everyone by default. Thank you!!

[stc1988]

Unfortunately, I don't have M5Stack Fire.

@washishi
Can you try this?

[washishi]

i tried it
but something seems to be wrong
won't connect to xsbug
It seems that the program is not running and there is no startup sound.
Since Fire is Flash16MB, I modified sdkconfig.defaults a little, but this is irrelevant, right?
(Because the partition table and flash size do not match)
By the way, building with "-p m5stack" works fine

M5Stack_Fire seems to have 7 revisions
the detail is right below
https://docs.m5stack.com/en/core/fire_v2.7#version-updates

What I have is v2.6 of 2021.8 with 8MB of PSRAM
ESP32 is like revision 3
esptool.py chip_id says "Chip is ESP32-D0WDQ6-V3 (revision 3)"

What else can I try?

[phoddie]

@washishi – thank you for trying. 7 revisions! That's a lot.

Since Fire is Flash16MB, I modified sdkconfig.defaults a little, but this is irrelevant, right?

Yes, it should be.

What I have is v2.6 of 2021.8 with 8MB of PSRAM
ESP32 is like revision 3
esptool.py chip_id says "Chip is ESP32-D0WDQ6-V3 (revision 3)"

Revision 3 is easier. But... the Revision 1 build should still work.

If it is OK, let's try two things.

Please try this first: run an instrumented Moddable SDK build. This will show more of what is going and perhaps why it is failing. When running mcconfig, replace -d with -i (mcconfig -i -m -p esp32/m5stack_fire). Instead of xsbug, you should see the serial log from the ESP-IDF. I would like to see that log.

Next, in the sdkconfig.defaults above let's try revision 3. Change CONFIG_ESP32_REV_MIN_1=y to:

CONFIG_ESP32_REV_MIN_3=y
CONFIG_ESP32_REV_MIN=3

Then run the instrumented build again.

[washishi]

I tryed instrumented build.
panic_abort was happening

serial log

--- idf_monitor on /dev/ttyACM0 115200 --- --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H --- ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x17 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:344
load:0x40078000,len:13524
load:0x40080400,len:3536
0x40080400: _init at ??:?

entry 0x400805d8
I (33) psram: This chip is ESP32-D0WD
I (34) spiram: Found 64MBit SPI RAM device
I (34) spiram: SPI RAM mode: flash 80m sram 40m
I (34) spiram: PSRAM initialized, cache is in low/high (2-core) mode.
I (40) cpu_start: Pro cpu up.
I (42) cpu_start: Starting app cpu, entry point is 0x40081138
0x40081138: call_start_cpu1 at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/port/cpu_start.c:148

I (0) cpu_start: App cpu up.
I (937) spiram: SPI SRAM memory test OK
I (944) cpu_start: Pro cpu start user code
I (944) cpu_start: cpu freq: 240000000
I (944) cpu_start: Application information:
I (945) cpu_start: Project name: xs_esp32
I (948) cpu_start: App version: 3.9.2-8-g2420f19c-dirty
I (954) cpu_start: Compile time: May 20 2023 07:26:19
I (959) cpu_start: ELF file SHA256: e06262af41f42925...
I (964) cpu_start: ESP-IDF: v4.4.3-dirty
I (969) heap_init: Initializing. RAM available for dynamic allocation:
I (975) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (980) heap_init: At 3FFB3A08 len 0002C5F8 (177 KiB): DRAM
I (985) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (990) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (996) heap_init: At 40091C7C len 0000E384 (56 KiB): IRAM
I (1001) spiram: Adding pool of 4095K of external SPI memory to heap allocator
I (1009) spi_flash: detected chip: generic
I (1012) spi_flash: flash io: qio

assert failed: 0x4011bfea
0x4011bfea: esp_startup_start_app at /home/stackchan/Projects/esp32/esp-idf/components/freertos/port/xtensa/port.c:492 (discriminator 1)

Backtrace: 0x400819b1:0x3ffe3b80 0x4008afa5:0x3ffe3ba0 0x40090ad5:0x3ffe3bc0 0x4011bfea:0x3ffe3c00 0x400d1a79:0x3ffe3c20 0x40081449:0x3ffe3c60 0x40079216:0x3ffe3c90 |<-CORRUPTED
0x400819b1: panic_abort at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/panic.c:402

0x4008afa5: esp_system_abort at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/esp_system.c:128

0x40090ad5: __assert_func at /home/stackchan/Projects/esp32/esp-idf/components/newlib/assert.c:47

0x4011bfea: esp_startup_start_app at /home/stackchan/Projects/esp32/esp-idf/components/freertos/port/xtensa/port.c:492 (discriminator 1)

0x400d1a79: start_cpu0_default at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/startup.c:454 (discriminator 3)

0x40081449: call_start_cpu0 at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/port/cpu_start.c:632

ELF file SHA256: e06262af41f42925

Entering gdb stub now.
$T0b#e6GNU gdb (esp-gdb) 11.2_20220823
Copyright (C) 2022 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=aarch64-linux-gnu --target=xtensa-esp-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
https://www.gnu.org/software/gdb/bugs/.
Find the GDB manual and other documentation resources online at:
http://www.gnu.org/software/gdb/documentation/.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from /home/stackchan/Projects/moddable/build/tmp/esp32/m5stack_fire/instrument/helloworld/xsProj-esp32/build/xs_esp32.elf...
Remote debugging using /dev/ttyACM0
warning: multi-threaded target stopped without sending a thread-id, using first non-exited thread
[Switching to Thread 1]
0x400819b4 in panic_abort (details=0x3ffe3bc0 "assert failed: 0x4011bfea")
at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/panic.c:402
402 *((volatile int *) 0) = 0; // NOLINT(clang-analyzer-core.NullDereference) should be an invalid operation on targets
(gdb)

Then I changed sdkconfig.defaults and ran

serial log

--- idf_monitor on /dev/ttyACM0 115200 --- --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H --- ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x17 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:344
load:0x40078000,len:13524
load:0x40080400,len:3536
0x40080400: _init at ??:?

entry 0x400805d8
I (33) psram: This chip is ESP32-D0WD
I (33) spiram: Found 64MBit SPI RAM device
I (33) spiram: SPI RAM mode: flash 80m sram 40m
I (33) spiram: PSRAM initialized, cache is in low/high (2-core) mode.
I (39) cpu_start: Pro cpu up.
I (42) cpu_start: Starting app cpu, entry point is 0x40081068
0x40081068: call_start_cpu1 at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/port/cpu_start.c:148

I (0) cpu_start: App cpu up.
I (925) spiram: SPI SRAM memory test OK
I (932) cpu_start: Pro cpu start user code
I (932) cpu_start: cpu freq: 240000000
I (932) cpu_start: Application information:
I (932) cpu_start: Project name: xs_esp32
I (936) cpu_start: App version: 3.9.2-8-g2420f19c-dirty
I (942) cpu_start: Compile time: May 20 2023 07:36:11
I (947) cpu_start: ELF file SHA256: 0792bb536157559e...
I (952) cpu_start: ESP-IDF: v4.4.3-dirty
I (956) heap_init: Initializing. RAM available for dynamic allocation:
I (963) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (968) heap_init: At 3FFB3900 len 0002C700 (177 KiB): DRAM
I (973) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (978) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (984) heap_init: At 4008F07C len 00010F84 (67 KiB): IRAM
I (989) spiram: Adding pool of 4095K of external SPI memory to heap allocator
I (996) spi_flash: detected chip: generic
I (1000) spi_flash: flash io: qio
I (1003) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (1015) spiram: Reserving pool of 32K of internal memory for DMA/internal allocations
instruments key: Pixels drawn,Frames drawn,Network bytes read,Network bytes written,Network sockets,Timers,Files,Poco display list used,Piu command List used,SPI flash erases,Turns,System bytes free,CPU 0,CPU 1,Chunk used,Chunk available,Slot used,Slot available,Stack used,Stack available,Garbage collections,Keys used,Modules loaded,Parser used,Floating Point
Error initializing: bad WHO_AM_I ID for MPU-6050.
instruments: 10,0,0,0,0,0,0,0,0,0,0,4294814,0,8,560,78848,2560,78832,1424,8192,0,0,0,0,0
Hello, world - sample
instruments: 0,0,0,0,0,0,0,0,0,0,1,4303330,0,0,608,78848,3184,78832,976,8192,0,1,1,0,0
instruments: 0,0,0,0,0,0,0,0,0,0,0,4303330,0,0,608,78848,3184,78832,208,8192,0,1,1,0,0
instruments: 0,0,0,0,0,0,0,0,0,0,0,4303330,0,0,608,78848,3184,78832,208,8192,0,1,1,0,0
instruments: 0,0,0,0,0,0,0,0,0,0,0,4303330,0,0,608,78848,3184,78832,208,8192,0,1,1,0,0
(Repeat the same below)

It seems to work normally, so I tried running xsbug with the -d option

[phoddie]

Great! We are making progress. The failure in the v1 case is caused by this code:

void esp_startup_start_app(void)
{
#if !CONFIG_ESP_INT_WDT
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
    assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
#endif
#endif

It is cool that Espressif includes this assert. (I'm not sure why I didn't have the same problem though.) In the sdkconfig.defaults for M5Stack Fire please try adding this line. They try the V1 support with an instrumented build again.

CONFIG_ESP_INT_WDT=y

Thank you.

[washishi]

I reverted my sdkconfig.defaults and added CONFIG_ESP_INT_WDT=y

CONFIG_ESP32_REV_MIN_0=n
CONFIG_ESP32_REV_MIN_1=y
CONFIG_ESP_INT_WDT=y

It worked fine!

serial log

--- idf_monitor on /dev/ttyACM0 115200 --- --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H --- ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x17 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:344
load:0x40078000,len:13524
load:0x40080400,len:3536
0x40080400: _init at ??:?

entry 0x400805d8
I (33) psram: This chip is ESP32-D0WD
I (34) spiram: Found 64MBit SPI RAM device
I (34) spiram: SPI RAM mode: flash 80m sram 40m
I (34) spiram: PSRAM initialized, cache is in low/high (2-core) mode.
I (40) cpu_start: Pro cpu up.
I (42) cpu_start: Starting app cpu, entry point is 0x40081168
0x40081168: call_start_cpu1 at /home/stackchan/Projects/esp32/esp-idf/components/esp_system/port/cpu_start.c:148

I (0) cpu_start: App cpu up.
I (937) spiram: SPI SRAM memory test OK
I (944) cpu_start: Pro cpu start user code
I (944) cpu_start: cpu freq: 240000000
I (945) cpu_start: Application information:
I (945) cpu_start: Project name: xs_esp32
I (948) cpu_start: App version: 3.9.2-8-g2420f19c-dirty
I (954) cpu_start: Compile time: May 20 2023 08:59:37
I (959) cpu_start: ELF file SHA256: 101751f208e1f7a6...
I (964) cpu_start: ESP-IDF: v4.4.3-dirty
I (969) heap_init: Initializing. RAM available for dynamic allocation:
I (975) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (980) heap_init: At 3FFB3A58 len 0002C5A8 (177 KiB): DRAM
I (985) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (991) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (996) heap_init: At 40091EC4 len 0000E13C (56 KiB): IRAM
I (1001) spiram: Adding pool of 4095K of external SPI memory to heap allocator
I (1009) spi_flash: detected chip: generic
I (1012) spi_flash: flash io: qio
I (1016) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (1028) spiram: Reserving pool of 32K of internal memory for DMA/internal allocations
instruments key: Pixels drawn,Frames drawn,Network bytes read,Network bytes written,Network sockets,Timers,Files,Poco display list used,Piu command List used,SPI flash erases,Turns,System bytes free,CPU 0,CPU 1,Chunk used,Chunk available,Slot used,Slot available,Stack used,Stack available,Garbage collections,Keys used,Modules loaded,Parser used,Floating Point
Error initializing: bad WHO_AM_I ID for MPU-6050.
instruments: 10,0,0,0,0,0,0,0,0,0,0,4294470,1,7,560,78848,2560,78832,1424,8192,0,0,0,0,0
Hello, world - sample
instruments: 0,0,0,0,0,0,0,0,0,0,1,4302986,0,0,608,78848,3184,78832,976,8192,0,1,1,0,0
instruments: 0,0,0,0,0,0,0,0,0,0,0,4302986,0,0,608,78848,3184,78832,208,8192,0,1,1,0,0
instruments: 0,0,0,0,0,0,0,0,0,0,0,4302986,0,0,608,78848,3184,78832,208,8192,0,1,1,0,0
(Repeat the same below)

running xsbug with the -d option

My Fire should have 8MB of PSRAM, so why doesn't it say 8MB? I looked it up and found this entry
https://www.esp32.com/viewtopic.php?t=13180

I'm glad I was of help

[phoddie]

Cool. Thank you! I think I have enough to commit the changes to the Moddable repository.

My Fire should have 8MB of PSRAM, so why doesn't it say 8MB?

Right. Only 4 MB is directly addressable as system memory. The other 4 MB is present but requires extra work to access through bank switching. Anyway... 4 MB is 16x more memory than you have now. It should be good enough for a little while. ;)