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mealy1.flow.rpt
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mealy1.flow.rpt
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Flow report for mealy1
Tue Mar 01 15:16:48 2022
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+-----------------------------------------+
; Flow Status ; Successful - Tue Mar 01 15:16:48 2022 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name ; mealy1 ;
; Top-level Entity Name ; mealy1 ;
; Family ; FLEX10KE ;
; Met timing requirements ; Yes ;
; Total logic elements ; 3 / 1,728 ( < 1 % ) ;
; Total pins ; 4 / 102 ( 4 % ) ;
; Total memory bits ; 0 / 24,576 ( 0 % ) ;
; Total PLLs ; 0 ;
; Device ; EPF10K30ETC144-1 ;
; Timing Models ; Final ;
+-------------------------+-----------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/01/2022 15:16:44 ;
; Main task ; Compilation ;
; Revision Name ; mealy1 ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------------+
; COMPILER_SIGNATURE_ID ; 198112241094619.164612620403604 ; -- ; -- ; -- ;
; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Custom ; <None> ; -- ; -- ;
; EDA_INPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_design_synthesis ;
; EDA_NETLIST_WRITER_OUTPUT_DIR ; timing/custom ; -- ; -- ; eda_timing_analysis ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_timing_analysis ;
; EDA_SIMULATION_TOOL ; Custom Verilog HDL ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; EDA_TIMING_ANALYSIS_TOOL ; Custom Verilog HDL ; <None> ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 217 MB ; 00:00:00 ;
; Fitter ; 00:00:00 ; 1.0 ; 223 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 211 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 177 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 157 MB ; 00:00:00 ;
; Total ; 00:00:00 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+-----------------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+-----------------------------+---------------+------------+----------------+
; Analysis & Synthesis ; MuballighWorkStationDesktop ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; MuballighWorkStationDesktop ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; MuballighWorkStationDesktop ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; MuballighWorkStationDesktop ; Windows Vista ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; MuballighWorkStationDesktop ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+-----------------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off mealy1 -c mealy1
quartus_fit --read_settings_files=off --write_settings_files=off mealy1 -c mealy1
quartus_asm --read_settings_files=off --write_settings_files=off mealy1 -c mealy1
quartus_tan --read_settings_files=off --write_settings_files=off mealy1 -c mealy1
quartus_eda --read_settings_files=off --write_settings_files=off mealy1 -c mealy1