/
nv_gpu_ops.c
10210 lines (8588 loc) · 359 KB
/
nv_gpu_ops.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "core/prelude.h"
#include <class/cl0002.h>
#include <class/cl0005.h>
#include <class/cl003e.h> // NV01_MEMORY_SYSTEM
#include <class/cl0040.h> // NV01_MEMORY_LOCAL_USER
#include <class/cl0080.h>
#include <class/cl503b.h>
#include <class/cl50a0.h> // NV50_MEMORY_VIRTUAL
#include <class/cl90e6.h>
#include <class/cl90f1.h>
#include <class/cla06c.h> // KEPLER_CHANNEL_GROUP_A
#include <class/cla06f.h>
#include <class/cla080.h>
#include <class/clb069.h>
#include <class/clb069sw.h>
#include <class/clb06f.h>
#include <class/clb0b5.h>
#include <class/clb0b5sw.h>
#include <class/clb0c0.h>
#include <class/clb1c0.h>
#include <class/clc06f.h>
#include <class/clc076.h>
#include <class/clc0b5.h>
#include <class/clc0c0.h>
#include <class/clc1b5.h>
#include <class/clc1c0.h>
#include <class/clc361.h>
#include <class/clc365.h>
#include <class/clc369.h>
#include <class/clc36f.h>
#include <class/clc3b5.h>
#include <class/clc3c0.h>
#include <class/clc46f.h>
#include <class/clc4c0.h>
#include <class/clc56f.h>
#include <class/clc572.h> // PHYSICAL_CHANNEL_GPFIFO
#include <class/clc574.h> // UVM_CHANNEL_RETAINER
#include <class/clc5b5.h>
#include <class/clc5c0.h>
#include <class/clc637.h>
#include <class/clc6b5.h>
#include <class/clc6c0.h>
#include <class/clc7b5.h>
#include <class/clc7c0.h>
#include <class/clcb33.h> // NV_CONFIDENTIAL_COMPUTE
#include <class/clc661.h> // HOPPER_USERMODE_A
#include <class/clc8b5.h> // HOPPER_DMA_COPY_A
#include <class/clcbc0.h> // HOPPER_COMPUTE_A
#include <class/clcba2.h> // HOPPER_SEC2_WORK_LAUNCH_A
#include <alloc/alloc_access_counter_buffer.h>
#include <ctrl/ctrl0000/ctrl0000gpu.h>
#include <ctrl/ctrl0000/ctrl0000system.h>
#include <ctrl/ctrl0080/ctrl0080fifo.h>
#include <ctrl/ctrl0080/ctrl0080gpu.h>
#include <ctrl/ctrl2080/ctrl2080fb.h>
#include <ctrl/ctrl2080/ctrl2080fifo.h>
#include <ctrl/ctrl2080/ctrl2080gpu.h>
#include <ctrl/ctrl2080/ctrl2080gr.h>
#include <ctrl/ctrl90e6.h>
#include <ctrl/ctrl90f1.h>
#include <ctrl/ctrla06f.h>
#include <ctrl/ctrla080.h>
#include <ctrl/ctrlb069.h>
#include <ctrl/ctrlc365.h>
#include <ctrl/ctrlc369.h>
#include <ctrl/ctrlc36f.h>
#include <ctrl/ctrlcb33.h>
#include <ampere/ga100/dev_runlist.h>
#include <containers/queue.h>
#include <core/locks.h>
#include <gpu/bus/kern_bus.h>
#include <gpu/device/device.h>
#include <gpu/gpu.h>
#include <gpu/mem_mgr/heap.h>
#include <gpu/mem_mgr/mem_mgr.h>
#include <gpu/mem_mgr/virt_mem_allocator.h>
#include <gpu/mem_sys/kern_mem_sys.h>
#include <gpu/mmu/kern_gmmu.h>
#include <gpu/subdevice/subdevice.h>
#include <gpu_mgr/gpu_mgr.h>
#include <kernel/gpu/fifo/kernel_channel.h>
#include <kernel/gpu/fifo/kernel_channel_group.h>
#include <kernel/gpu/fifo/kernel_channel_group_api.h>
#include <kernel/gpu/fifo/kernel_ctxshare.h>
#include <kernel/gpu/gr/kernel_graphics.h>
#include <kernel/gpu/mig_mgr/gpu_instance_subscription.h>
#include <kernel/gpu/mig_mgr/kernel_mig_manager.h>
#include <kernel/gpu/nvlink/kernel_nvlink.h>
#include <mem_mgr/fabric_vaspace.h>
#include <mem_mgr/fla_mem.h>
#include <mem_mgr/gpu_vaspace.h>
#include <mem_mgr/vaspace.h>
#include <mmu/gmmu_fmt.h>
#include <nv_uvm_types.h>
#include <objrpc.h>
#include <os/os.h>
#include <resserv/rs_client.h>
#include <rmapi/client.h>
#include <rmapi/nv_gpu_ops.h>
#include <rmapi/rs_utils.h>
#include <turing/tu102/dev_vm.h>
#include <gpu/mem_mgr/vaspace_api.h>
#include <vgpu/rpc.h>
#include <platform/sli/sli.h>
#include <maxwell/gm107/dev_timer.h>
#include <pascal/gp100/dev_mmu.h>
#include <kernel/gpu/conf_compute/ccsl.h>
#define NV_GPU_OPS_NUM_GPFIFO_ENTRIES_DEFAULT 1024
#define NV_GPU_SMALL_PAGESIZE (4 * 1024)
#define PAGE_SIZE_DEFAULT UVM_PAGE_SIZE_DEFAULT
typedef struct
{
NODE btreeNode;
NvU64 address;
NvHandle handle;
NvU64 size;
// childHandle tightly couples a physical allocation with a VA memdesc.
// A VA memsdesc is considered as a parent memdesc i.e. childHandle will be non-zero (valid).
// - If childHandle is non-zero,there is a corresponding PA allocation present.
// - If childHandle is zero, this is an invalid state for a VA memdesc.
NvHandle childHandle;
} gpuMemDesc;
typedef struct
{
NvU64 pageSize; // default is 4k or 64k else use pagesize = 2M.
NvU64 alignment;
} gpuVaAllocInfo;
typedef struct
{
NODE btreeNode;
NvU64 cpuPointer;
NvHandle handle;
} cpuMappingDesc;
typedef struct
{
NODE btreeNode;
PORT_RWLOCK *btreeLock;
NvHandle deviceHandle;
PNODE subDevices;
NvU32 subDeviceCount;
NvU32 arch;
NvU32 implementation;
} deviceDesc;
typedef struct
{
NODE btreeNode;
NvHandle subDeviceHandle;
NvU64 refCount;
struct
{
NvHandle handle;
// Pointer to the SMC partition information. It is used as a flag to
// indicate that the SMC information has been initialized.
KERNEL_MIG_GPU_INSTANCE *info;
} smcPartition;
NvU32 eccOffset;
NvU32 eccMask;
void *eccReadLocation;
NvHandle eccMasterHandle;
NvHandle eccCallbackHandle;
NvBool bEccInitialized;
NvBool bEccEnabled;
NvBool eccErrorNotifier;
NVOS10_EVENT_KERNEL_CALLBACK_EX eccDbeCallback;
// The below is used for controlling channel(s) in the GPU.
// Example: Volta maps the doorbell work submission register in this
// region.
NvHandle clientRegionHandle;
volatile void *clientRegionMapping;
NvHandle hP2pObject;
volatile NvU64 p2pObjectRef;
} subDeviceDesc;
struct gpuSession
{
NvHandle handle;
PNODE devices;
PORT_RWLOCK *btreeLock;
};
MAKE_MAP(MemdescMap, PMEMORY_DESCRIPTOR);
struct gpuDevice
{
deviceDesc *rmDevice;
subDeviceDesc *rmSubDevice;
// same as rmDevice->deviceHandle
NvHandle handle;
// same as rmSubDevice->subDeviceHandle
NvHandle subhandle;
NvU32 deviceInstance;
NvU32 subdeviceInstance;
NvU32 gpuId;
// TODO: Bug 3906861: The info struct contains many of these fields. Find
// and remove the redundant fields from this top level.
NvU32 hostClass;
NvU32 ceClass;
NvU32 sec2Class;
NvU32 computeClass;
NvU32 faultBufferClass;
NvU32 accessCounterBufferClass;
NvBool isTccMode;
NvBool isWddmMode;
struct gpuSession *session;
NvU8 gpuUUID[NV_GPU_UUID_LEN];
gpuFbInfo fbInfo;
gpuInfo info;
MemdescMap kern2PhysDescrMap;
PORT_MUTEX *pPagingChannelRpcMutex;
};
struct gpuAddressSpace
{
NvHandle handle;
struct gpuDevice *device;
PNODE allocations;
PORT_RWLOCK *allocationsLock;
PNODE cpuMappings;
PORT_RWLOCK *cpuMappingsLock;
PNODE physAllocations;
PORT_RWLOCK *physAllocationsLock;
NvU64 vaBase;
NvU64 vaSize;
// Dummy BAR1 allocation required on PCIe systems when GPPut resides in
// sysmem.
struct
{
NvU64 refCount;
NvU64 gpuAddr;
volatile void *cpuAddr;
} dummyGpuAlloc;
};
struct gpuTsg
{
NvHandle tsgHandle;
struct gpuAddressSpace *vaSpace;
UVM_GPU_CHANNEL_ENGINE_TYPE engineType;
// Index of the engine the TSG is bound to.
// Ignored if engineType is anything other than
// UVM_GPU_CHANNEL_ENGINE_TYPE_CE.
NvU32 engineIndex;
// True when the GPU does not support TSG for the engineType.
NvBool isFakeTsg;
};
struct gpuChannel
{
const struct gpuTsg *tsg;
NvHandle channelHandle;
NvHandle engineHandle;
NvU32 hwRunlistId;
NvU32 hwChannelId;
NvU64 gpFifo;
NvNotification *errorNotifier;
NvU64 errorNotifierOffset;
NvU64 *gpFifoEntries;
NvU32 fifoEntries;
KeplerAControlGPFifo *controlPage;
NvHandle hFaultCancelSwMethodClass;
volatile unsigned *workSubmissionOffset;
NvU32 workSubmissionToken;
volatile NvU32 *pWorkSubmissionToken;
NvHandle hUserdPhysHandle;
NvU64 userdGpuAddr;
UVM_BUFFER_LOCATION gpFifoLoc;
UVM_BUFFER_LOCATION gpPutLoc;
NvBool retainedDummyAlloc;
NvBool bClientRegionGpuMappingNeeded;
NvU64 clientRegionGpuAddr;
};
// Add 3 to include local ctx buffer, patch context buffer and PM ctxsw buffer
ct_assert(UVM_GPU_CHANNEL_MAX_RESOURCES >= (GR_GLOBALCTX_BUFFER_COUNT + 3));
// A retained channel is a user client's channel which has been registered with
// the UVM driver.
struct gpuRetainedChannel_struct
{
struct gpuDevice *device;
deviceDesc *rmDevice;
subDeviceDesc *rmSubDevice;
struct gpuSession *session;
OBJGPU *pGpu;
MEMORY_DESCRIPTOR *instanceMemDesc;
MEMORY_DESCRIPTOR *resourceMemDesc[UVM_GPU_CHANNEL_MAX_RESOURCES];
UVM_GPU_CHANNEL_ENGINE_TYPE channelEngineType;
NvU32 resourceCount;
NvU32 chId;
NvU32 runlistId;
NvU32 grIdx;
// Dup of user's TSG (if one exists) under our RM client
NvHandle hDupTsg;
// Dup to context share object
NvHandle hDupKernelCtxShare;
// Handle for object that retains chId and instance mem
NvHandle hChannelRetainer;
};
struct allocFlags
{
NvBool bGetKernelVA;
NvBool bfixedAddressAllocate;
};
struct ChannelAllocInfo
{
NV_CHANNEL_ALLOC_PARAMS gpFifoAllocParams;
gpuAllocInfo gpuAllocInfo;
};
struct systemP2PCaps
{
// peerId[i] contains gpu[i]'s peer id of gpu[1 - i]
NvU32 peerIds[2];
// egmPeerId[i] contains gpu[i]'s peer id of gpu[1 - i]
NvU32 egmPeerIds[2];
// true if the two GPUs are direct NvLink or PCIe peers
NvU32 accessSupported : 1;
// true if the two GPUs are indirect (NvLink) peers
NvU32 indirectAccessSupported : 1;
// true if the two GPUs are direct NvLink peers
NvU32 nvlinkSupported : 1;
NvU32 atomicSupported : 1;
// optimalNvlinkWriteCEs[i] contains the index of the optimal CE to use when
// writing from gpu[i] to gpu[1 - i]
NvU32 optimalNvlinkWriteCEs[2];
};
static NV_STATUS findUvmAddressSpace(NvHandle hClient, NvU32 gpuInstance, NvHandle *pHandle, OBJVASPACE **ppVaspace);
static NV_STATUS nvGpuOpsGpuMalloc(struct gpuAddressSpace *vaSpace,
NvBool isSystemMemory,
NvLength length,
NvU64 *gpuOffset,
struct allocFlags flags,
gpuAllocInfo *allocInfo);
static NV_STATUS trackDescriptor(PNODE *pRoot, NvU64 key, void *desc);
static NV_STATUS findDescriptor(PNODE pRoot, NvU64 key, void **desc);
static NV_STATUS deleteDescriptor(PNODE *pRoot, NvU64 key, void **desc);
static NV_STATUS destroyAllGpuMemDescriptors(NvHandle hClient, PNODE pNode);
static NV_STATUS getHandleForVirtualAddr(struct gpuAddressSpace *vaSpace,
NvU64 allocationVa,
NvBool bPhysical,
NvHandle *pHandle);
static NV_STATUS findDeviceClasses(NvHandle hRoot,
NvHandle hDevice,
NvHandle hSubdevice,
NvU32 *hostClass,
NvU32 *ceClass,
NvU32 *computeClass,
NvU32 *faultBufferClass,
NvU32 *accessCounterBufferClass,
NvU32 *sec2Class);
static NV_STATUS queryCopyEngines(struct gpuDevice *gpu, gpuCesCaps *cesCaps);
static void nvGpuOpsFreeVirtual(struct gpuAddressSpace *vaSpace,
NvU64 vaOffset);
static NvBool isDeviceVoltaPlus(const struct gpuDevice *device);
static NvBool isDeviceTuringPlus(const struct gpuDevice *device);
static NV_STATUS gpuDeviceMapUsermodeRegion(struct gpuDevice *device);
static void gpuDeviceDestroyUsermodeRegion(struct gpuDevice *device);
static void gpuDeviceUnmapCpuFreeHandle(struct gpuDevice *device,
NvHandle handle,
void *ptr,
NvU32 flags);
static NV_STATUS allocNvlinkStatus(NvHandle hClient,
NvHandle hSubDevice,
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut);
static NvU32 getNvlinkConnectionToNpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus,
NvBool *atomicSupported,
NvU32 *linkBandwidthMBps);
static NvU32 getNvlinkConnectionToSwitch(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus,
NvU32 *linkBandwidthMBps);
static NV_STATUS nvGpuOpsGetMemoryByHandle(NvHandle hClient, NvHandle hMemory, Memory **ppMemory);
static void _nvGpuOpsReleaseChannel(gpuRetainedChannel *retainedChannel);
static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device,
NvHandle hClient,
NvHandle hKernelChannel,
gpuRetainedChannel *retainedChannel,
gpuChannelInstanceInfo *channelInstanceInfo);
static void _nvGpuOpsReleaseChannelResources(gpuRetainedChannel *retainedChannel);
static NV_STATUS _nvGpuOpsP2pObjectCreate(struct gpuDevice *device1,
struct gpuDevice *device2,
NvHandle *hP2pObject,
RMAPI_TYPE rmapiType);
static NV_STATUS _nvGpuOpsP2pObjectDestroy(struct gpuSession *session,
NvHandle hP2pObject,
RMAPI_TYPE rmapiType);
static NV_STATUS
nvGpuOpsQueryGpuConfidentialComputeCaps(NvHandle hClient,
UvmGpuConfComputeCaps *pGpuConfComputeCaps);
/*
* This function will lock the RM API lock according to rmApiLockFlags, and then
* examine numLocksNeeded. If this is 0, no GPU locks will be acquired. If it
* is 1, the GPU lock for deviceInstance1 will be locked. If it is 2, both GPU
* locks for deviceInstance1 and deviceInstance2 will be locked. If it is any
* other number, all the GPU locks will be acquired.
*
* This function will attempt to grab the needed GPU locks, and will write the
* resulting mask into *lockedGpusMask. In the event of a failure to acquire any
* needed GPU locks, the written mask is 0 and the function returns
* NV_ERR_INVALID_LOCK_STATE. In this case, all locks held are released and the
* caller does not need to release any locks.
*/
typedef struct nvGpuOpsLockSet
{
NvBool isRmLockAcquired;
NvBool isRmSemaAcquired;
GPU_MASK gpuMask;
RsClient *pClientLocked;
} nvGpuOpsLockSet;
static void _nvGpuOpsLocksRelease(nvGpuOpsLockSet *acquiredLocks)
{
OBJSYS *pSys;
pSys = SYS_GET_INSTANCE();
if (acquiredLocks->gpuMask != 0)
{
rmGpuGroupLockRelease(acquiredLocks->gpuMask, GPUS_LOCK_FLAGS_NONE);
acquiredLocks->gpuMask = 0;
}
if (acquiredLocks->pClientLocked != NULL)
{
serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, acquiredLocks->pClientLocked);
acquiredLocks->pClientLocked = NULL;
}
if (acquiredLocks->isRmLockAcquired == NV_TRUE)
{
rmapiLockRelease();
acquiredLocks->isRmLockAcquired = NV_FALSE;
}
if (acquiredLocks->isRmSemaAcquired == NV_TRUE)
{
osReleaseRmSema(pSys->pSema, NULL);
acquiredLocks->isRmSemaAcquired = NV_FALSE;
}
}
static NV_STATUS _nvGpuOpsLocksAcquire(NvU32 rmApiLockFlags,
NvHandle hClient,
RsClient **ppClient,
NvU32 numLocksNeeded,
NvU32 deviceInstance1,
NvU32 deviceInstance2,
nvGpuOpsLockSet *acquiredLocks)
{
NV_STATUS status;
OBJSYS *pSys;
GPU_MASK gpuMaskRequested;
GPU_MASK gpuMaskAcquired;
acquiredLocks->isRmSemaAcquired = NV_FALSE;
acquiredLocks->isRmLockAcquired = NV_FALSE;
acquiredLocks->gpuMask = 0;
acquiredLocks->pClientLocked = NULL;
pSys = SYS_GET_INSTANCE();
if (pSys == NULL)
{
return NV_ERR_GENERIC;
}
status = osAcquireRmSema(pSys->pSema);
if (status != NV_OK)
{
return status;
}
acquiredLocks->isRmSemaAcquired = NV_TRUE;
status = rmapiLockAcquire(rmApiLockFlags, RM_LOCK_MODULES_GPU_OPS);
if (status != NV_OK)
{
_nvGpuOpsLocksRelease(acquiredLocks);
return status;
}
acquiredLocks->isRmLockAcquired = NV_TRUE;
if (hClient != NV01_NULL_OBJECT)
{
status = serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, &acquiredLocks->pClientLocked);
if (status != NV_OK)
{
_nvGpuOpsLocksRelease(acquiredLocks);
return status;
}
if (ppClient != NULL)
*ppClient = acquiredLocks->pClientLocked;
}
//
// Determine the GPU lock mask we need. If we are asked for 0, 1, or 2 locks
// then we should use neither, just the first, or both deviceInstance
// parameters, respectively. If any other number of locks is requested, we
// acquire all of the lockable GPUS.
//
// We cannot simply determine the mask outside of this function and pass in
// the mask, because gpumgrGetDeviceGpuMask requires that we hold the RM API
// lock. Otherwise, SLI rewiring could preempt lock acquisition and render
// the mask invalid.
//
gpuMaskRequested = 0;
if (numLocksNeeded > 2)
{
gpuMaskRequested = GPUS_LOCK_ALL;
}
else
{
if (numLocksNeeded > 0)
{
gpuMaskRequested |= gpumgrGetDeviceGpuMask(deviceInstance1);
}
if (numLocksNeeded > 1)
{
gpuMaskRequested |= gpumgrGetDeviceGpuMask(deviceInstance2);
}
}
//
// The gpuMask parameter to rmGpuGroupLockAcquire is both input and output,
// so we have to copy in what we want here to make comparisons later.
//
gpuMaskAcquired = gpuMaskRequested;
if (gpuMaskRequested != 0)
{
status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK,
GPUS_LOCK_FLAGS_NONE,
RM_LOCK_MODULES_GPU_OPS, &gpuMaskAcquired);
}
acquiredLocks->gpuMask = gpuMaskAcquired;
//
// If we cannot acquire all the locks requested, we release all the locks
// we *were* able to get and bail out here. There is never a safe way to
// proceed with a GPU ops function with fewer locks than requested. If there
// was a safe way to proceed, the client should have asked for fewer locks
// in the first place.
//
// That said, callers sometimes want "all available GPUs", and then the call
// to rmGpuGroupLockAcquire will mask off invalid GPUs for us. Hence the
// exception for GPUS_LOCK_ALL.
//
if (gpuMaskAcquired != gpuMaskRequested && gpuMaskRequested != GPUS_LOCK_ALL)
{
status = NV_ERR_INVALID_LOCK_STATE;
}
if (status != NV_OK)
{
_nvGpuOpsLocksRelease(acquiredLocks);
}
return status;
}
static NV_STATUS _nvGpuOpsLocksAcquireAll(NvU32 rmApiLockFlags,
NvHandle hClient, RsClient **ppClient,
nvGpuOpsLockSet *acquiredLocks)
{
return _nvGpuOpsLocksAcquire(rmApiLockFlags, hClient, ppClient, 3, 0, 0, acquiredLocks);
}
static NV_STATUS nvGpuOpsCreateClient(RM_API *pRmApi, NvHandle *hClient)
{
NV_STATUS status;
RS_SHARE_POLICY sharePolicy;
*hClient = NV01_NULL_OBJECT;
status = pRmApi->Alloc(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT,
hClient, NV01_ROOT, hClient, sizeof(*hClient));
if (status != NV_OK)
{
return status;
}
// Override default system share policy. Prohibit sharing of any and all
// objects owned by this client.
portMemSet(&sharePolicy, 0, sizeof(sharePolicy));
sharePolicy.type = RS_SHARE_TYPE_ALL;
sharePolicy.action = RS_SHARE_ACTION_FLAG_REVOKE;
RS_ACCESS_MASK_ADD(&sharePolicy.accessMask, RS_ACCESS_DUP_OBJECT);
status = pRmApi->Share(pRmApi, *hClient, *hClient, &sharePolicy);
if (status != NV_OK)
{
pRmApi->Free(pRmApi, *hClient, *hClient);
}
return status;
}
NV_STATUS nvGpuOpsCreateSession(struct gpuSession **session)
{
struct gpuSession *gpuSession = NULL;
NV_STATUS status;
RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL);
PORT_MEM_ALLOCATOR *pAlloc = portMemAllocatorGetGlobalNonPaged();
gpuSession = portMemAllocNonPaged(sizeof(*gpuSession));
if (gpuSession == NULL)
return NV_ERR_NO_MEMORY;
portMemSet(gpuSession, 0, sizeof(*gpuSession));
status = nvGpuOpsCreateClient(pRmApi, &gpuSession->handle);
if (status != NV_OK)
{
portMemFree(gpuSession);
return status;
}
gpuSession->devices = NULL;
gpuSession->btreeLock = portSyncRwLockCreate(pAlloc);
*session = (gpuSession);
return status;
}
NV_STATUS nvGpuOpsDestroySession(struct gpuSession *session)
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL);
if (!session)
return NV_OK;
// Sanity Check: There should not be any attached devices with the session!
NV_ASSERT(!session->devices);
// freeing session will free everything under it
pRmApi->Free(pRmApi, session->handle, session->handle);
portSyncRwLockDestroy(session->btreeLock);
portMemFree(session);
return NV_OK;
}
static void *gpuBar0BaseAddress(OBJGPU *pGpu)
{
DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0);
NV_ASSERT(pMapping);
return pMapping->gpuNvAddr;
}
static void eccErrorCallback(void *pArg, void *pData, NvHandle hEvent,
NvU32 data, NvU32 status)
{
subDeviceDesc *rmSubDevice = (subDeviceDesc *)pArg;
NV_ASSERT(rmSubDevice);
rmSubDevice->eccErrorNotifier = NV_TRUE;
}
static NvBool deviceNeedsDummyAlloc(struct gpuDevice *device)
{
// The dummy mapping is needed so the client can issue a read to flush out
// any CPU BAR1 PCIE writes prior to updating GPPUT. This is only needed
// when the bus is non-coherent and when not in ZeroFB (where there can't be
// any BAR1 mappings).
return device->info.sysmemLink < UVM_LINK_TYPE_NVLINK_2 && !device->fbInfo.bZeroFb;
}
static NV_STATUS nvGpuOpsVaSpaceRetainDummyAlloc(struct gpuAddressSpace *vaSpace)
{
struct gpuDevice *device;
NV_STATUS status = NV_OK;
gpuAllocInfo allocInfo = {0};
struct allocFlags flags = {0};
device = vaSpace->device;
NV_ASSERT(device);
NV_ASSERT(deviceNeedsDummyAlloc(device));
if (vaSpace->dummyGpuAlloc.refCount > 0)
goto done;
// When HCC is enabled the allocation happens in CPR vidmem
// The dummy BAR1 pointer read mechanism won't work when
// BAR1 access to CPR vidmem is sealed off as part of HCC
// production settings. Creating dummy BAR1 mapping can
// also be avoided when doorbell is in BAR1.
flags.bGetKernelVA = NV_FALSE;
status = nvGpuOpsGpuMalloc(vaSpace,
NV_FALSE,
NV_GPU_SMALL_PAGESIZE,
&vaSpace->dummyGpuAlloc.gpuAddr,
flags,
&allocInfo);
if (status != NV_OK)
return status;
status = nvGpuOpsMemoryCpuMap(vaSpace,
vaSpace->dummyGpuAlloc.gpuAddr,
NV_GPU_SMALL_PAGESIZE,
(void **)&vaSpace->dummyGpuAlloc.cpuAddr,
PAGE_SIZE_DEFAULT);
if (status != NV_OK)
nvGpuOpsMemoryFree(vaSpace, vaSpace->dummyGpuAlloc.gpuAddr);
done:
if (status == NV_OK)
{
++vaSpace->dummyGpuAlloc.refCount;
NV_ASSERT(vaSpace->dummyGpuAlloc.gpuAddr);
NV_ASSERT(vaSpace->dummyGpuAlloc.cpuAddr);
}
return status;
}
static void nvGpuOpsVaSpaceReleaseDummyAlloc(struct gpuAddressSpace *vaSpace)
{
NV_ASSERT(deviceNeedsDummyAlloc(vaSpace->device));
NV_ASSERT(vaSpace->dummyGpuAlloc.refCount != 0);
if (--vaSpace->dummyGpuAlloc.refCount > 0)
return;
if (vaSpace->dummyGpuAlloc.cpuAddr)
nvGpuOpsMemoryCpuUnMap(vaSpace, (void *)vaSpace->dummyGpuAlloc.cpuAddr);
if (vaSpace->dummyGpuAlloc.gpuAddr)
nvGpuOpsMemoryFree(vaSpace, vaSpace->dummyGpuAlloc.gpuAddr);
vaSpace->dummyGpuAlloc.cpuAddr = NULL;
vaSpace->dummyGpuAlloc.gpuAddr = 0;
}
static NV_STATUS nvGpuOpsDisableVaSpaceChannels(struct gpuAddressSpace *vaSpace)
{
NV_STATUS status = NV_OK;
OBJVASPACE *pVAS = NULL;
Device *pDevice;
RsClient *pClient;
RS_ORDERED_ITERATOR it;
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS disableParams = {0};
if (vaSpace == NULL)
return NV_ERR_INVALID_ARGUMENT;
status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, &pClient);
if (status != NV_OK)
return status;
status = deviceGetByHandle(pClient, vaSpace->device->handle, &pDevice);
if (status != NV_OK)
return status;
GPU_RES_SET_THREAD_BC_STATE(pDevice);
status = vaspaceGetByHandleOrDeviceDefault(pClient,
vaSpace->device->handle,
vaSpace->handle,
&pVAS);
if ((status != NV_OK) || (pVAS == NULL))
return NV_ERR_INVALID_ARGUMENT;
// Stop all channels under the VAS, but leave them bound.
it = kchannelGetIter(pClient, RES_GET_REF(pDevice));
while (clientRefOrderedIterNext(pClient, &it))
{
KernelChannel *pKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel);
NV_ASSERT_OR_ELSE(pKernelChannel != NULL, continue);
if (pKernelChannel->pVAS != pVAS)
continue;
NV_ASSERT_OR_RETURN(disableParams.numChannels < NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES, NV_ERR_NOT_SUPPORTED);
disableParams.hClientList[disableParams.numChannels] = RES_GET_CLIENT_HANDLE(pKernelChannel);
disableParams.hChannelList[disableParams.numChannels] = RES_GET_HANDLE(pKernelChannel);
disableParams.numChannels++;
}
if (disableParams.numChannels == 0)
return status;
disableParams.bDisable = NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE;
status = pRmApi->Control(pRmApi,
vaSpace->device->session->handle,
vaSpace->device->subhandle,
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS,
&disableParams,
sizeof(disableParams));
return status;
}
static NV_STATUS nvGpuOpsEnableVaSpaceChannels(struct gpuAddressSpace *vaSpace)
{
NV_STATUS status = NV_OK;
OBJVASPACE *pVAS = NULL;
Device *pDevice;
RsClient *pClient;
RS_ORDERED_ITERATOR it;
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS disableParams = {0};
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
if (vaSpace == NULL)
return NV_ERR_INVALID_ARGUMENT;
status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, &pClient);
if (status != NV_OK)
return status;
status = deviceGetByHandle(pClient, vaSpace->device->handle, &pDevice);
if (status != NV_OK)
return status;
GPU_RES_SET_THREAD_BC_STATE(pDevice);
status = vaspaceGetByHandleOrDeviceDefault(pClient,
vaSpace->device->handle,
vaSpace->handle,
&pVAS);
if ((status != NV_OK) || (pVAS == NULL))
return NV_ERR_INVALID_ARGUMENT;
it = kchannelGetIter(pClient, RES_GET_REF(pDevice));
while (clientRefOrderedIterNext(pClient, &it))
{
KernelChannel *pKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel);
NV_ASSERT_OR_ELSE(pKernelChannel != NULL, continue);
if (pKernelChannel->pVAS != pVAS)
continue;
NV_ASSERT_OR_RETURN(disableParams.numChannels < NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES, NV_ERR_NOT_SUPPORTED);
disableParams.hClientList[disableParams.numChannels] = RES_GET_CLIENT_HANDLE(pKernelChannel);
disableParams.hChannelList[disableParams.numChannels] = RES_GET_HANDLE(pKernelChannel);
disableParams.numChannels++;
}
if (disableParams.numChannels == 0)
return status;
disableParams.bDisable = NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE;
status = pRmApi->Control(pRmApi,
vaSpace->device->session->handle,
vaSpace->device->subhandle,
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS,
&disableParams,
sizeof(disableParams));
return status;
}
// Differentiate between different MIG instances.
static NvU64 makeDeviceDescriptorKey(const struct gpuDevice *device)
{
NvU64 key = device->deviceInstance;
NvU64 swizzid = device->info.smcSwizzId;
if (device->info.smcEnabled)
key |= (swizzid << 32);
return key;
}
static NV_STATUS nvGpuOpsRmDeviceCreate(struct gpuDevice *device)
{
NV_STATUS status;
NV0080_ALLOC_PARAMETERS nv0080AllocParams = { 0 };
deviceDesc *rmDevice = NULL;
struct gpuSession *session = device->session;
RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL);
PORT_MEM_ALLOCATOR *pAlloc = portMemAllocatorGetGlobalNonPaged();
NvU64 deviceKey = makeDeviceDescriptorKey(device);
OBJGPU *pGpu;
// Find the existing rmDevice.
// Otherwise, allocate an rmDevice.
portSyncRwLockAcquireRead(session->btreeLock);
status = findDescriptor(session->devices, deviceKey, (void**)&rmDevice);
portSyncRwLockReleaseRead(session->btreeLock);
if (status == NV_OK)
{
NV_ASSERT(rmDevice);
device->rmDevice = rmDevice;
device->handle = rmDevice->deviceHandle;
return NV_OK;
}
rmDevice = portMemAllocNonPaged(sizeof(*rmDevice));
if (rmDevice == NULL)
return NV_ERR_INSUFFICIENT_RESOURCES;
portMemSet(rmDevice, 0, sizeof(*rmDevice));
nv0080AllocParams.deviceId = device->deviceInstance;
nv0080AllocParams.hClientShare = session->handle;
device->handle = NV01_NULL_OBJECT;
status = pRmApi->Alloc(pRmApi,
session->handle,
session->handle,
&device->handle,
NV01_DEVICE_0,
&nv0080AllocParams,
sizeof(nv0080AllocParams));
if (status != NV_OK)
goto cleanup_device_desc;
device->rmDevice = rmDevice;
rmDevice->deviceHandle = device->handle;
rmDevice->subDevices = NULL;
rmDevice->subDeviceCount = 0;
portSyncRwLockAcquireWrite(session->btreeLock);
status = trackDescriptor(&session->devices, deviceKey, rmDevice);
portSyncRwLockReleaseWrite(session->btreeLock);
if (status != NV_OK)
goto cleanup_device;
// TODO: Acquired because CliGetGpuContext expects RMAPI lock. Necessary?
status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS);
if (status != NV_OK)
goto cleanup_device;
status = CliSetGpuContext(session->handle, device->handle, &pGpu, NULL);
rmapiLockRelease();
if (status != NV_OK)
goto cleanup_device;
rmDevice->arch = gpuGetChipArch(pGpu);
rmDevice->implementation = gpuGetChipImpl(pGpu);
rmDevice->btreeLock = portSyncRwLockCreate(pAlloc);
return NV_OK;
cleanup_device:
pRmApi->Free(pRmApi, session->handle, device->handle);
cleanup_device_desc:
portMemFree(rmDevice);
return status;
}