Sleigh vector move operation

[astrelsky]

Is your feature request related to a problem? Please describe.
I'm always frustrated when I encounter vectorized code and the decompiler either spews a bunch of nonsense, warns about unimplemented instructions, or emits a placeholder pcodeop.

Describe the solution you'd like
A special operation, or set of operations, which would tell the decompiler that it may use a "best fit" sized varnode for the operation.

Additional context
Some of the AVX instructions are problematic whether it be they are missing, not decoded, unimplemented or using placeholders.

[ghidracadabra]

How to best handle this situation in general is something we're actively thinking about. We would like to have both accurate emulation and understandable decompilation. There's some related discussion in #4476.

The decompiler does have the ability to split vector registers into independent varnodes in certain cases (based on the vector_lane_sizes attribute in a .pspec file). "Complicated" operations, such as shuffles or various permutations, can be problematic, and of course if there's no associated pcode the decompiler doesn't have much to go on.

If you encounter AVX instructions that are missing or decoding incorrectly please let us know, unless they're AVX-512. We already know about those. 😄

[astrelsky]

They are indeed AVX-512.

[astrelsky]

@ghidracadabra I was thinking more along the lines of new pcodeops specifically for common parallel instructions. In my opinion the vector lane registers is an incomplete approach since the registers can be used in non vector instructions and when used there is nothing to tell the decompiler that the register is indeed being used in a vector instruction. This leaves both guesswork and room for error. Having something as simple as parallel(ADD, output, input1, input2, op size, full data size) (crude example) could go a long way. It is explicitly informing both the decompiler and the pcode emulator of what it is doing so it can be handled accordingly.

While this still wouldn't help much for complex operations I still think this could go a long way for improving this area.

[ghidracadabra]

@astrelsky We've considered something like that - it would also make writing the sleigh implementations of vector ops less painful and error-prone. It might be useful for the decompiler as well. There are some complications given the fact that instructions with a natural lane size are often mixed with instructions which are "lane agnostic" (such as bitwise instructions) and instructions which don't really respect lane sizes (like the shuffles or permutes mentioned above). Discussions are ongoing...