This is a simple proof of concept CPU made solely by myself. There might be still some bugs floating around.
- 8bit Data Bus
- 16bit Data Address Bus
- 8bit I/O Address Bus
- 1 General Purpose, 1 Special Purpose Register
- Conditional / Unconditional Jump
- Indirect Addressing
- Zero Page Addressing
- 4 function ALU
- Memory-Mapped I/O (Separate Address)
- Update Emulator code to reflect the changes in Logisim-Evolution circuit
- Enhance & clean-up the assembler
