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Automatic-abstract-model-computation-from-Verilog-design-descriptions

What is abstraction?

it is process of hiding implementation details and only showing the functionality to the user. Abstraction focus on what the object does instead of how it does. It is achieved by using Abstract class and Interface. abstract methods (methods without body, cannot be static and final), interface must implemented and abstract classes must be extended by regular classes in order to achieve abstraction

Why is Abstraction necessary?

Due to the complexity of life, abstraction is necessary. Complex systems must be simplified for people to understand and use them. To understand this in simple form. Let us take an example of 8-Bit Counter. 8-Bit Counter will count from 0 to 255. Let us assume that this design is a bit complicated. To make this design simpler we have to do abstraction. This can be done by introducing new states in between the counter or reducing the bit width. The new design/Abstract model will count from 0 to 127, and then 127 to 255. This can be easily visualized in the following diagram:

image

How to automate the abstraction of verilog models

Reducing the Bit width

Removing the same registers

Abstraction of verilog variables

Abstraction of verilog constants

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