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2023.2 OFS Release for Intel Agilex 7 PCIe Attach Reference Shells (ofs-2023.2)

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@cohensus cohensus released this 16 Sep 00:16

OFS 2023.2

Summary: OFS 2023.2 Release for Intel® Agilex 7 PCIe Attach FPGAs

  • Boards Targeted: Intel® FPGA SmartNIC N6001-PL and Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile)
  • BMC MAX10 NIOS FW Version: 3.15.0 (Intel® FPGA SmartNIC N6001-PL only; AC_BMC_RSU_user_retail_3.15.0_unsigned.rsu binary found in assets tab below)
  • BMC MAX10 Build Version: 3.15.0 (Intel® FPGA SmartNIC N6001-PL only; AC_BMC_RSU_user_retail_3.15.0_unsigned.rsu binary found in assets tab below)
  • Quartus® Prime Pro Version: 23.2
  • Quartus Prime Pro License File: quartus-0.0-0.02iofs-linux.run
  • Quartus Prime Pro Patch: 0.02 patch (oneAPI), 0.19 patch (Ethernet Subsystem) and 0.11 patch (PCIe). Note that patches are found at the bottom of this page in the assets.
  • OS Tested: Red Hat® Enterprise Linux® 8.6
  • OPAE Version: 2.8.0-1
  • Kernel Version: 6.1.41-lts
  • N6001 Bitstream Id: 0x5010202C73B6C4B
  • N6001 PR Interface Id: 921c7ed8-eb79-52b0-85e0-a96c2dc0f926
  • OFS Intel Agilex 7 PCIe Attach FIM Github Branch: https://github.com/OFS/ofs-agx7-pcie-attach/ofs-2023.2
  • OFS N6001 FIM Github Tag: https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2023.2-1
  • OFS FIM_COMMON Github Tag: https://github.com/OFS/ofs-fim-common/releases/tag/ofs-2023.2-1

OPAE SDK:

OPAE SIM:

Driver:

This page provides up-to-date information about the Open FPGA Stack (OFS) for Intel® Agilex® 7 PCIe Attach devices. This project targets the Intel FPGA SmartNIC N6001-PL and Intel Agilex 7 FPGA F-Series Development Kit (2x F-Tile). The summary of OFS framework features are shown below. To find out more about these platforms refer to the documentation below:

OFS FIM Targeting Intel® Agilex®7 PCIe Attach (P-tile, E-tile)

Key Feature Description
Target OPN AGFB014R24A2E2V
PCIe P-tile PCIe* Gen4x16
Virtualization 5 physical functions/3 virtual functions with ability to expand
Memory 5 DDR Channels:* One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 1200 MHz, 1GB each* Four Fabric DDR4 banks, x32 (no ECC), 1200 MHz, 4GB
Ethernet 2x4x25GbE, 2x4x10GbE or 2x100GbE
Hard Processor System 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals.
Configuration and Board Manageability * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration)
* Platform Controller Management Interface (PMCI) Module for Board Management Controller
Partial Reconfiguration Supported
OneAPI OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime
Software Support * Linux DFL drivers targeting OFS FIMs
* OPAE Software Development Kit* OPAE Tools
Target Board Intel FPGA SmartNIC N6001-PL

OFS FIM Targeting Intel® Agilex®7 PCIe Attach (2xF-tile)

Key Feature Description
Target OPN AGFB027R24C2E2VR2
PCIe P-tile PCIe* Gen4x16 (currently downtrains to Gen4x8 in the ES version of the development kit)
Virtualization 5 physical functions/3 virtual functions with ability to expand
Memory 3 DDR Channels:* One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 2400 MHz, 1GB each* Two Fabric DDR4 banks, x64 (no ECC), 2400 MHz, 8GB
Ethernet 2x4x25GbE
Hard Processor System 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals.
Configuration and Board Manageability * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration)
* Platform Controller Management Interface (PMCI) Module for Board Management Controller
Partial Reconfiguration Supported
OneAPI OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime
Software Support * Linux DFL drivers targeting OFS FIMs
* OPAE Software Development Kit* OPAE Tools
Target Board Intel Agilex 7 FPGA F-Series Development Kit (2x F-Tile)

The OFS hardware framework also provides:

  • Support for unit test simulation (using Synopsys® VCS® or Siemens® Questa simulators)
  • UVM support using Synopsys® VCS®
  • Host exercisers that allow you to test interfaces on the FPGA

The OFS software framework provides:

  • FPGA platform Linux drivers that are being upstreamed to linux.org
  • A programmable software development kit and userspace tools for managing the FPGA

Important: If you would like to begin evaluating the default shell that can be built from this repository, please scroll down to the "assets" accordion button below which contains the FPGA binary/POF/SOF along with the applicable Linux driver and Open Programmable Acceleration Engine (OPAE) software development kit (SDK) packages.

New Updates for ofs-2023.2 Release

  • Upgrade to Quartus Prime Pro version 23.2
  • F-Tile Support
  • Repository has been updated to build both the Intel FPGA SmartNIC N6001-PL and Intel Agilex 7 FPGA F-Series Development Kit (2x F-Tile)
  • The P-Tile/E-tile FIM now targets multiple Ethernet Configurations (10G/25G/100G)
  • New ofss files to enable a variety of build combinations

Known Issues

This table describes the known issues for the 2023.2 OFS Release targeting Intel Agilex 7 PCIe Attach devices.

IDKnown IssuesWorkaroundStatusPlatform Target Affected
14020113416Simulations of Ethernet Subsystem in 10GbE configuration show rx_tvalid in an unknown state upon reset. 10GbE simulation is currently not supportedNoneFixed in a future version of OFS.Intel FPGA SmartNIC N6001-PL
18019768262A Quartus issue is causing intermittent HPS build failures when generating the IP during compilation or simulation.Workaround the failure by targeting a different work directory in your build command.Fixed in a future version of OFS.- F-Series Development Kit (2x F-Tile)
- Intel FPGA SmartNIC N6001-PL
14020225085, 14020221909The following unit tests are not working: he_mem_lb_test, mem_ss_csr_test, mem_ss_rst_test, mem_tg_test and hssi_csr_test.NoneFixed in a future version of OFS.F-Series Development Kit (2x F-Tile)
14020116806Unit test hssi_kpi_test results are invalid and should not be used.NoneFixed in a future version of OFS.- F-Series Development Kit (2x F-Tile)
- Intel FPGA SmartNIC N6001-PL
14020225084The regress_run.py script includes PMCI tests that fail for F-tile PCIe Attach design because PMCI is not included in this design.Ignore PMCI test errors as they do not apply to the F-tile PCIe Attach Design.Fixed in a future version of OFS.- F-Series Development Kit (2x F-Tile)
22015871994AFU Simulation Environment (ASE) for hardware/software co-simulation is not supported with OneAPI.NoneFixed in a future version of OFS.Intel FPGA SmartNIC N6001-PL
22018273793When sending greater than 1400 byte packets upstream to the PCIe subsystem, you should disable the protocol checker in the src/top/top.sv file to prevent packet stalls.NoneFixed in a future version of OFS.Intel FPGA SmartNIC N6001-PL
14020129685The **hssi_loopback** command is currently not supported when FIM Ethernet configuration is 2x100GbE.NoneFixed in a future version of OFS.Intel FPGA SmartNIC N6001-PL
14020221909When running the OPAE command **mem_tg** the maximum transfer rates reported are incorrect even though it indicates the test passes.None. Do not use mem_tg for this releaseFixed in a future version of OFS.-F-Series Development Kit (2x F-Tile)
- Intel FPGA SmartNIC N6001-PL
14018364039The OPAE command **fpgainfo bmc** and **fpgainfo temp** display a "CVL" field that is not utilized by the design.None. Ignore "CVL" listings.Fixed in a future version of OFS.Intel FPGA SmartNIC N6001-PL

Important Notes

The following section provides important information about this release:

IDImportant Notes
-When using the PF/VF configuration tool to reconfigure the PF/VF mux, you must keep at least one physical function and one virtual function on PF0. The tool does not support less than one PF and one VF on PF0. All other PFs and VFs can be removed if desired.
15012246661When enabling cable hotplug IP and ANLT, the E-tile recipe resulting from the ANLT initialization flow is over-written by the hotplug initialization flow. If you require a custom ANLT recipe, then you cannot use hotplug at this time. You can disable hotplug by writing 1 to index-0 of HSSI Hotplug Debug Control Register (offset 0x600B4) followed by a port level reset or analog reset.
15012406417If using the Intel FPGA SmartNIC N6001-PL Platform (SKU2) for evaluation of the OFS release, ensure DIP Switch SW1.4 on the board is set to convey the correct board type or the OPAE commands could display invalid temperature values for an Intel NIC E810 (SKU1) which is not populated on the SKU2 board. For Intel FPGA SmartNIC N6001-PL Platform (SKU2), SW1.4 must be off (pointing towards the PCIe goldfinger). Note that a BMC reset is required if you must flip the switch to the correct setting.

Resolved Issues

This table describes prior known issues resolved in the 2023.2 OFS Release targeting Intel Agilex 7 devices.

IDResolved Issues
14017669281The version of cable hotplug IP in this release supports the VSR (very short route) recipes only.
14019349213he_random_long_test and mmio_stress_test generate mmio_timeout_errors.