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api-shell.c
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api-shell.c
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// Copyright(c) 2018-2022, Intel Corporation
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif // HAVE_CONFIG_H
#ifndef _GNU_SOURCE
#define _GNU_SOURCE
#endif // _GNU_SOURCE
#include <stdio.h>
#include <opae/properties.h>
#include <opae/types_enum.h>
#include "pluginmgr.h"
#include "opae_int.h"
#include "props.h"
#include "multi-port-afu.h"
#include "mock/opae_std.h"
const char *
__OPAE_API__ fpgaErrStr(fpga_result e)
{
switch (e) {
case FPGA_OK:
return "success";
case FPGA_INVALID_PARAM:
return "invalid parameter";
case FPGA_BUSY:
return "resource busy";
case FPGA_EXCEPTION:
return "exception";
case FPGA_NOT_FOUND:
return "not found";
case FPGA_NO_MEMORY:
return "no memory";
case FPGA_NOT_SUPPORTED:
return "not supported";
case FPGA_NO_DRIVER:
return "no driver available";
case FPGA_NO_DAEMON:
return "no fpga daemon running";
case FPGA_NO_ACCESS:
return "insufficient privileges";
case FPGA_RECONF_ERROR:
return "reconfiguration error";
default:
return "unknown error";
}
}
STATIC pthread_mutex_t token_list_lock = PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP;
STATIC opae_wrapped_token token_list_head = {
.prev = &token_list_head,
.next = &token_list_head,
};
opae_wrapped_token *
opae_allocate_wrapped_token(fpga_token token,
const opae_api_adapter_table *adapter)
{
opae_wrapped_token *wtok =
(opae_wrapped_token *)opae_malloc(sizeof(opae_wrapped_token));
if (wtok) {
wtok->magic = OPAE_WRAPPED_TOKEN_MAGIC;
wtok->opae_token = token;
wtok->ref_count = 0;
wtok->prev = wtok->next = NULL;
wtok->adapter_table = (opae_api_adapter_table *)adapter;
opae_upref_wrapped_token(wtok);
}
return wtok;
}
void opae_upref_wrapped_token(opae_wrapped_token *wt)
{
int res;
opae_mutex_lock(res, &token_list_lock);
++wt->ref_count;
if (wt->ref_count == 1) {
OPAE_DBG("token ref count begin %p", wt);
wt->prev = &token_list_head;
wt->next = token_list_head.next;
token_list_head.next->prev = wt;
token_list_head.next = wt;
}
#ifdef LIBOPAE_DEBUG
else {
OPAE_DBG("token ref count up %p, %u", wt, wt->ref_count);
}
#endif // LIBOPAE_DEBUG
opae_mutex_unlock(res, &token_list_lock);
}
fpga_result opae_downref_wrapped_token(opae_wrapped_token *wt)
{
int res;
fpga_result fres = FPGA_OK;
opae_mutex_lock(res, &token_list_lock);
--wt->ref_count;
if (wt->ref_count == 0) {
OPAE_DBG("token ref count end %p", wt);
wt->prev->next = wt->next;
wt->next->prev = wt->prev;
wt->magic = 0;
if (wt->adapter_table->fpgaDestroyToken)
fres = wt->adapter_table->fpgaDestroyToken(
&wt->opae_token);
else
fres = FPGA_NOT_SUPPORTED;
opae_free(wt);
#ifdef LIBOPAE_DEBUG
if ((token_list_head.prev == &token_list_head) &&
(token_list_head.next == &token_list_head)) {
OPAE_DBG("token ref count CLEAN HERE");
}
#endif // LIBOPAE_DEBUG
}
#ifdef LIBOPAE_DEBUG
else {
OPAE_DBG("token ref count down %p, %u", wt, wt->ref_count);
}
#endif // LIBOPAE_DEBUG
opae_mutex_unlock(res, &token_list_lock);
return fres;
}
#ifdef LIBOPAE_DEBUG
uint32_t opae_wrapped_tokens_in_use(void)
{
int res;
uint32_t count = 0;
opae_wrapped_token *wt;
opae_mutex_lock(res, &token_list_lock);
for (wt = token_list_head.next ;
wt != &token_list_head ;
wt = wt->next) {
++count;
OPAE_DBG("token ref count %p, %u LEAKED",
wt, wt->ref_count);
}
opae_mutex_unlock(res, &token_list_lock);
return count;
}
#endif // LIBOPAE_DEBUG
opae_wrapped_handle *
opae_allocate_wrapped_handle(opae_wrapped_token *wt, fpga_handle opae_handle,
opae_api_adapter_table *adapter)
{
opae_wrapped_handle *whan =
(opae_wrapped_handle *)opae_malloc(sizeof(opae_wrapped_handle));
if (whan) {
whan->magic = OPAE_WRAPPED_HANDLE_MAGIC;
whan->wrapped_token = wt;
whan->opae_handle = opae_handle;
whan->adapter_table = adapter;
whan->parent = NULL;
whan->child_next = NULL;
opae_upref_wrapped_token(wt);
}
return whan;
}
opae_wrapped_event_handle *
opae_allocate_wrapped_event_handle(fpga_event_handle opae_event_handle,
opae_api_adapter_table *adapter)
{
pthread_mutexattr_t mattr;
opae_wrapped_event_handle *wevent = (opae_wrapped_event_handle *)opae_malloc(
sizeof(opae_wrapped_event_handle));
if (wevent) {
if (pthread_mutexattr_init(&mattr)) {
OPAE_ERR("pthread_mutexattr_init() failed");
goto out_free;
}
if (pthread_mutexattr_settype(&mattr,
PTHREAD_MUTEX_RECURSIVE)) {
OPAE_ERR("pthread_mutexattr_settype() failed");
goto out_destroy;
}
if (pthread_mutex_init(&wevent->lock, &mattr)) {
OPAE_ERR("pthread_mutex_init() failed");
goto out_destroy;
}
pthread_mutexattr_destroy(&mattr);
wevent->magic = OPAE_WRAPPED_EVENT_HANDLE_MAGIC;
wevent->flags = 0;
wevent->opae_event_handle = opae_event_handle;
wevent->adapter_table = adapter;
}
return wevent;
out_destroy:
pthread_mutexattr_destroy(&mattr);
out_free:
opae_free(wevent);
return NULL;
}
opae_wrapped_object *
opae_allocate_wrapped_object(fpga_object opae_object,
opae_api_adapter_table *adapter)
{
opae_wrapped_object *wobj =
(opae_wrapped_object *)opae_malloc(sizeof(opae_wrapped_object));
if (wobj) {
wobj->magic = OPAE_WRAPPED_OBJECT_MAGIC;
wobj->opae_object = opae_object;
wobj->adapter_table = adapter;
}
return wobj;
}
fpga_result __OPAE_API__ fpgaInitialize(const char *config_file)
{
return opae_plugin_mgr_initialize(config_file) ? FPGA_EXCEPTION
: FPGA_OK;
}
fpga_result __OPAE_API__ fpgaFinalize(void)
{
return opae_plugin_mgr_finalize_all() ? FPGA_EXCEPTION
: FPGA_OK;
}
fpga_result __OPAE_API__ fpgaOpen(fpga_token token, fpga_handle *handle,
int flags)
{
fpga_result res;
opae_wrapped_token *wrapped_token;
fpga_token_header *token_hdr;
fpga_handle opae_handle = NULL;
opae_wrapped_handle *wrapped_handle;
wrapped_token = opae_validate_wrapped_token(token);
ASSERT_NOT_NULL(wrapped_token);
ASSERT_NOT_NULL(handle);
ASSERT_NOT_NULL_RESULT(wrapped_token->adapter_table->fpgaOpen,
FPGA_NOT_SUPPORTED);
ASSERT_NOT_NULL_RESULT(wrapped_token->adapter_table->fpgaClose,
FPGA_NOT_SUPPORTED);
if (flags & FPGA_OPEN_HAS_PARENT_AFU) {
ASSERT_NOT_NULL(*handle);
opae_handle = *handle;
}
res = wrapped_token->adapter_table->fpgaOpen(wrapped_token->opae_token,
&opae_handle, flags);
ASSERT_RESULT(res);
wrapped_handle = opae_allocate_wrapped_handle(
wrapped_token, opae_handle, wrapped_token->adapter_table);
if (!wrapped_handle) {
OPAE_ERR("malloc failed");
wrapped_token->adapter_table->fpgaClose(opae_handle);
return FPGA_NO_MEMORY;
}
token_hdr = (fpga_token_header *)wrapped_token->opae_token;
if (token_hdr->objtype == FPGA_ACCELERATOR) {
res = afu_open_children(wrapped_handle);
if (res != FPGA_OK) {
// Close any children that are open
afu_close_children(wrapped_handle);
// Close parent due to failure with child
if (wrapped_handle->adapter_table->fpgaClose)
wrapped_handle->adapter_table->fpgaClose(
wrapped_handle->opae_handle);
opae_destroy_wrapped_handle(wrapped_handle);
return res;
}
}
*handle = wrapped_handle;
return FPGA_OK;
}
fpga_result __OPAE_API__ fpgaGetChildren(fpga_handle handle,
uint32_t max_children,
fpga_handle *children,
uint32_t *num_children)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL(num_children);
if ((max_children > 0) && !children) {
OPAE_ERR("max_children > 0 with NULL children");
return FPGA_INVALID_PARAM;
}
*num_children = 0;
// Is handle a child? If so, it has no children.
if (wrapped_handle->parent)
return FPGA_OK;
// Children are already open
opae_wrapped_handle *wrapped_child = wrapped_handle->child_next;
while (wrapped_child) {
if (*num_children < max_children)
children[*num_children] = wrapped_child;
*num_children += 1;
wrapped_child = wrapped_child->child_next;
}
return FPGA_OK;
}
fpga_result __OPAE_API__ fpgaClose(fpga_handle handle)
{
fpga_result res;
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaClose,
FPGA_NOT_SUPPORTED);
res = wrapped_handle->adapter_table->fpgaClose(
wrapped_handle->opae_handle);
afu_close_children(wrapped_handle);
opae_destroy_wrapped_handle(wrapped_handle);
return res;
}
fpga_result __OPAE_API__ fpgaReset(fpga_handle handle)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaReset,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaReset(
wrapped_handle->opae_handle);
}
STATIC opae_wrapped_token *
opae_get_parent_token(opae_wrapped_token *child)
{
int mres = 0;
opae_wrapped_token *p;
opae_wrapped_token *parent = NULL;
fpga_token_header *child_hdr;
fpga_token_header *parent_hdr;
child_hdr = (fpga_token_header *)child->opae_token;
if (opae_mutex_lock(mres, &token_list_lock))
return NULL;
for (p = token_list_head.next ;
p != &token_list_head ;
p = p->next) {
parent_hdr = (fpga_token_header *)p->opae_token;
if (fpga_is_parent_child(parent_hdr, child_hdr)) {
parent = p;
opae_upref_wrapped_token(parent);
break;
}
}
opae_mutex_unlock(mres, &token_list_lock);
return parent;
}
fpga_result __OPAE_API__ fpgaGetPropertiesFromHandle(fpga_handle handle,
fpga_properties *prop)
{
fpga_result res;
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
struct _fpga_properties *p;
opae_wrapped_token *wrapped_parent;
int err;
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL(prop);
ASSERT_NOT_NULL_RESULT(
wrapped_handle->adapter_table->fpgaGetPropertiesFromHandle,
FPGA_NOT_SUPPORTED);
res = wrapped_handle->adapter_table->fpgaGetPropertiesFromHandle(
wrapped_handle->opae_handle, prop);
ASSERT_RESULT(res);
p = opae_validate_and_lock_properties(*prop);
ASSERT_NOT_NULL(p);
wrapped_parent = opae_get_parent_token(wrapped_handle->wrapped_token);
if (wrapped_parent) {
SET_FIELD_VALID(p, FPGA_PROPERTY_PARENT);
p->parent = wrapped_parent;
}
opae_mutex_unlock(err, &p->lock);
return res;
}
fpga_result __OPAE_API__ fpgaGetProperties(fpga_token token,
fpga_properties *prop)
{
fpga_result res = FPGA_OK;
opae_wrapped_token *wrapped_token = opae_validate_wrapped_token(token);
ASSERT_NOT_NULL(prop);
if (!token) {
fpga_properties pr;
pr = opae_properties_create();
if (!pr) {
OPAE_ERR("malloc failed");
return FPGA_NO_MEMORY;
}
*prop = pr;
} else {
struct _fpga_properties *p;
opae_wrapped_token *wrapped_parent;
int err;
ASSERT_NOT_NULL(wrapped_token);
ASSERT_NOT_NULL_RESULT(
wrapped_token->adapter_table->fpgaGetProperties,
FPGA_NOT_SUPPORTED);
res = wrapped_token->adapter_table->fpgaGetProperties(
wrapped_token->opae_token, prop);
ASSERT_RESULT(res);
p = opae_validate_and_lock_properties(*prop);
ASSERT_NOT_NULL(p);
wrapped_parent = opae_get_parent_token(wrapped_token);
if (wrapped_parent) {
SET_FIELD_VALID(p, FPGA_PROPERTY_PARENT);
p->parent = wrapped_parent;
}
opae_mutex_unlock(err, &p->lock);
}
return res;
}
fpga_result __OPAE_API__ fpgaUpdateProperties(fpga_token token,
fpga_properties prop)
{
fpga_result res;
struct _fpga_properties *p;
int err;
opae_wrapped_token *wrapped_token = opae_validate_wrapped_token(token);
opae_wrapped_token *wrapped_parent = NULL;
ASSERT_NOT_NULL(wrapped_token);
ASSERT_NOT_NULL_RESULT(
wrapped_token->adapter_table->fpgaUpdateProperties,
FPGA_NOT_SUPPORTED);
// If the input properties already has a parent token
// set, then it will be wrapped.
p = opae_validate_and_lock_properties(prop);
ASSERT_NOT_NULL(p);
if (FIELD_VALID(p, FPGA_PROPERTY_PARENT)) {
wrapped_parent = opae_validate_wrapped_token(p->parent);
if (wrapped_parent) {
opae_destroy_wrapped_token(wrapped_parent);
}
CLEAR_FIELD_VALID(p, FPGA_PROPERTY_PARENT);
p->parent = NULL;
}
res = wrapped_token->adapter_table->fpgaUpdateProperties(
wrapped_token->opae_token, prop);
if (res != FPGA_OK) {
opae_mutex_unlock(err, &p->lock);
return res;
}
wrapped_parent = opae_get_parent_token(wrapped_token);
if (wrapped_parent) {
SET_FIELD_VALID(p, FPGA_PROPERTY_PARENT);
p->parent = wrapped_parent;
}
opae_mutex_unlock(err, &p->lock);
return res;
}
fpga_result __OPAE_API__ fpgaWriteMMIO64(fpga_handle handle, uint32_t mmio_num,
uint64_t offset, uint64_t value)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaWriteMMIO64,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaWriteMMIO64(
wrapped_handle->opae_handle, mmio_num, offset, value);
}
fpga_result __OPAE_API__ fpgaReadMMIO64(fpga_handle handle, uint32_t mmio_num,
uint64_t offset, uint64_t *value)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaReadMMIO64,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaReadMMIO64(
wrapped_handle->opae_handle, mmio_num, offset, value);
}
fpga_result __OPAE_API__ fpgaWriteMMIO32(fpga_handle handle, uint32_t mmio_num,
uint64_t offset, uint32_t value)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaWriteMMIO32,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaWriteMMIO32(
wrapped_handle->opae_handle, mmio_num, offset, value);
}
fpga_result __OPAE_API__ fpgaReadMMIO32(fpga_handle handle, uint32_t mmio_num,
uint64_t offset, uint32_t *value)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaReadMMIO32,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaReadMMIO32(
wrapped_handle->opae_handle, mmio_num, offset, value);
}
fpga_result __OPAE_API__ fpgaWriteMMIO512(fpga_handle handle,
uint32_t mmio_num, uint64_t offset, const void *value)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaWriteMMIO512,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaWriteMMIO512(
wrapped_handle->opae_handle, mmio_num, offset, value);
}
fpga_result __OPAE_API__ fpgaMapMMIO(fpga_handle handle, uint32_t mmio_num,
uint64_t **mmio_ptr)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaMapMMIO,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaMapMMIO(
wrapped_handle->opae_handle, mmio_num, mmio_ptr);
}
fpga_result __OPAE_API__ fpgaUnmapMMIO(fpga_handle handle, uint32_t mmio_num)
{
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaUnmapMMIO,
FPGA_NOT_SUPPORTED);
return wrapped_handle->adapter_table->fpgaUnmapMMIO(
wrapped_handle->opae_handle, mmio_num);
}
typedef struct _opae_enumeration_context {
// <verbatim from fpgaEnumerate>
const fpga_properties *filters;
uint32_t num_filters;
fpga_token *wrapped_tokens;
uint32_t max_wrapped_tokens;
uint32_t *num_matches;
// </verbatim from fpgaEnumerate>
fpga_token *adapter_tokens;
uint32_t num_wrapped_tokens;
uint32_t errors;
} opae_enumeration_context;
static int opae_enumerate(const opae_api_adapter_table *adapter, void *context)
{
opae_enumeration_context *ctx = (opae_enumeration_context *)context;
fpga_result res;
uint32_t num_matches = 0;
uint32_t i;
uint32_t space_remaining;
space_remaining = ctx->max_wrapped_tokens - ctx->num_wrapped_tokens;
if (ctx->wrapped_tokens && !space_remaining)
return OPAE_ENUM_STOP;
if (!adapter->fpgaEnumerate) {
OPAE_MSG("NULL fpgaEnumerate in adapter \"%s\"",
adapter->plugin.path);
return OPAE_ENUM_CONTINUE;
}
res = adapter->fpgaEnumerate(ctx->filters, ctx->num_filters,
ctx->adapter_tokens, space_remaining,
&num_matches);
if (res != FPGA_OK) {
OPAE_DBG("fpgaEnumerate() failed for \"%s\": %s",
adapter->plugin.path, fpgaErrStr(res));
switch (res) {
case FPGA_NO_DRIVER: // Fall through
case FPGA_NOT_FOUND:
return OPAE_ENUM_CONTINUE;
default:
break;
}
++ctx->errors;
return OPAE_ENUM_CONTINUE;
}
*ctx->num_matches += num_matches;
if (!ctx->adapter_tokens) {
// requesting token count, only.
return OPAE_ENUM_CONTINUE;
}
if (space_remaining > num_matches)
space_remaining = num_matches;
for (i = 0; i < space_remaining; ++i) {
opae_wrapped_token *wt = opae_allocate_wrapped_token(
ctx->adapter_tokens[i], adapter);
if (!wt) {
++ctx->errors;
return OPAE_ENUM_STOP;
}
if (ctx->wrapped_tokens) {
ctx->wrapped_tokens[ctx->num_wrapped_tokens++] = wt;
} else {
opae_destroy_wrapped_token(wt);
}
}
return ctx->num_wrapped_tokens == ctx->max_wrapped_tokens
? OPAE_ENUM_STOP
: OPAE_ENUM_CONTINUE;
}
fpga_result __OPAE_API__ fpgaEnumerate(const fpga_properties *filters,
uint32_t num_filters, fpga_token *tokens, uint32_t max_tokens,
uint32_t *num_matches)
{
fpga_result res = FPGA_EXCEPTION;
fpga_token *adapter_tokens = NULL;
opae_enumeration_context enum_context;
typedef struct _parent_token_fixup {
struct _parent_token_fixup *next;
fpga_properties prop;
opae_wrapped_token *wrapped_token;
} parent_token_fixup;
parent_token_fixup *ptf_list = NULL;
uint32_t i;
ASSERT_NOT_NULL(num_matches);
if ((max_tokens > 0) && !tokens) {
OPAE_ERR("max_tokens > 0 with NULL tokens");
return FPGA_INVALID_PARAM;
}
if ((num_filters > 0) && !filters) {
OPAE_ERR("num_filters > 0 with NULL filters");
return FPGA_INVALID_PARAM;
}
if ((num_filters == 0) && (filters != NULL)) {
OPAE_ERR("num_filters == 0 with non-NULL filters");
return FPGA_INVALID_PARAM;
}
*num_matches = 0;
enum_context.filters = filters;
enum_context.num_filters = num_filters;
enum_context.wrapped_tokens = tokens;
enum_context.max_wrapped_tokens = max_tokens;
enum_context.num_matches = num_matches;
if (tokens) {
adapter_tokens =
(fpga_token *)opae_calloc(max_tokens, sizeof(fpga_token));
if (!adapter_tokens) {
OPAE_ERR("out of memory");
return FPGA_NO_MEMORY;
}
}
enum_context.adapter_tokens = adapter_tokens;
enum_context.num_wrapped_tokens = 0;
enum_context.errors = 0;
// If any of the input filters has a parent token set,
// then it will be wrapped. We need to unwrap it here,
// then re-wrap below.
for (i = 0; i < num_filters; ++i) {
int err;
struct _fpga_properties *p =
opae_validate_and_lock_properties(filters[i]);
if (!p) {
OPAE_ERR("Invalid input filter");
res = FPGA_INVALID_PARAM;
goto out_free_tokens;
}
if (FIELD_VALID(p, FPGA_PROPERTY_PARENT)) {
parent_token_fixup *fixup;
opae_wrapped_token *wrapped_parent =
opae_validate_wrapped_token(p->parent);
if (!wrapped_parent) {
OPAE_ERR("Invalid wrapped parent in filter");
res = FPGA_INVALID_PARAM;
opae_mutex_unlock(err, &p->lock);
goto out_free_tokens;
}
fixup = (parent_token_fixup *)opae_malloc(
sizeof(parent_token_fixup));
if (!fixup) {
OPAE_ERR("malloc failed");
res = FPGA_NO_MEMORY;
opae_mutex_unlock(err, &p->lock);
goto out_free_tokens;
}
fixup->next = NULL;
fixup->prop = filters[i];
fixup->wrapped_token = wrapped_parent;
if (!ptf_list)
ptf_list = fixup;
else {
fixup->next = ptf_list;
ptf_list = fixup;
}
// Set the unwrapped parent token.
p->parent = wrapped_parent->opae_token;
}
opae_mutex_unlock(err, &p->lock);
}
// perform the enumeration.
opae_plugin_mgr_for_each_adapter(opae_enumerate, &enum_context);
res = (enum_context.errors > 0) ? FPGA_EXCEPTION : FPGA_OK;
out_free_tokens:
if (adapter_tokens)
opae_free(adapter_tokens);
// Re-establish any wrapped parent tokens.
while (ptf_list) {
int err;
parent_token_fixup *trash = ptf_list;
struct _fpga_properties *p =
opae_validate_and_lock_properties(trash->prop);
ptf_list = ptf_list->next;
if (p) {
p->parent = trash->wrapped_token;
opae_mutex_unlock(err, &p->lock);
}
opae_free(trash);
}
return res;
}
fpga_result __OPAE_API__ fpgaCloneToken(fpga_token src, fpga_token *dst)
{
fpga_result res;
fpga_result dres = FPGA_OK;
fpga_token cloned_token = NULL;
opae_wrapped_token *wrapped_dst_token;
opae_wrapped_token *wrapped_src_token =
opae_validate_wrapped_token(src);
ASSERT_NOT_NULL(wrapped_src_token);
ASSERT_NOT_NULL(dst);
ASSERT_NOT_NULL_RESULT(wrapped_src_token->adapter_table->fpgaCloneToken,
FPGA_NOT_SUPPORTED);
ASSERT_NOT_NULL_RESULT(
wrapped_src_token->adapter_table->fpgaDestroyToken,
FPGA_NOT_SUPPORTED);
res = wrapped_src_token->adapter_table->fpgaCloneToken(
wrapped_src_token->opae_token, &cloned_token);
ASSERT_RESULT(res);
wrapped_dst_token = opae_allocate_wrapped_token(
cloned_token, wrapped_src_token->adapter_table);
if (!wrapped_dst_token) {
OPAE_ERR("malloc failed");
res = FPGA_NO_MEMORY;
dres = wrapped_src_token->adapter_table->fpgaDestroyToken(
&cloned_token);
}
*dst = wrapped_dst_token;
return res != FPGA_OK ? res : dres;
}
fpga_result __OPAE_API__ fpgaDestroyToken(fpga_token *token)
{
fpga_result res = FPGA_INVALID_PARAM;
opae_wrapped_token *wrapped_token;
ASSERT_NOT_NULL(token);
wrapped_token = opae_validate_wrapped_token(*token);
if (wrapped_token)
res = opae_destroy_wrapped_token(wrapped_token);
return res;
}
fpga_result __OPAE_API__ fpgaGetNumUmsg(fpga_handle handle, uint64_t *value)
{
UNUSED_PARAM(handle);
UNUSED_PARAM(value);
return FPGA_NOT_SUPPORTED;
}
fpga_result __OPAE_API__ fpgaSetUmsgAttributes(fpga_handle handle,
uint64_t value)
{
UNUSED_PARAM(handle);
UNUSED_PARAM(value);
return FPGA_NOT_SUPPORTED;
}
fpga_result __OPAE_API__ fpgaTriggerUmsg(fpga_handle handle, uint64_t value)
{
UNUSED_PARAM(handle);
UNUSED_PARAM(value);
return FPGA_NOT_SUPPORTED;
}
fpga_result __OPAE_API__ fpgaGetUmsgPtr(fpga_handle handle, uint64_t **umsg_ptr)
{
UNUSED_PARAM(handle);
UNUSED_PARAM(umsg_ptr);
return FPGA_NOT_SUPPORTED;
}
fpga_result __OPAE_API__ fpgaPrepareBuffer(fpga_handle handle,
uint64_t len, void **buf_addr, uint64_t *wsid, int flags)
{
fpga_result res;
opae_wrapped_handle *wrapped_handle =
opae_validate_wrapped_handle(handle);
// A special case: allow each plugin to respond FPGA_OK
// when !buf_addr and !len as an indication that
// FPGA_BUF_PREALLOCATED is supported by the plugin.
if (!(flags & FPGA_BUF_PREALLOCATED) || (len > 0)) {
// Assert only if not the special case described above.
ASSERT_NOT_NULL(buf_addr);
}
ASSERT_NOT_NULL(wrapped_handle);
ASSERT_NOT_NULL(wsid);
ASSERT_NOT_NULL_RESULT(wrapped_handle->adapter_table->fpgaPrepareBuffer,
FPGA_NOT_SUPPORTED);
if (wrapped_handle->parent) {
OPAE_ERR("Call fpgaPrepareBuffer() from the parent handle");
return FPGA_NOT_SUPPORTED;
}
res = wrapped_handle->adapter_table->fpgaPrepareBuffer(
wrapped_handle->opae_handle, len, buf_addr, wsid, flags);
if ((res != FPGA_OK) || !buf_addr)
return res;
res = afu_pin_buffer(wrapped_handle, *buf_addr, len, *wsid);
if (res == FPGA_OK)
return FPGA_OK;
// Error! Undo pinning of parent after child failure.