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Using two SPI buses #9
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@wcpettus This is a good question have you found the answer to this yet? Looking at the boards headers I am not seeing any dedicated SPI ports. What are your thoughts? @TsvetanUsunov |
I would love to know the answer. I also tried asking on the forums but never heard anything back: |
Hello |
@wcpettus Just out of curiosity what did you use for your CLK? GPIO6? |
I used GPIO32 - I didn't want to touch GPIO6 since it's one of the reserved for debug only pins that I don't understand. Beyond that my choice for which was MISO/MOSI/CLK/CS were pretty random. |
@wcpettus were you able to get SPI peripheral + ethernet functionality working? |
that's right - I've been using an SPI to communicate with an ADC and ethernet to readout the data |
@wcpettus any chance you'd be willing to share your code? |
I would also love to hear how an external SPI Device can be User with this Board? ( HSPI and VSPI seems Not to be available in the Header) |
Prefaced with the disclaimer that I don't think this is the final code version, but this is what I found digging through old code directories; clearly I should have documented better and answered 3.5 years ago when the original question was fresh (or made the undergrad who was doing the implementation do so :D) This at least seems to work with an ADC, use SPI, and have ethernet functionality.
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Thanks you very much for the example of using Software SPI/bitbanging. |
I'm trying to configure an ESP32-Gateway to talk with an SPI device. I feel I must be missing something about the hardware configuration.
I've started with the SPI_Multiple_Buses example code, but the default pins for VSPI (18,19,23,5) and HSPI (14,12,13,15) are mostly not exposed to the extension headers. Consulting the schematic (I'm using a rev C) I have access to
GPIO 5,16,17,32,33
GPI 34,35,36,39
Debug only 6,7,8,9,10,11
I've verified I can see SPI signals on the 5 pins I have access to, I'm explicitly told to skip the 6 SD-related pins, and the other 4 are input only? That seems like a waste of header real estate, and how can one operate two SPI buses concurrently (alternatively this would limit the number of SS pins for a single SPI bus)?
Probably some trivial ignorance on my part?
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