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git-svn-id: https://openmodelica.org/svn/OpenModelica/trunk@16699 f25d12d1-65f4-0310-ae8a-bbce733d8d8e
OpenModelica · Jul 31, 2013 · 5eb2612 · 5eb2612
1 parent 533b589
commit 5eb2612
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Showing 3 changed files with 183 additions and 183 deletions.
diff --git a/Compiler/Template/SimCodeTV.mo b/Compiler/Template/SimCodeTV.mo
@@ -225,11 +225,11 @@ package SimCode
     end ZEROCROSSINGS_CONTEXT;  
   end Context;
 
-	uniontype HpcOmParInformation
-	  record HPCOMPARINFORMATION
-	    list<list<Integer>> eqsOfLevels;
-	  end HPCOMPARINFORMATION;
-	end HpcOmParInformation;
+  uniontype HpcOmParInformation
+    record HPCOMPARINFORMATION
+      list<list<Integer>> eqsOfLevels;
+    end HPCOMPARINFORMATION;
+  end HpcOmParInformation;
 
   uniontype Variable
     record VARIABLE
@@ -2881,10 +2881,10 @@ end FMI;
 
 package HpcOmSimCode
   function getSimCodeEqByIndex
-	  input list<SimCode.SimEqSystem> iEqs;
-	  input Integer iIdx;
-	  output SimCode.SimEqSystem oEq;
-	end getSimCodeEqByIndex;
+    input list<SimCode.SimEqSystem> iEqs;
+    input Integer iIdx;
+    output SimCode.SimEqSystem oEq;
+  end getSimCodeEqByIndex;
 end HpcOmSimCode;
 
 end SimCodeTV;
diff --git a/SimulationRuntime/c/simulation/simulation_runtime.cpp b/SimulationRuntime/c/simulation/simulation_runtime.cpp
@@ -506,7 +506,7 @@ int startNonInteractiveSimulation(int argc, char**argv, DATA* data)
       } else if (0==strcmp(clockName, "RT")) {
         clock = OMC_CLOCK_REALTIME;
       } else if(0==strcmp(clockName, "CYC")) {
-    	clock = OMC_CPU_CYCLES;
+      clock = OMC_CPU_CYCLES;
       } else {
         WARNING1(LOG_STDOUT, "[unknown clock-type] got %s, expected CPU|RT|CYC. Defaulting to RT.", clockName);
       }