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how to apply SimTop.v in Vivado #933
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SimTop is for behavior simulation. If you need synthesizable verilog, please use As for |
thanks and is top module -> XSTop.v? |
Yes. It's XSTop, with 3 AXI channels |
thanks a lot man |
Done for this |
@fatalfeel What's the synthesized frequency of XSTop on your FPGA ? |
Did you use MinimalConfig of XiangShan? We actually don't test enough on this minimal version. So there may be some functional or timing issues with this version. |
I did not set synthesized frequency only draw a cpu circuit |
load source file /root/riscv_cpu/XiangShan/build/SimTop.v
/root/riscv_cpu/XiangShan/build/plusarg_reader.v
or
/root/riscv_cpu/XiangShan/build/XSTop.v
/root/riscv_cpu/XiangShan/build/plusarg_reader.v
make Schematic failed
[Synth 8-439] module 'plusarg_reader' not found ["/root/riscv_cpu/XiangShan/build/SimTop.v":622]
[Synth 8-6156] failed synthesizing module 'TLMonitor' ["/root/riscv_cpu/XiangShan/build/SimTop.v":35]
[Vivado_Tcl 4-5] Elaboration failed - please see the console for details
how to to use it correctly?
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