test_show_graph.py

from psyneulink.core.compositions.composition import Composition
# from psyneulink.core.compositions.showgraph import _get_graph_node_label
from psyneulink.core.components.functions.transferfunctions import Linear
from psyneulink.core.components.functions.learningfunctions import BackPropagation
from psyneulink.core.components.mechanisms.processing.objectivemechanism import ObjectiveMechanism
from psyneulink.core.components.mechanisms.processing.transfermechanism import TransferMechanism
from psyneulink.core.components.mechanisms.modulatory.control.optimizationcontrolmechanism import OptimizationControlMechanism
from psyneulink.core.components.ports.modulatorysignals.controlsignal import ControlSignal
from psyneulink.core.globals.keywords import ALL, INSET, INTERCEPT, NESTED, NOISE, SLOPE
from psyneulink.core.globals.registry import clear_registry
from psyneulink.library.components.mechanisms.modulatory.control.agt.lccontrolmechanism import LCControlMechanism

class TestSimpleCompositions:
    def test_process(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")

        comp = Composition()
        comp.add_linear_processing_pathway([a, b])

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label

    def test_diverging_pathways(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        c = TransferMechanism(name="c", default_variable=[0, 0, 0, 0, 0])
        comp = Composition()
        comp.add_linear_processing_pathway([a, b])
        comp.add_linear_processing_pathway([a, c])

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)
        c_label = comp._show_graph._get_graph_node_label(comp, c, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label
        assert "out (5)" in c_label and "in (5)" in c_label

    def test_converging_pathways(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        c = TransferMechanism(name="c", default_variable=[0, 0, 0, 0, 0])
        comp = Composition()
        comp.add_linear_processing_pathway([a, c])
        comp.add_linear_processing_pathway([b, c])

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)
        c_label = comp._show_graph._get_graph_node_label(comp, c, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label
        assert "out (5)" in c_label and "in (5)" in c_label


class TestLearning:
    def test_process(self):
        a = TransferMechanism(name="a-sg", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b-sg")

        comp = Composition()
        comp.add_linear_learning_pathway([a, b], learning_function=BackPropagation)

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label

    def test_diverging_pathways(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        c = TransferMechanism(name="c", default_variable=[0, 0, 0, 0, 0])
        comp = Composition()
        comp.add_linear_learning_pathway(
            [a, b], learning_function=BackPropagation
        )
        comp.add_linear_learning_pathway(
            [a, c], learning_function=BackPropagation
        )

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)
        c_label = comp._show_graph._get_graph_node_label(comp, c, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label
        assert "out (5)" in c_label and "in (5)" in c_label

    def test_converging_pathways(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        c = TransferMechanism(name="c", default_variable=[0, 0, 0, 0, 0])
        comp = Composition()
        comp.add_linear_learning_pathway(
            [a, c], learning_function=BackPropagation
        )
        comp.add_linear_learning_pathway(
            [b, c], learning_function=BackPropagation
        )

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)
        c_label = comp._show_graph._get_graph_node_label(comp, c, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label
        assert "out (5)" in c_label and "in (5)" in c_label


class TestControl:
    def test_process(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        LC = LCControlMechanism(
            modulated_mechanisms=[a, b],
            objective_mechanism=ObjectiveMechanism(
                function=Linear, monitor=[b], name="lc_om"
            ),
            name="lc",
        )
        comp = Composition()
        comp.add_linear_processing_pathway([a, b])

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label

    def test_diverging_pathways(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        c = TransferMechanism(name="c", default_variable=[0, 0, 0, 0, 0])
        LC = LCControlMechanism(
            modulated_mechanisms=[a, b],
            objective_mechanism=ObjectiveMechanism(
                function=Linear, monitor=[b], name="lc_om"
            ),
            name="lc",
        )
        comp = Composition()
        comp.add_linear_processing_pathway([a, b])
        comp.add_linear_processing_pathway([a, c])

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)
        c_label = comp._show_graph._get_graph_node_label(comp, c, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label
        assert "out (5)" in c_label and "in (5)" in c_label

    def test_converging_pathways(self):
        a = TransferMechanism(name="a", default_variable=[0, 0, 0])
        b = TransferMechanism(name="b")
        c = TransferMechanism(name="c", default_variable=[0, 0, 0, 0, 0])
        LC = LCControlMechanism(
            modulated_mechanisms=[a, b],
            objective_mechanism=ObjectiveMechanism(
                function=Linear, monitor=[b], name="lc_om"
            ),
            name="lc",
        )
        comp = Composition()
        comp.add_linear_processing_pathway([a, c])
        comp.add_linear_processing_pathway([b, c])

        a_label = comp._show_graph._get_graph_node_label(comp, a, show_dimensions=ALL)
        b_label = comp._show_graph._get_graph_node_label(comp, b, show_dimensions=ALL)
        c_label = comp._show_graph._get_graph_node_label(comp, c, show_dimensions=ALL)

        assert "out (3)" in a_label and "in (3)" in a_label
        assert "out (1)" in b_label and "in (1)" in b_label
        assert "out (5)" in c_label and "in (5)" in c_label

    def test_multiple_nesting_levels_in_simple_comp(self):

        # clear_registry(MechanismRegistry)
        # clear_registry(CompositionRegistry)

        ia = TransferMechanism(name='ia')
        ib = TransferMechanism(name='ib')
        icomp = Composition(name='icomp', pathways=[ia,ib])

        # Middle Composition
        ma = TransferMechanism(name='ma')
        mb = TransferMechanism(name='mb')
        mcomp = Composition(name='mcomp', pathways=[ma, icomp, mb])

        # Outer Composition
        oa = TransferMechanism(name='oa')
        ob = TransferMechanism(name='ob')
        ocomp = Composition(name='ocomp', pathways=[oa, mcomp, ob])

        gv = ocomp.show_graph(show_nested=False, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\tmcomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> mcomp [label="" arrowhead=normal color=black penwidth=1]\n\tmcomp -> ob [label="" arrowhead=normal color=black penwidth=1]\n\tob [color=red penwidth=3 rank=max shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=0, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\tmcomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> mcomp [label="" arrowhead=normal color=black penwidth=1]\n\tmcomp -> ob [label="" arrowhead=normal color=black penwidth=1]\n\tob [color=red penwidth=3 rank=max shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=1, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\toa -> ma [label="" arrowhead=normal color=black penwidth=1]\n\tsubgraph cluster_mcomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tma [color=green penwidth=3 rank=source shape=oval]\n\t\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\t\tma -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\t\ticomp -> mb [label="" arrowhead=normal color=black penwidth=1]\n\t\tmb [color=red penwidth=3 rank=max shape=oval]\n\t\tlabel=mcomp\n\t}\n\tmb -> ob [label="" arrowhead=normal color=black penwidth=1]\n\tob [color=red penwidth=3 rank=max shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=2, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\toa -> ma [label="" arrowhead=normal color=black penwidth=1]\n\tsubgraph cluster_mcomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tma [color=green penwidth=3 rank=source shape=oval]\n\t\tma -> ia [label="" arrowhead=normal color=black penwidth=1]\n\t\tsubgraph cluster_icomp {\n\t\t\tgraph [overlap=False rankdir=BT]\n\t\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\t\tedge [fontname=arial fontsize=10]\n\t\t\tia [color=green penwidth=3 rank=source shape=oval]\n\t\t\tia -> ib [label="" arrowhead=normal color=black penwidth=1]\n\t\t\tib [color=red penwidth=3 rank=max shape=oval]\n\t\t\tlabel=icomp\n\t\t}\n\t\tib -> mb [label="" arrowhead=normal color=black penwidth=1]\n\t\tmb [color=red penwidth=3 rank=max shape=oval]\n\t\tlabel=mcomp\n\t}\n\tmb -> ob [label="" arrowhead=normal color=black penwidth=1]\n\tob [color=red penwidth=3 rank=max shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=INSET, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\tsubgraph cluster_mcomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tma [color=green penwidth=3 rank=source shape=oval]\n\t\tsubgraph cluster_icomp {\n\t\t\tgraph [overlap=False rankdir=BT]\n\t\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\t\tedge [fontname=arial fontsize=10]\n\t\t\tia [color=green penwidth=3 rank=source shape=oval]\n\t\t\tia -> ib [label="" arrowhead=normal color=black penwidth=1]\n\t\t\tib [color=red penwidth=3 rank=max shape=oval]\n\t\t\tlabel=icomp\n\t\t}\n\t\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\t\tma -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\t\ticomp -> mb [label="" arrowhead=normal color=black penwidth=1]\n\t\tmb [color=red penwidth=3 rank=max shape=oval]\n\t\tlabel=mcomp\n\t}\n\tmcomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> mcomp [label="" arrowhead=normal color=black penwidth=1]\n\tmcomp -> ob [label="" arrowhead=normal color=black penwidth=1]\n\tob [color=red penwidth=3 rank=max shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=2, show_cim=True, show_node_structure=True, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\toa:"OutputPort-RESULT" -> "mcomp INPUT":"InputPort-INPUT_CIM_ma_InputPort-0" [label="" color=black penwidth=1]\n\t"mcomp OUTPUT":"OutputPort-OUTPUT_CIM_mb_RESULT" -> ob:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\tsubgraph cluster_mcomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tma [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ma" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ma</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\t\tma:"OutputPort-RESULT" -> "icomp INPUT":"InputPort-INPUT_CIM_ia_InputPort-0" [label="" color=black penwidth=1]\n\t\t"icomp OUTPUT":"OutputPort-OUTPUT_CIM_ib_RESULT" -> mb:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t\tsubgraph cluster_icomp {\n\t\t\tgraph [overlap=False rankdir=BT]\n\t\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\t\tedge [fontname=arial fontsize=10]\n\t\t\tia [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ia" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ia</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\t\t\tia:"OutputPort-RESULT" -> ib:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\t\t\t"icomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_ia_InputPort-0"><b>INPUT_CIM_ia_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Input_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-INPUT_CIM_ia_InputPort-0"><b>INPUT_CIM_ia_InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t\t\t"icomp INPUT":"OutputPort-INPUT_CIM_ia_InputPort-0" -> ia:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t\t\t"icomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-OUTPUT_CIM_ib_RESULT"><b>OUTPUT_CIM_ib_RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_ib_RESULT"><b>OUTPUT_CIM_ib_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\t\t\tib:"OutputPort-RESULT" -> "icomp OUTPUT":"InputPort-OUTPUT_CIM_ib_RESULT" [label="" color=black penwidth=1]\n\t\t\tib [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ib" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ib</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\t\t\tlabel=icomp\n\t\t}\n\t\t"mcomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_ma_InputPort-0"><b>INPUT_CIM_ma_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="mcomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >mcomp Input_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-INPUT_CIM_ma_InputPort-0"><b>INPUT_CIM_ma_InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t\t"mcomp INPUT":"OutputPort-INPUT_CIM_ma_InputPort-0" -> ma:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t\t"mcomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-OUTPUT_CIM_mb_RESULT"><b>OUTPUT_CIM_mb_RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="mcomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >mcomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_mb_RESULT"><b>OUTPUT_CIM_mb_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\t\tmb:"OutputPort-RESULT" -> "mcomp OUTPUT":"InputPort-OUTPUT_CIM_mb_RESULT" [label="" color=black penwidth=1]\n\t\tmb [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="mb" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >mb</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\t\tlabel=mcomp\n\t}\n\t"ocomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_oa_InputPort-0"><b>INPUT_CIM_oa_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Input_CIM</font></b></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_oa_InputPort-0" -> oa:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td port="ocomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_ob_RESULT"><b>OUTPUT_CIM_ob_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\tob:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_ob_RESULT" [label="" color=black penwidth=1]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n}'

    def test_of_control_projection_to_nested_comp_one_level_below(self):
        pass


    def test_of_show_nested_show_cim_and_show_node_structure(self):
        # clear_registry(MechanismRegistry)
        # clear_registry(CompositionRegistry)

        # Inner Composition
        ia = TransferMechanism(name='ia')
        icomp = Composition(name='icomp', pathways=[ia])

        # Outer Composition
        oa = TransferMechanism(name='oa')
        ob = TransferMechanism(name='ob')
        oc = TransferMechanism(name='oc')
        # ctl_mech = ControlMechanism(name='ctl_mech',
        #                             control_signals=[ControlSignal(projections=[(SLOPE, ia)])])
        ocomp = Composition(name='ocomp', pathways=[oa, icomp, oc])
        ocomp.add_nodes(ob)
        ocm = OptimizationControlMechanism(name='ocm',
                                           agent_rep=ocomp,
                                           control_signals=[
                                               ControlSignal(projections=[(NOISE, ia)]),
                                               ControlSignal(projections=[(INTERCEPT, ia)]),
                                               ControlSignal(projections=[(SLOPE, ia)]),
                                               ControlSignal(projections=[(SLOPE, oa)]),
                                               # ControlSignal(projections=[(SLOPE, nonmember_node)]),
                                           ])
        ocomp.add_controller(ocm)

        gv = ocomp.show_graph(show_nested=False, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc [label="" arrowhead=normal color=black penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> oa [label="" color=blue penwidth=1]\n\toc [color=red penwidth=3 rank=max shape=oval]\n\tob [color=brown penwidth=3 rank=same shape=oval]\n\tocm [color=blue penwidth=1 rank=min shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=INSET, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tia [color=brown penwidth=3 rank=same shape=oval]\n\t\tlabel=icomp\n\t}\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc [label="" arrowhead=normal color=black penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> oa [label="" color=blue penwidth=1]\n\toc [color=red penwidth=3 rank=max shape=oval]\n\tob [color=brown penwidth=3 rank=same shape=oval]\n\tocm [color=blue penwidth=1 rank=min shape=oval]\n}'
        gv = ocomp.show_graph(show_nested=NESTED, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\toa -> ia [label="" arrowhead=normal color=black penwidth=1]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tia [color=brown penwidth=3 rank=same shape=oval]\n\t\tlabel=icomp\n\t}\n\tia -> oc [label="" arrowhead=normal color=black penwidth=1]\n\tocm -> ia [label="" color=blue penwidth=1]\n\tocm -> ia [label="" color=blue penwidth=1]\n\tocm -> ia [label="" color=blue penwidth=1]\n\tocm -> oa [label="" color=blue penwidth=1]\n\toc [color=red penwidth=3 rank=max shape=oval]\n\tob [color=brown penwidth=3 rank=same shape=oval]\n\tocm [color=blue penwidth=1 rank=min shape=oval]\n}'
        gv = ocomp.show_graph(show_cim=True, show_nested=False, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc [label="" arrowhead=normal color=black penwidth=1]\n\t"ocomp INPUT" [color=green penwidth=1 rank=same shape=rectangle]\n\t"ocomp INPUT" -> oa [label="" color=black penwidth=1]\n\t"ocomp INPUT" -> ob [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [color=red penwidth=1 rank=same shape=rectangle]\n\toc -> "ocomp OUTPUT" [label="" color=black penwidth=1]\n\tob -> "ocomp OUTPUT" [label="" color=black penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> oa [label="" color=blue penwidth=1]\n\toc [color=red penwidth=3 rank=max shape=oval]\n\tob [color=brown penwidth=3 rank=same shape=oval]\n\tocm [color=blue penwidth=1 rank=min shape=oval]\n}'
        gv = ocomp.show_graph(show_cim=True, show_nested=INSET, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\t"icomp INPUT" [color=green penwidth=1 rank=same shape=rectangle]\n\t\t"icomp INPUT" -> ia [label="" color=black penwidth=1]\n\t\t"icomp CONTROL" [color=blue penwidth=1 rank=same shape=rectangle]\n\t\t"icomp CONTROL" -> ia [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL" -> ia [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL" -> ia [label="" color=blue penwidth=1]\n\t\t"icomp OUTPUT" [color=red penwidth=1 rank=same shape=rectangle]\n\t\tia -> "icomp OUTPUT" [label="" color=black penwidth=1]\n\t\tia [color=brown penwidth=3 rank=same shape=oval]\n\t\tlabel=icomp\n\t}\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc [label="" arrowhead=normal color=black penwidth=1]\n\t"ocomp INPUT" [color=green penwidth=1 rank=same shape=rectangle]\n\t"ocomp INPUT" -> oa [label="" color=black penwidth=1]\n\t"ocomp INPUT" -> ob [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [color=red penwidth=1 rank=same shape=rectangle]\n\toc -> "ocomp OUTPUT" [label="" color=black penwidth=1]\n\tob -> "ocomp OUTPUT" [label="" color=black penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> icomp [label="" color=blue penwidth=1]\n\tocm -> oa [label="" color=blue penwidth=1]\n\toc [color=red penwidth=3 rank=max shape=oval]\n\tob [color=brown penwidth=3 rank=same shape=oval]\n\tocm [color=blue penwidth=1 rank=min shape=oval]\n}'
        gv = ocomp.show_graph(show_cim=True, show_nested=NESTED, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [color=green penwidth=3 rank=source shape=oval]\n\toa -> "icomp INPUT" [label="" color=black penwidth=1]\n\t"icomp OUTPUT" -> oc [label="" color=black penwidth=1]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\t"icomp INPUT" [color=green penwidth=1 rank=same shape=rectangle]\n\t\t"icomp INPUT" -> ia [label="" color=black penwidth=1]\n\t\t"icomp CONTROL" [color=blue penwidth=1 rank=same shape=rectangle]\n\t\t"icomp CONTROL" -> ia [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL" -> ia [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL" -> ia [label="" color=blue penwidth=1]\n\t\t"icomp OUTPUT" [color=red penwidth=1 rank=same shape=rectangle]\n\t\tia -> "icomp OUTPUT" [label="" color=black penwidth=1]\n\t\tia [color=brown penwidth=3 rank=same shape=oval]\n\t\tlabel=icomp\n\t}\n\t"ocomp INPUT" [color=green penwidth=1 rank=same shape=rectangle]\n\t"ocomp INPUT" -> oa [label="" color=black penwidth=1]\n\t"ocomp INPUT" -> ob [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [color=red penwidth=1 rank=same shape=rectangle]\n\toc -> "ocomp OUTPUT" [label="" color=black penwidth=1]\n\tob -> "ocomp OUTPUT" [label="" color=black penwidth=1]\n\tocm -> "icomp CONTROL" [label="" color=blue penwidth=1]\n\tocm -> "icomp CONTROL" [label="" color=blue penwidth=1]\n\tocm -> "icomp CONTROL" [label="" color=blue penwidth=1]\n\tocm -> oa [label="" color=blue penwidth=1]\n\toc [color=red penwidth=3 rank=max shape=oval]\n\tob [color=brown penwidth=3 rank=same shape=oval]\n\tocm [color=blue penwidth=1 rank=min shape=oval]\n}'
        gv = ocomp.show_graph(show_node_structure=True, show_nested=False, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa:"OutputPort-RESULT" -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\tocm:"OutputPort-ia[noise] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[intercept] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[slope] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-oa[slope] ControlSignal" -> oa:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\toc [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oc" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oc</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\tocm [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-ia[noise] ControlSignal"><b>ia[noise] ControlSignal</b></td><td port="OutputPort-ia[intercept] ControlSignal"><b>ia[intercept] ControlSignal</b></td><td port="OutputPort-ia[slope] ControlSignal"><b>ia[slope] ControlSignal</b></td><td port="OutputPort-oa[slope] ControlSignal"><b>oa[slope] ControlSignal</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocm" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocm</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTCOME"><b>OUTCOME</b></td><td port="InputPort-OUTCOME-1"><b>OUTCOME-1</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=min shape=plaintext]\n}'
        gv = ocomp.show_graph(show_node_structure=True, show_nested=INSET, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tia [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ia" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ia</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\t\tlabel=icomp\n\t}\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa:"OutputPort-RESULT" -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\tocm:"OutputPort-ia[noise] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[intercept] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[slope] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-oa[slope] ControlSignal" -> oa:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\toc [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oc" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oc</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\tocm [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-ia[noise] ControlSignal"><b>ia[noise] ControlSignal</b></td><td port="OutputPort-ia[intercept] ControlSignal"><b>ia[intercept] ControlSignal</b></td><td port="OutputPort-ia[slope] ControlSignal"><b>ia[slope] ControlSignal</b></td><td port="OutputPort-oa[slope] ControlSignal"><b>oa[slope] ControlSignal</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocm" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocm</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTCOME"><b>OUTCOME</b></td><td port="InputPort-OUTCOME-1"><b>OUTCOME-1</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=min shape=plaintext]\n}'
        gv = ocomp.show_graph(show_node_structure=True, show_nested=NESTED, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\toa:"OutputPort-RESULT" -> ia:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\tia [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ia" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ia</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\t\tlabel=icomp\n\t}\n\tia:"OutputPort-RESULT" -> oc:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\tocm:"OutputPort-ia[noise] ControlSignal" -> ia:"ParameterPort-noise" [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[intercept] ControlSignal" -> ia:"ParameterPort-intercept" [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[slope] ControlSignal" -> ia:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\tocm:"OutputPort-oa[slope] ControlSignal" -> oa:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\toc [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oc" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oc</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\tocm [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-ia[noise] ControlSignal"><b>ia[noise] ControlSignal</b></td><td port="OutputPort-ia[intercept] ControlSignal"><b>ia[intercept] ControlSignal</b></td><td port="OutputPort-ia[slope] ControlSignal"><b>ia[slope] ControlSignal</b></td><td port="OutputPort-oa[slope] ControlSignal"><b>oa[slope] ControlSignal</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocm" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocm</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTCOME"><b>OUTCOME</b></td><td port="InputPort-OUTCOME-1"><b>OUTCOME-1</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=min shape=plaintext]\n}'
        gv = ocomp.show_graph(show_node_structure=True, show_cim=True, show_nested=False, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa:"OutputPort-RESULT" -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\t"ocomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_oa_InputPort-0"><b>INPUT_CIM_oa_InputPort-0</b></td><td port="OutputPort-INPUT_CIM_ob_InputPort-0"><b>INPUT_CIM_ob_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Input_CIM</font></b></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_oa_InputPort-0" -> oa:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_ob_InputPort-0" -> ob:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td port="ocomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_oc_RESULT"><b>OUTPUT_CIM_oc_RESULT</b></td><td port="InputPort-OUTPUT_CIM_ob_RESULT"><b>OUTPUT_CIM_ob_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\toc:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_oc_RESULT" [label="" color=black penwidth=1]\n\tob:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_ob_RESULT" [label="" color=black penwidth=1]\n\tocm:"OutputPort-ia[noise] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[intercept] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[slope] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-oa[slope] ControlSignal" -> oa:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\toc [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oc" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oc</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\tocm [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-ia[noise] ControlSignal"><b>ia[noise] ControlSignal</b></td><td port="OutputPort-ia[intercept] ControlSignal"><b>ia[intercept] ControlSignal</b></td><td port="OutputPort-ia[slope] ControlSignal"><b>ia[slope] ControlSignal</b></td><td port="OutputPort-oa[slope] ControlSignal"><b>oa[slope] ControlSignal</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocm" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocm</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTCOME"><b>OUTCOME</b></td><td port="InputPort-OUTCOME-1"><b>OUTCOME-1</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=min shape=plaintext]\n}'
        gv = ocomp.show_graph(show_node_structure=True, show_cim=True, show_nested=INSET, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\t"icomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_ia_InputPort-0"><b>INPUT_CIM_ia_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Input_CIM</font></b></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t\t"icomp INPUT":"OutputPort-INPUT_CIM_ia_InputPort-0" -> ia:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t\t"icomp CONTROL" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-PARAMETER_CIM_ia_intercept"><b>PARAMETER_CIM_ia_intercept</b></td><td port="OutputPort-PARAMETER_CIM_ia_noise"><b>PARAMETER_CIM_ia_noise</b></td><td port="OutputPort-PARAMETER_CIM_ia_slope"><b>PARAMETER_CIM_ia_slope</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Parameter_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Parameter_CIM</font></b></td></tr></table>> color=blue penwidth=1 rank=same shape=plaintext]\n\t\t"icomp CONTROL":"OutputPort-PARAMETER_CIM_ia_intercept" -> ia:"ParameterPort-intercept" [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL":"OutputPort-PARAMETER_CIM_ia_noise" -> ia:"ParameterPort-noise" [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL":"OutputPort-PARAMETER_CIM_ia_slope" -> ia:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\t\t"icomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td port="icomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_ia_RESULT"><b>OUTPUT_CIM_ia_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\t\tia:"OutputPort-RESULT" -> "icomp OUTPUT":"InputPort-OUTPUT_CIM_ia_RESULT" [label="" color=black penwidth=1]\n\t\tia [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ia" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ia</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\t\tlabel=icomp\n\t}\n\ticomp [color=pink penwidth=3 rank=same shape=rectangle]\n\toa:"OutputPort-RESULT" -> icomp [label="" arrowhead=normal color=black penwidth=1]\n\ticomp -> oc:"InputPort-InputPort-0" [label="" arrowhead=normal color=black penwidth=1]\n\t"ocomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_oa_InputPort-0"><b>INPUT_CIM_oa_InputPort-0</b></td><td port="OutputPort-INPUT_CIM_ob_InputPort-0"><b>INPUT_CIM_ob_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Input_CIM</font></b></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_oa_InputPort-0" -> oa:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_ob_InputPort-0" -> ob:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td port="ocomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_oc_RESULT"><b>OUTPUT_CIM_oc_RESULT</b></td><td port="InputPort-OUTPUT_CIM_ob_RESULT"><b>OUTPUT_CIM_ob_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\toc:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_oc_RESULT" [label="" color=black penwidth=1]\n\tob:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_ob_RESULT" [label="" color=black penwidth=1]\n\tocm:"OutputPort-ia[noise] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[intercept] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[slope] ControlSignal" -> icomp [label="" color=blue penwidth=1]\n\tocm:"OutputPort-oa[slope] ControlSignal" -> oa:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\toc [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oc" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oc</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\tocm [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-ia[noise] ControlSignal"><b>ia[noise] ControlSignal</b></td><td port="OutputPort-ia[intercept] ControlSignal"><b>ia[intercept] ControlSignal</b></td><td port="OutputPort-ia[slope] ControlSignal"><b>ia[slope] ControlSignal</b></td><td port="OutputPort-oa[slope] ControlSignal"><b>oa[slope] ControlSignal</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocm" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocm</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTCOME"><b>OUTCOME</b></td><td port="InputPort-OUTCOME-1"><b>OUTCOME-1</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=min shape=plaintext]\n}'
        gv = ocomp.show_graph(show_node_structure=True, show_cim=True, show_nested=NESTED, output_fmt='source')
        assert gv == 'digraph ocomp {\n\tgraph [overlap=False rankdir=BT]\n\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\tedge [fontname=arial fontsize=10]\n\toa [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oa" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oa</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=3 rank=source shape=plaintext]\n\toa:"OutputPort-RESULT" -> "icomp INPUT":"InputPort-INPUT_CIM_ia_InputPort-0" [label="" color=black penwidth=1]\n\t"icomp OUTPUT":"OutputPort-OUTPUT_CIM_ia_RESULT" -> oc:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\tsubgraph cluster_icomp {\n\t\tgraph [overlap=False rankdir=BT]\n\t\tnode [color=black fontname=arial fontsize=12 penwidth=1 shape=record]\n\t\tedge [fontname=arial fontsize=10]\n\t\t"icomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_ia_InputPort-0"><b>INPUT_CIM_ia_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Input_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-INPUT_CIM_ia_InputPort-0"><b>INPUT_CIM_ia_InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t\t"icomp INPUT":"OutputPort-INPUT_CIM_ia_InputPort-0" -> ia:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t\t"icomp CONTROL" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-PARAMETER_CIM_ia_intercept"><b>PARAMETER_CIM_ia_intercept</b></td><td port="OutputPort-PARAMETER_CIM_ia_noise"><b>PARAMETER_CIM_ia_noise</b></td><td port="OutputPort-PARAMETER_CIM_ia_slope"><b>PARAMETER_CIM_ia_slope</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Parameter_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Parameter_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-PARAMETER_CIM_ia_intercept"><b>PARAMETER_CIM_ia_intercept</b></td><td port="InputPort-PARAMETER_CIM_ia_noise"><b>PARAMETER_CIM_ia_noise</b></td><td port="InputPort-PARAMETER_CIM_ia_slope"><b>PARAMETER_CIM_ia_slope</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=same shape=plaintext]\n\t\t"icomp CONTROL":"OutputPort-PARAMETER_CIM_ia_intercept" -> ia:"ParameterPort-intercept" [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL":"OutputPort-PARAMETER_CIM_ia_noise" -> ia:"ParameterPort-noise" [label="" color=blue penwidth=1]\n\t\t"icomp CONTROL":"OutputPort-PARAMETER_CIM_ia_slope" -> ia:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\t\t"icomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-OUTPUT_CIM_ia_RESULT"><b>OUTPUT_CIM_ia_RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="icomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >icomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_ia_RESULT"><b>OUTPUT_CIM_ia_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\t\tia:"OutputPort-RESULT" -> "icomp OUTPUT":"InputPort-OUTPUT_CIM_ia_RESULT" [label="" color=black penwidth=1]\n\t\tia [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ia" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ia</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\t\tlabel=icomp\n\t}\n\t"ocomp INPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-INPUT_CIM_oa_InputPort-0"><b>INPUT_CIM_oa_InputPort-0</b></td><td port="OutputPort-INPUT_CIM_ob_InputPort-0"><b>INPUT_CIM_ob_InputPort-0</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocomp Input_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Input_CIM</font></b></td></tr></table>> color=green penwidth=1 rank=same shape=plaintext]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_oa_InputPort-0" -> oa:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp INPUT":"OutputPort-INPUT_CIM_ob_InputPort-0" -> ob:"InputPort-InputPort-0" [label="" color=black penwidth=1]\n\t"ocomp OUTPUT" [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td port="ocomp Output_CIM" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocomp Output_CIM</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTPUT_CIM_oc_RESULT"><b>OUTPUT_CIM_oc_RESULT</b></td><td port="InputPort-OUTPUT_CIM_ob_RESULT"><b>OUTPUT_CIM_ob_RESULT</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=1 rank=same shape=plaintext]\n\toc:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_oc_RESULT" [label="" color=black penwidth=1]\n\tob:"OutputPort-RESULT" -> "ocomp OUTPUT":"InputPort-OUTPUT_CIM_ob_RESULT" [label="" color=black penwidth=1]\n\tocm:"OutputPort-ia[noise] ControlSignal" -> "icomp CONTROL":"InputPort-PARAMETER_CIM_ia_noise" [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[intercept] ControlSignal" -> "icomp CONTROL":"InputPort-PARAMETER_CIM_ia_intercept" [label="" color=blue penwidth=1]\n\tocm:"OutputPort-ia[slope] ControlSignal" -> "icomp CONTROL":"InputPort-PARAMETER_CIM_ia_slope" [label="" color=blue penwidth=1]\n\tocm:"OutputPort-oa[slope] ControlSignal" -> oa:"ParameterPort-slope" [label="" color=blue penwidth=1]\n\toc [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="oc" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >oc</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=red penwidth=3 rank=max shape=plaintext]\n\tob [label=<<table border=\'3\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-RESULT"><b>RESULT</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ob" colspan="1"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ob</font></b></td><td> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td rowspan="1" valign="middle"><b><i>ParameterPorts</i></b></td> <td> <table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="ParameterPort-integration_rate"><b>integration_rate</b></td></tr><tr><td port="ParameterPort-intercept"><b>intercept</b></td></tr><tr><td port="ParameterPort-noise"><b>noise</b></td></tr><tr><td port="ParameterPort-slope"><b>slope</b></td></tr></table></td></tr></table></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-InputPort-0"><b>InputPort-0</b></td></tr></table></td></tr></table></td></tr></table>> color=brown penwidth=3 rank=same shape=plaintext]\n\tocm [label=<<table border=\'1\' cellborder="0" cellspacing="1" bgcolor="#FFFFF0"><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="OutputPort-ia[noise] ControlSignal"><b>ia[noise] ControlSignal</b></td><td port="OutputPort-ia[intercept] ControlSignal"><b>ia[intercept] ControlSignal</b></td><td port="OutputPort-ia[slope] ControlSignal"><b>ia[slope] ControlSignal</b></td><td port="OutputPort-oa[slope] ControlSignal"><b>oa[slope] ControlSignal</b></td></tr></table></td></tr> <tr><td colspan="1" valign="middle"><b><i>OutputPorts</i></b></td></tr> </table></td></tr><tr><td port="ocm" colspan="2"><b><b><i>Mechanism</i></b>:<br/><font point-size="16" >ocm</font></b></td></tr><tr><td colspan="2"> <table border="0" cellborder="0" bgcolor="#FAFAD0"> <tr><td colspan="1" valign="middle"><b><i>InputPorts</i></b></td></tr><tr><td><table border="0" cellborder="2" cellspacing="0" color="LIGHTGOLDENRODYELLOW" bgcolor="PALEGOLDENROD"><tr><td port="InputPort-OUTCOME"><b>OUTCOME</b></td><td port="InputPort-OUTCOME-1"><b>OUTCOME-1</b></td></tr></table></td></tr></table></td></tr></table>> color=blue penwidth=1 rank=min shape=plaintext]\n}'