Updating delay model

[tanvir-a]

At this moment the generated VPR model adds some fake delay. I would like to update with more realistic dealy. What are the steps for that? For example, right now I got a more accurate delay from the layout of the RTL model, and want to update the PRGA for that.

[angl-dev]

Yes, this is on my long-term todo list. My plan was to add another delegate class (similar to the FASMDelegate class) that "answers" questions about the timing. One possible implementation of this delegate could be reading timing info from a timing report generated by STA tools, or reading a pre-processed timing database.

Specifically, there are three categories of timing: 1) primitive timing, e.g. LUT delay, 2) intra-block switch delay, and 3) routing channel switch delay. The first two categories are simple to deal with, but for the last one, things are a bit complicated. If the switch delays are constrained before layout, you may use the constraint value to define a tag in VPR's rrg.xml, and refer to that in each <rr_edge>. If the switch delays are measured after layout, I recommend you quantitize the switches and classify them into a few speed classes. Create tags for each speed class and then refer to them in each <rr_edge>.

In addition, some big changes are undergoing in the dev branch, and the RTL generation is slightly different. If you've progressed far into ASIC backend, we can have more discussion on how to deal with timing model. But if you can switch over to the dev branch, we can work on the timing model together. If you're interested, we can schedule a virtual meeting and I can go over the changes in the dev branch.

[angl-dev]

Besides, which type of configuration circuitry are you using?