Transpiler pushes gates behind measurements

[Cryoris]

Information

• Qiskit Terra version: 0.13.0
• Python version: 3.7.5
• Operating system: MacOS Catalina

What is the current behavior?

If circuits with measurements are run on real hardware they must be the last operation on the wire/qubit. If the measurement is specified as last operation, but no prior global barrier is added the transpiler might move gates behind these measurements and causes the circuit to fail.

Steps to reproduce the problem

Transpile the QASM below [1] with the specifications of the singapore backend [2].
Then the transpiled circuit contains the following part:

What is the expected behavior?

If measurement are added as final operations, they should remain the final operations.

Suggested solutions

Possibly check if the measurements are the final operations and apply the transpiler only to the part prior to the measurements.

Resources for reproducing the problem

[1] QASM:

OPENQASM 2.0;
include "qelib1.inc";
qreg q[4];
qreg aux[3];
creg c0[1];
u3(1.51080452689302,0.0,0.0) q[2];
u1(0.0) q[2];
cx q[2],q[1];
u3(1.0354507674742846,0.0,0.0) q[1];
cx q[2],q[1];
u3(1.682873047977714,0.0,0.0) q[1];
cx q[2],q[1];
u1(-0.0) q[1];
cx q[2],q[1];
u1(-0.0) q[1];
cx q[2],q[0];
u3(0.6814046158063359,0.0,0.0) q[0];
cx q[1],q[0];
u3(0.15368907928867048,0.0,0.0) q[0];
cx q[1],q[0];
cx q[2],q[0];
cx q[1],q[0];
u3(0.31774997878994404,0.0,0.0) q[0];
cx q[1],q[0];
u3(1.7092511325680475,0.0,0.0) q[0];
cx q[2],q[0];
u1(-0.0) q[0];
cx q[1],q[0];
u1(-0.0) q[0];
cx q[1],q[0];
cx q[2],q[0];
cx q[1],q[0];
u1(-0.0) q[0];
cx q[1],q[0];
u1(-0.0) q[0];
ry(1.1780972450961724) q[3];
cx q[0],aux[1];
ccx q[1],aux[1],aux[2];
u3(3.141592653589793,0,3.141592653589793) aux[0];
u3(3.141592653589793,0,3.141592653589793) q[2];
u3(3.141592653589793,0,3.141592653589793) aux[2];
ccx q[2],aux[2],aux[0];
u3(3.141592653589793,0,3.141592653589793) q[2];
u3(3.141592653589793,0,3.141592653589793) aux[2];
ccx q[1],aux[1],aux[2];
cx q[0],aux[1];
cu3(-0.5885047295390851,0.0,0.0) aux[0],q[3];
cu3(0.0981359209240381,0,0) aux[0],q[3];
ccx aux[0],q[0],q[3];
cu3(-0.0981359209240381,0,0) aux[0],q[3];
ccx aux[0],q[0],q[3];
cu3(0.1962718418480762,0,0) aux[0],q[3];
ccx aux[0],q[1],q[3];
cu3(-0.1962718418480762,0,0) aux[0],q[3];
ccx aux[0],q[1],q[3];
cu3(0.3925436836961524,0,0) aux[0],q[3];
ccx aux[0],q[2],q[3];
cu3(-0.3925436836961524,0,0) aux[0],q[3];
ccx aux[0],q[2],q[3];
cx q[0],aux[1];
ccx q[1],aux[1],aux[2];
u3(-3.141592653589793,-3.141592653589793,0) aux[2];
u3(-3.141592653589793,-3.141592653589793,0) q[2];
ccx q[2],aux[2],aux[0];
u3(-3.141592653589793,-3.141592653589793,0) aux[2];
u3(-3.141592653589793,-3.141592653589793,0) q[2];
u3(-3.141592653589793,-3.141592653589793,0) aux[0];
ccx q[1],aux[1],aux[2];
cx q[0],aux[1];
measure q[3] -> c0[0]

[2] Specs of the singapore backend:

cmap = [[0, 1], [1, 0], [1, 2], [1, 6], [2, 1], [2, 3], [3, 2],
        [3, 4], [3, 8], [4, 3], [5, 6], [5, 10], [6, 1], [6, 5],
        [6, 7], [7, 6], [7, 8], [7, 12], [8, 3], [8, 7], [8, 9],
        [9, 8], [9, 14], [10, 5], [10, 11], [11, 10], [11, 12],
        [11, 16], [12, 7], [12, 11], [12, 13], [13, 12], [13, 14],
        [13, 18], [14, 9], [14, 13], [15, 16], [16, 11], [16, 15],
        [16, 17], [17, 16], [17, 18], [18, 13], [18, 17], [18, 19],
        [19, 18]]
basis_gates = ['u1', 'u2', 'u3', 'cx', 'id']

[1ucian0]

I think the root of the problem is that BarrierBeforeFinalMeasurements should be over all the qubits, not just those with measure. @kdk has more experience here, what do think?

Adding manually barrier q, aux; before the measure seems to do the trick.

[kdk]

Think this was caused I think by a change in stochastic swap, but making BarrierBeforeFinalMeasurements across all qubits should fix it, and will correspond more closely to the actual device constraint.