Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Support for QuantumRegister in gates supporing qubits #369

Merged
merged 52 commits into from May 3, 2018
Merged

Support for QuantumRegister in gates supporing qubits #369

merged 52 commits into from May 3, 2018

Conversation

1ucian0
Copy link
Member

@1ucian0 1ucian0 commented Mar 26, 2018

This PR adds support to gates which support qubits to also accept full register, as the spec defines.

Description

The gates that take one or more qubit as args, should also support the full QuantumRegister as argument. For example: circuit.h(self.qr). The PR also extends the tests for the added code (and more).

Motivation and Context

Trying to write a test for #352 (and #362) I ended up falling the rabbit hole of supporting QuantumRegisters as arguments in the gates that operate over qubits. I noticed that many of the gates had this feature broken.

The most notable cases are:

  • The type of arguments in barrier are extended, in order to behave more similarly to other gates. In addition to the previous *list, now QuantumRegister are supported, also in combination with qubits. Also, if None is passed, it applied the barrier to every QuantumRegister of the circuit (this was a TODO in the code).
  • The specification the semantics of cx when is called with register and bits (Fig 2, page 4). This semantic is now supported.
  • The gates cx_base and swap are analogue to cx.
  • The specification do not define the semantics for ccx when called with registers. Therefore, I only included the intuitive case in which all the arguments are registers (with the same length): ccx q,r,s => ccx q[0],r[0],s[0];ccx q[1],r[1],s[1]; when length is 2.
  • The cswap case is analogue to ccx.

BTW, this PR closes #352.

How Has This Been Tested?

make test

The added tests extend the coverage with respect the existing tests:

file previous stms previously covered new stms now covered
qiskit/extensions/standard/init.py 28 100% 28 100%
qiskit/extensions/standard/barrier.py 45 78% 40 98%
qiskit/extensions/standard/ccx.py 25 100% 32 100%
qiskit/extensions/standard/ch.py 30 87% 40 100%
qiskit/extensions/standard/crz.py 32 88% 42 100%
qiskit/extensions/standard/cswap.py 20 100% 27 100%
qiskit/extensions/standard/cu1.py 32 88% 42 100%
qiskit/extensions/standard/cu3.py 37 89% 47 100%
qiskit/extensions/standard/cx.py 30 87% 40 100%
qiskit/extensions/standard/cxbase.py 23 100% 40 100%
qiskit/extensions/standard/cy.py 30 87% 40 100%
qiskit/extensions/standard/cz.py 30 87% 40 100%
qiskit/extensions/standard/gatestools.py 12 0% 12 0%
qiskit/extensions/standard/h.py 27 85% 32 88%
qiskit/extensions/standard/header.py 5 100% 5 100%
qiskit/extensions/standard/iden.py 27 85% 27 100%
qiskit/extensions/standard/rx.py 29 86% 29 100%
qiskit/extensions/standard/ry.py 29 86% 29 100%
qiskit/extensions/standard/rz.py 29 86% 29 100%
qiskit/extensions/standard/s.py 33 88% 33 100%
qiskit/extensions/standard/swap.py 23 100% 40 100%
qiskit/extensions/standard/t.py 33 88% 33 100%
qiskit/extensions/standard/u0.py 27 52% 27 52%
qiskit/extensions/standard/u1.py 29 86% 29 100%
qiskit/extensions/standard/u2.py 33 88% 33 100%
qiskit/extensions/standard/u3.py 34 88% 34 100%
qiskit/extensions/standard/ubase.py 27 100% 34 100%
qiskit/extensions/standard/x.py 27 85% 27 100%
qiskit/extensions/standard/y.py 27 85% 27 100%
qiskit/extensions/standard/z.py 27 85% 27 100%

None of the changes brake backward compatibility.

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)

@diego-plan9
Copy link
Member

Can you revise the test that is failing in Appveyor? It seems the order of the parameters for barrier is different depending on the os or the version:

AssertionError: 'barrier q[0],q[1],q[2],r[0],r[1],r[2],s[0],s[1],s[2];' not found in 'OPENQASM 2.0;\ninclude "qelib1.inc";\nqreg q[3];\nqreg r[3];\nqreg s[3];\ncreg c[3];\nbarrier q[0],q[1],q[2],s[0],s[1],s[2],r[0],r[1],r[2];\n'

If args is None, applies to all the qbits.
If args is a QuantumRegister, applies to all the qbits in that register.
If args is a list of QuantumRegister, applies to all of them."""

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It looks like args can be a list of QuantumRegister and/or qubit, and the barrier will be applied to all arguments. If that's right, could you add that to the comment?

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Clarified in d3a9d32. Thanks!

if isinstance(tgt, QuantumRegister):
instructions = InstructionSet()
for j in range(tgt.size):
instructions.add(self.swap(ctl, (tgt, j)))
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The swap gate should not allow ctrl and tgt of different sizes I think.

I think swaps between 2 individual qubits or between 2 registers of the same size makes sense. But when the size of registers differ, an exception should be raised.

@awcross1 do you agree?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@ajavadia Yes, I missed this. I agree that swap should not allow different sized registers as input. Good catch.

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Generally we should be careful when G_{i,j} and G_{i,k} do not commute. Does this happen anywhere else in the PR?

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

fixed in 42f6b5a. The valid and invalid cases are listed in the tests. I'm not fully sure what you mean with "G_{i,j} and G_{i,k} cases".

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks @1ucian0 the issue doesn't occur anywhere else. I meant G_{i,j} to denote a two-qubit gate acting on qubits i and j.

Copy link
Member

@atilag atilag left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good!
Thanks for the tests.
Just a note: in general is not a good practice to have more than one assert per test.

@@ -52,182 +52,424 @@
from .common import QiskitTestCase


class TestStandard(QiskitTestCase):
"""Standard Extension Test."""
class StandardExtensionTest(QiskitTestCase):
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Would it be possible to add human-readable docstrings to the assertions methods in this class, ideally describing the parameters as well?

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

fixed in ff05123

@diego-plan9 diego-plan9 added this to the 0.5.0 milestone May 3, 2018
@diego-plan9
Copy link
Member

Thanks @1ucian0 !

@diego-plan9 diego-plan9 merged commit 0648263 into Qiskit:master May 3, 2018
lia-approves pushed a commit to edasgupta/qiskit-terra that referenced this pull request Jul 30, 2019
* no name in the registers means no name :-/

* slip assertResult

* simpler

* 352 fix, test_rz_reg and test_s_reg

* test_sdg_reg

* swap behaves as CX when called with registers as args.

* test_swap_reg_reg_inv

* useless =

* cx

* cx_base

* test_rz_reg_inv

* ry and rx

* test_s_reg_inv

* cy and cz

* barrier

* keeping previous behaivor

* ch

* cu3

* cu1

* crz

* crz and h

* iden

* sdg

* t

* tdg

* u1

* u2

* u3

* ubase

* x

* y

* z

* code organization

* barrier for a list of qbits (and formating)

* adding backwards compatibility to barrier

* format

* ccx and cswap

* format

* this extension of instructionset is not needed

* format

* ordered get_{c,q}regs

* invalid tests

* -from qiskit import InstructionSet

* clarification in barrier usage

* do not allow, swap q,r[1]

* qasm stmt should be in new lines

* docstring
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

Error in Rz gate
5 participants