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phy_drv_ext3.c
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phy_drv_ext3.c
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/*
Copyright (c) 2015 Broadcom Corporation
All Rights Reserved
<:label-BRCM:2015:DUAL/GPL:standard
Unless you and Broadcom execute a separate written software license
agreement governing use of this software, this software is licensed
to you under the terms of the GNU General Public License version 2
(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
with the following added to such license:
As a special exception, the copyright holders of this software give
you permission to link this software with independent modules, and
to copy and distribute the resulting executable under terms of your
choice, provided that you also meet, for each linked independent
module, the terms and conditions of the license of that module.
An independent module is a module which is not derived from this
software. The special exception does not apply to any modifications
of the software.
Not withstanding the above, under no circumstances may you combine
this software in any way with any other Broadcom software provided
under a license other than the GPL, without Broadcom's express prior
written consent.
:>
*/
/*
* Created on: Jan 2016
* Author: yuval.raviv@broadcom.com
*/
/*
* Phy driver for external 1G/2.5G/5G/10G phys: BCM8486x, BCM8488x, BCM8489x, BCM5499x
*/
/*
* PHY firmware versions:
* MAKO A0 1.0.3
* ORCA A0 1.1.2
* ORCA B0 2.3.5
* BLACKFIN A0 0.2.4
* BLACKFIN B0 2.2.8
* SHORTFIN B0 2.2.11
* LONGFIN A0 2.2.8
*/
#include <linux/path.h>
#include <linux/namei.h>
#include <linux/fs.h>
#include "phy_drv.h"
#include "phy_drv_mii.h"
#include "xrdp_led_init.h"
#ifdef MACSEC_SUPPORT
#include "phy_macsec_api.h"
#endif
typedef struct firmware_s firmware_t;
typedef struct phy_desc_s phy_desc_t;
struct firmware_s {
char *name;
int (*load)(firmware_t *firmware);
uint32_t map;
uint8_t macsec_capable;
};
struct phy_desc_s {
uint16_t phyid1;
uint16_t phyid2;
char *name;
firmware_t *firmware;
uint32_t inter_phy_types;
};
#if defined(CONFIG_BCM_PHY_MAKO_A0)
static int load_mako(firmware_t *firmware);
#endif
#if defined(CONFIG_BCM_PHY_ORCA_A0) || defined(CONFIG_BCM_PHY_ORCA_B0)
static int load_orca(firmware_t *firmware);
#endif
#if defined(CONFIG_BCM_PHY_BLACKFIN_A0) || defined(CONFIG_BCM_PHY_BLACKFIN_B0) || defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
static int load_blackfin(firmware_t *firmware);
#endif
#ifdef CONFIG_BCM_PHY_SHORTFIN_B0
static int load_shortfin(firmware_t *firmware);
#endif
#ifdef CONFIG_BCM_PHY_MAKO_A0
firmware_t mako_a0 = { "mako_a0", load_mako, 0, 0 };
#endif
#ifdef CONFIG_BCM_PHY_ORCA_A0
firmware_t orca_a0 = { "orca_a0", load_orca, 0, 0 };
#endif
#ifdef CONFIG_BCM_PHY_ORCA_B0
firmware_t orca_b0 = { "orca_b0", load_orca, 0, 0 };
#endif
#ifdef CONFIG_BCM_PHY_BLACKFIN_A0
firmware_t blackfin_a0 = { "blackfin_a0", load_blackfin, 0, 0 };
#endif
#ifdef CONFIG_BCM_PHY_BLACKFIN_B0
firmware_t blackfin_b0 = { "blackfin_b0", load_blackfin, 0, 0 };
#endif
#ifdef CONFIG_BCM_PHY_SHORTFIN_B0
firmware_t shortfin_b0 = { "shortfin_b0", load_shortfin, 0, 0 };
#endif
#if defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
// longfin A0 and B0 use same firmware dated April 2020 or later
firmware_t longfin_a0_m = { "longfin_a0", load_blackfin, 0, 1 };
firmware_t longfin_a0 = { "longfin_a0", load_blackfin, 0, 0 };
#endif
static firmware_t *firmware_list[] = {
#ifdef CONFIG_BCM_PHY_MAKO_A0
&mako_a0,
#endif
#ifdef CONFIG_BCM_PHY_ORCA_A0
&orca_a0,
#endif
#ifdef CONFIG_BCM_PHY_ORCA_B0
&orca_b0,
#endif
#ifdef CONFIG_BCM_PHY_BLACKFIN_A0
&blackfin_a0,
#endif
#ifdef CONFIG_BCM_PHY_BLACKFIN_B0
&blackfin_b0,
#endif
#if defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
&longfin_a0_m,
&longfin_a0,
#endif
#if defined(CONFIG_BCM_PHY_SHORTFIN_B0)
&shortfin_b0,
#endif
};
static phy_desc_t phy_desc[] = {
#ifdef CONFIG_BCM_PHY_MAKO_A0
{ 0xae02, 0x5048, "84860 A0", &mako_a0, INTER_PHY_TYPES_S1K2KI5I_M },
{ 0xae02, 0x5040, "84861 A0", &mako_a0, INTER_PHY_TYPES_S1K2KI5I_M },
#endif
#ifdef CONFIG_BCM_PHY_ORCA_A0
{ 0xae02, 0x5158, "84880 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5150, "84881 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5148, "84884 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5168, "84884E A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5178, "84885 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5170, "84886 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5144, "84887 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5140, "84888 A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5160, "84888E A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5174, "84888S A0", &orca_a0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
#endif
#ifdef CONFIG_BCM_PHY_ORCA_B0
{ 0xae02, 0x5159, "84880 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5151, "84881 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5149, "84884 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5169, "84884E B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5179, "84885 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI_M },
{ 0xae02, 0x5171, "84886 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5145, "84887 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5141, "84888 B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5161, "84888E B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
{ 0xae02, 0x5175, "84888S B0", &orca_b0, INTER_PHY_TYPES_US1K2KI5KI10R_M },
#endif
#ifdef CONFIG_BCM_PHY_BLACKFIN_A0
{ 0x3590, 0x5090, "84891 A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5094, "54991 A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x5098, "54991E A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x5080, "84891L A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5084, "54991L A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x5088, "54991EL A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50a0, "84892 A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50a4, "54992 A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x50a8, "54992E A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50b0, "84894 A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50b4, "54994 A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x50b8, "54994E A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50d0, "54991H A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50f0, "54994H A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50c8, "50991EL A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50f8, "50994E A0", &blackfin_a0, INTER_PHY_TYPES_US1K2KIR_M },
#endif
#ifdef CONFIG_BCM_PHY_BLACKFIN_B0
{ 0x3590, 0x5091, "84891 B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5095, "54991 B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x5099, "54991E B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x5081, "84891L B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5085, "54991L B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x5089, "54991EL B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50c9, "50991EL B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50a1, "84892 B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50a5, "54992 B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x50a9, "54992E B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50b1, "84894 B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50b5, "54994 B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x50b9, "54994E B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50d1, "54991H B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50f1, "54994H B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x50f9, "50994E B0", &blackfin_b0, INTER_PHY_TYPES_US1K2KIR_M },
#endif
#ifdef CONFIG_BCM_PHY_SHORTFIN_B0
{ 0x3590, 0x5001, "84898 B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x5005, "84896 B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x5009, "54998S B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x500d, "54998ES B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x5011, "54998 B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x5015, "54998E B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x5019, "54994L B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
{ 0x3590, 0x501d, "54994EL B0", &shortfin_b0, INTER_PHY_TYPE_USXGMII_MP_M },
#endif
#ifdef CONFIG_BCM_PHY_LONGFIN_A0
{ 0x3590, 0x5180, "84891LM A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5184, "54991LM A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5190, "84891M A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5194, "54991M A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x5198, "54991EM A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x5188, "54991ELM A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x51a0, "84892M A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51a4, "54992M A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x51a8, "54992EM A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x51b0, "84894M A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51b4, "54994M A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x51b8, "54994EM A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x51d0, "54991H A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51f0, "54994H A0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
#endif
#ifdef CONFIG_BCM_PHY_LONGFIN_B0
{ 0x3590, 0x5181, "84891LM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5185, "54991LM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5191, "84891M B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x5195, "54991M B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x5199, "54991EM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x5189, "54991ELM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x518d, "50991ELM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x51a1, "84892M B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51a5, "54992M B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x51a9, "54992EM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x51b1, "84894M B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51b5, "54994M B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M },
{ 0x3590, 0x51b9, "54994EM B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M },
{ 0x3590, 0x50c1, "49418 ", &longfin_a0, INTER_PHY_TYPES_US1K2KIR5KIR_M }, // 4912 integrated XGPHY
{ 0x3590, 0x51c1, "49418M ", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR_M }, // 4912 integrated XGPHY
{ 0x3590, 0x50cd, "4912 ", &longfin_a0, INTER_PHY_TYPES_US1K2KIR_M }, // 4912 integrated XGPHY
{ 0x3590, 0x51cd, "4912M ", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR_M }, // 4912 integrated XGPHY
{ 0x3590, 0x51d1, "54991H B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51d5, "54991SK B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51f1, "54994H B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
{ 0x3590, 0x51f5, "54994SK B0", &longfin_a0_m, INTER_PHY_TYPES_US1K2KIR5KIR10R_M },
#endif
};
static uint32_t enabled_phys;
static uint32_t macsec_phys;
bus_drv_t *bus_drv;
#define BUS_READ(a, b, c, d) if ((ret = _bus_read(a, b, c, d))) goto Exit;
#define BUS_WRITE(a, b, c, d) if ((ret = _bus_write(a, b, c, d))) goto Exit;
#define BUS_WRITE_ALL(a, b, c, d) if ((ret = _bus_write_all(a, b, c, d))) goto Exit;
#define BUS_WRITE_AND_VERIFY_ALL(a, b, c, d, e) if ((ret = _bus_write_and_verify_all(a, b, c, d, e))) goto Exit;
#define PHY_READ(a, b, c, d) if ((ret = phy_bus_c45_read(a, b, c, d))) goto Exit;
#define PHY_WRITE(a, b, c, d) if ((ret = phy_bus_c45_write(a, b, c, d))) goto Exit;
/* Command codes */
#define CMD_GET_PAIR_SWAP 0x8000
#define CMD_SET_PAIR_SWAP 0x8001
#define CMD_GET_1588_ENABLE 0x8004
#define CMD_SET_1588_ENABLE 0x8005
#define CMD_GET_SHORT_REACH_MODE_ENABLE 0x8006
#define CMD_SET_SHORT_REACH_MODE_ENABLE 0x8007
#define CMD_GET_EEE_MODE 0x8008
#define CMD_SET_EEE_MODE 0x8009
#define CMD_GET_EMI_MODE_ENABLE 0x800A
#define CMD_SET_EMI_MODE_ENABLE 0x800B
#define CMD_GET_SUB_LF_RF_STATUS 0x800D
#define CMD_GET_SERDES_KR_MODE_ENABLE 0x800E
#define CMD_SET_SERDES_KR_MODE_ENABLE 0x800F
#define CMD_CLEAR_SUB_LF_RF 0x8010
#define CMD_SET_SUB_LF_RF 0x8011
#define CMD_READ_INDIRECT_GPHY_REG_BITS 0x8014
#define CMD_WRITE_INDIRECT_GPHY_REG_BITS 0x8015
#define CMD_GET_XFI_2P5G_5G_MODE 0x8016
#define CMD_SET_XFI_2P5G_5G_MODE 0x8017
#define CMD_GET_TWO_PAIR_1G_MODE 0x8018
#define CMD_SET_TWO_PAIR_1G_MODE 0x8019
#define CMD_SET_EEE_STATISTICS 0x801A
#define CMD_GET_EEE_STATISTICS 0x801B
#define CMD_SET_JUMBO_PACKET 0x801C
#define CMD_GET_JUMBO_PACKET 0x801D
#define CMD_GET_MSE 0x801E
#define CMD_GET_PAUSE_FRAME_MODE 0x801F
#define CMD_SET_PAUSE_FRAME_MODE 0x8020
#define CMD_GET_LED_TYPE 0x8021
#define CMD_SET_LED_TYPE 0x8022
#define CMD_GET_MGBASE_T_802_3BZ_TYPE 0x8023
#define CMD_SET_MGBASE_T_802_3BZ_TYPE 0x8024
#define CMD_GET_MSE_GPHY 0x8025
#define CMD_SET_USXGMII 0x8026
#define CMD_GET_USXGMII 0x8027
#define CMD_GET_XL_MODE 0x8029
#define CMD_SET_XL_MODE 0x802A
#define CMD_GET_XFI_TX_FILTERS 0x802B
#define CMD_SET_XFI_TX_FILTERS 0x802C
#define CMD_GET_XFI_POLARITY 0x802D
#define CMD_SET_XFI_POLARITY 0x802E
#define CMD_GET_CURRENT_VOLTAGE 0x802F
#define CMD_GET_SNR 0x8030
#define CMD_GET_CURRENT_TEMP 0x8031
#define CMD_SET_UPPER_TEMP_WARNING_LEVEL 0x8032
#define CMD_GET_UPPER_TEMP_WARNING_LEVEL 0x8033
#define CMD_SET_LOWER_TEMP_WARNING_LEVEL 0x8034
#define CMD_GET_LOWER_TEMP_WARNING_LEVEL 0x8035
#define CMD_GET_HW_FR_EMI_MODE_ENABLE 0x803A
#define CMD_SET_HW_FR_EMI_MODE_ENABLE 0x803B
#define CMD_GET_CUSTOMER_REQUESTED_TX_PWR_ADJUST 0x8040
#define CMD_SET_CUSTOMER_REQUESTED_TX_PWR_ADJUST 0x8041
#define CMD_GET_DYNAMIC_PARTITION_SELECT 0x8042
#define CMD_SET_DYNAMIC_PARTITION_SELECT 0x8043
#define CMD_SET_MACSEC_ENABLE 0x805E
#define CMD_GET_MACSEC_ENABLE 0x805F
#define CMD_RESET_STAT_LOG 0xC017
/* Command hanlder status codes */
#define CMD_RECEIVED 0x0001
#define CMD_IN_PROGRESS 0x0002
#define CMD_COMPLETE_PASS 0x0004
#define CMD_COMPLETE_ERROR 0x0008
#define CMD_SYSTEM_BUSY 0xBBBB
/* Fixups for 5499x phys */
#define ID1_5499X 0x35900000
#define ID1_MASK 0xffff0000
#define SUPER_I_DEFAULT (1<<15)
#define SUPER_I_BLACKFIN (1<<8)
#define CHANGE_STRAP_STATUS (1<<1)
#define STEPS 10
static int _wait_for_cmd_ready(phy_dev_t *phy_dev)
{
int ret, i;
uint16_t val;
for (i = 0; i < 1000; i++)
{
/* Read status of command */
PHY_READ(phy_dev, 0x1e, 0x4037, &val);
if (val != CMD_IN_PROGRESS && val != CMD_SYSTEM_BUSY)
return 0;
udelay(2000);
}
printk("Timed out waiting for command ready");
Exit:
return -1;
}
static uint16_t _wait_for_cmd_complete(phy_dev_t *phy_dev)
{
int ret, i;
uint16_t val = 0;
for (i = 0; i < 1000; i++)
{
/* Read status of command */
PHY_READ(phy_dev, 0x1e, 0x4037, &val);
if (val == CMD_COMPLETE_PASS || val == CMD_COMPLETE_ERROR)
goto Exit;
udelay(2000);
}
printk("Timed out waiting for command complete\n");
Exit:
return val;
}
int cmd_handler(phy_dev_t *phy_dev, uint16_t cmd_code, uint16_t *data1, uint16_t *data2, uint16_t *data3, uint16_t *data4, uint16_t *data5)
{
int ret;
uint16_t cmd_status = 0;
/* Make sure command interface is open */
if ((ret = _wait_for_cmd_ready(phy_dev)))
goto Exit;
switch (cmd_code)
{
case CMD_SET_PAIR_SWAP:
case CMD_SET_1588_ENABLE:
case CMD_SET_SHORT_REACH_MODE_ENABLE:
case CMD_SET_EEE_MODE:
case CMD_SET_EMI_MODE_ENABLE:
case CMD_SET_SERDES_KR_MODE_ENABLE:
case CMD_CLEAR_SUB_LF_RF:
case CMD_SET_SUB_LF_RF:
case CMD_WRITE_INDIRECT_GPHY_REG_BITS:
case CMD_SET_XFI_2P5G_5G_MODE:
case CMD_SET_TWO_PAIR_1G_MODE:
case CMD_SET_PAUSE_FRAME_MODE:
case CMD_SET_LED_TYPE:
case CMD_SET_MGBASE_T_802_3BZ_TYPE:
case CMD_SET_USXGMII:
case CMD_SET_EEE_STATISTICS:
case CMD_SET_JUMBO_PACKET:
case CMD_SET_XL_MODE:
case CMD_SET_XFI_TX_FILTERS:
case CMD_SET_XFI_POLARITY:
case CMD_SET_UPPER_TEMP_WARNING_LEVEL:
case CMD_SET_LOWER_TEMP_WARNING_LEVEL:
case CMD_SET_HW_FR_EMI_MODE_ENABLE:
case CMD_SET_CUSTOMER_REQUESTED_TX_PWR_ADJUST:
case CMD_SET_DYNAMIC_PARTITION_SELECT:
case CMD_SET_MACSEC_ENABLE:
{
if (data1)
PHY_WRITE(phy_dev, 0x1e, 0x4038, *data1);
if (data2)
PHY_WRITE(phy_dev, 0x1e, 0x4039, *data2);
if (data3)
PHY_WRITE(phy_dev, 0x1e, 0x403a, *data3);
if (data4)
PHY_WRITE(phy_dev, 0x1e, 0x403b, *data4);
if (data5)
PHY_WRITE(phy_dev, 0x1e, 0x403c, *data5);
PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
cmd_status = _wait_for_cmd_complete(phy_dev);
break;
}
case CMD_GET_PAIR_SWAP:
case CMD_GET_1588_ENABLE:
case CMD_GET_SHORT_REACH_MODE_ENABLE:
case CMD_GET_EEE_MODE:
case CMD_GET_EMI_MODE_ENABLE:
case CMD_GET_SERDES_KR_MODE_ENABLE:
case CMD_GET_SUB_LF_RF_STATUS:
case CMD_GET_XFI_2P5G_5G_MODE:
case CMD_GET_TWO_PAIR_1G_MODE:
case CMD_GET_PAUSE_FRAME_MODE:
case CMD_GET_LED_TYPE:
case CMD_GET_MGBASE_T_802_3BZ_TYPE:
case CMD_GET_MSE_GPHY:
case CMD_GET_USXGMII:
case CMD_GET_JUMBO_PACKET:
case CMD_GET_MSE:
case CMD_GET_XL_MODE:
case CMD_GET_XFI_TX_FILTERS:
case CMD_GET_XFI_POLARITY:
case CMD_GET_CURRENT_VOLTAGE:
case CMD_GET_SNR:
case CMD_GET_CURRENT_TEMP:
case CMD_GET_UPPER_TEMP_WARNING_LEVEL:
case CMD_GET_LOWER_TEMP_WARNING_LEVEL:
case CMD_GET_HW_FR_EMI_MODE_ENABLE:
case CMD_GET_CUSTOMER_REQUESTED_TX_PWR_ADJUST:
case CMD_GET_DYNAMIC_PARTITION_SELECT:
case CMD_GET_MACSEC_ENABLE:
case CMD_RESET_STAT_LOG:
{
PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
cmd_status = _wait_for_cmd_complete(phy_dev);
if (data1)
PHY_READ(phy_dev, 0x1e, 0x4038, data1);
if (data2)
PHY_READ(phy_dev, 0x1e, 0x4039, data2);
if (data3)
PHY_READ(phy_dev, 0x1e, 0x403a, data3);
if (data4)
PHY_READ(phy_dev, 0x1e, 0x403b, data4);
if (data5)
PHY_READ(phy_dev, 0x1e, 0x403c, data5);
break;
}
case CMD_READ_INDIRECT_GPHY_REG_BITS:
{
if (data1)
PHY_WRITE(phy_dev, 0x1e, 0x4038, *data1);
if (data2)
PHY_WRITE(phy_dev, 0x1e, 0x4039, *data2);
if (data3)
PHY_WRITE(phy_dev, 0x1e, 0x403a, *data3);
if (data4)
PHY_WRITE(phy_dev, 0x1e, 0x403b, *data4);
PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
cmd_status = _wait_for_cmd_complete(phy_dev);
if (data5)
PHY_READ(phy_dev, 0x1e, 0x403c, data5);
break;
}
case CMD_GET_EEE_STATISTICS:
{
if (data1)
PHY_WRITE(phy_dev, 0x1e, 0x4038, *data1);
PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
cmd_status = _wait_for_cmd_complete(phy_dev);
if (data2)
PHY_READ(phy_dev, 0x1e, 0x4039, data2);
if (data3)
PHY_READ(phy_dev, 0x1e, 0x403a, data3);
if (data4)
PHY_READ(phy_dev, 0x1e, 0x403b, data4);
if (data5)
PHY_READ(phy_dev, 0x1e, 0x403c, data5);
break;
}
default:
printk("Unsupported cmd code: 0x%x\n", cmd_code);
break;
}
if (cmd_status != CMD_COMPLETE_PASS)
{
printk("Failed to execute cmd code: 0x%x\n", cmd_code);
return -1;
}
Exit:
return ret;
}
static phy_desc_t *_phy_get_ext3_desc_by_phyid(int phyid1, int phyid2)
{
int j;
for (j = 0; j < sizeof(phy_desc)/sizeof(phy_desc[0]); j++)
{
if (phy_desc[j].phyid1 != phyid1 || phy_desc[j].phyid2 != phyid2)
continue;
return &phy_desc[j];
}
return 0;
}
static phy_desc_t *_phy_get_ext3_desc(phy_dev_t *phy_dev)
{
uint16_t phyid1, phyid2;
int ret;
PHY_READ(phy_dev, 0x01, 0x0002, &phyid1);
PHY_READ(phy_dev, 0x01, 0x0003, &phyid2);
return _phy_get_ext3_desc_by_phyid(phyid1, phyid2);
Exit:
return 0;
}
static void serdes_register_read(phy_dev_t *phy_dev, int dev, int reg, uint16_t *val)
{
int ret;
PHY_WRITE(phy_dev, 0x1e, 0x4110, 0x2004);
PHY_READ(phy_dev, dev, reg, val);
PHY_WRITE(phy_dev, 0x1e, 0x4110, 0x0001);
Exit:
return;
}
static void serdes_register_write(phy_dev_t *phy_dev, int dev, int reg, uint16_t val)
{
int ret;
PHY_WRITE(phy_dev, 0x1e, 0x4110, 0x2004);
PHY_WRITE(phy_dev, dev, reg, val);
PHY_WRITE(phy_dev, 0x1e, 0x4110, 0x0001);
Exit:
return;
}
void phy_shortfin_short_amble_workaround(phy_dev_t *phy_dev)
{
uint16_t val;
static uint16_t reg_save, reg_1c600h_default, reg_1c6e2h_default;
return;
if (!phy_dev->descriptor)
{
phy_dev->descriptor = _phy_get_ext3_desc(phy_dev);
if (!phy_dev->descriptor)
return;
}
if (((phy_desc_t *)phy_dev->descriptor)->firmware != &shortfin_b0)
return;
if (!reg_save)
{
serdes_register_read(phy_dev, 0x01, 0xc600, ®_1c600h_default);
serdes_register_read(phy_dev, 0x01, 0xc6e2, ®_1c6e2h_default);
reg_save = 1;
}
if (phy_dev->link == 0)
return;
if (phy_dev->speed == PHY_SPEED_1000)
{
serdes_register_read(phy_dev, 0x01, 0xc600, &val);
val &= ~0x000f;
/* (en_1588_rxtx_phy.3) */
val |= 0x0003;
/* (sel_int_extclk phy,0) */
val |= 0x0004;
serdes_register_write(phy_dev, 0x01, 0xc600, val);
serdes_register_read(phy_dev, 0x01, 0xc6e2, &val);
/* (en_preabmle_fix phy ,1) */
val &= ~0x0cc0;
val |= ((0x0 & 0x3) << 6);
val |= ((0x3 & 0x3) << 10);
serdes_register_write(phy_dev, 0x01, 0xc6e2, val);
}
else
{
serdes_register_write(phy_dev, 0x01, 0xc600, reg_1c600h_default);
serdes_register_write(phy_dev, 0x01, 0xc6e2, reg_1c6e2h_default);
}
return;
}
static int _phy_power_get(phy_dev_t *phy_dev, int *enable)
{
uint16_t val;
int ret;
PHY_READ(phy_dev, 0x01, 0x0000, &val);
*enable = (val & (1 << 11)) ? 0 : 1;
Exit:
return ret;
}
static int _phy_power_set(phy_dev_t *phy_dev, int enable)
{
uint16_t val;
int ret;
PHY_READ(phy_dev, 0x01, 0x0000, &val);
if (enable)
val &= ~(1 << 11); /* Power up */
else
val |= (1 << 11); /* Power down */
PHY_WRITE(phy_dev, 0x01, 0x0000, val);
Exit:
return ret;
}
#define XFI_MODE_IDLE_STUFFING 0 /* Idle Stuffing mode over XFI interface */
#define XFI_MODE_BASE_X 1 /* 2.5GBase-X or 5GBase-X */
#define XFI_MODE_BASE_R 2 /* 2.5GBase-R or 5GBase-R */
#if !defined(DSL_DEVICES)
static int _phy_inter_phy_types_set(phy_dev_t *phy_dev, inter_phy_type_t inter_phy_types)
{
int ret;
uint16_t data1, data2, data3, data4, data5;
data1 = XFI_MODE_BASE_X ; /* XFI mode in 2.5G speed */
data2 = XFI_MODE_BASE_X ; /* XFI mode in 5G speed */
if (inter_phy_types & INTER_PHY_TYPE_2P5GBASE_R_M)
data1 = XFI_MODE_BASE_R;
if (inter_phy_types & INTER_PHY_TYPE_2P5GIDLE_M)
data1 = XFI_MODE_IDLE_STUFFING;
if (inter_phy_types & INTER_PHY_TYPE_5GBASE_R_M)
data2 = XFI_MODE_BASE_R;
if (inter_phy_types & INTER_PHY_TYPE_5GIDLE_M)
data2 = XFI_MODE_IDLE_STUFFING;
/* Set XFI modes for 2.5G and 5G */
if ((ret = cmd_handler(phy_dev, CMD_SET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL)))
goto Exit;
/* Configure USXGMII mode */
data1 = inter_phy_types & (INTER_PHY_TYPE_USXGMII_M | INTER_PHY_TYPE_USXGMII_MP_M)? 1 : 0; /* Enable */
data2 = 1; /* AN,*/
data3 = 0x124; /* baud rate 10G, quad speed 2.5G */
data4 = 0; /* 0 = Broadcom mode */
data5 = 0; /* 0 = MAC/PHY frequency is locked without PPM offset */
if ((ret = cmd_handler(phy_dev, CMD_SET_USXGMII, &data1, &data2, &data3, &data4, &data5)))
goto Exit;
Exit:
return ret;
}
static int _phy_led_control_mode_set(phy_dev_t *phy_dev, int user_control)
{
int ret = 0;
/* uint16_t val = user_control ? 1 : 0; */
/* Set led control to user or firmware */
/*if ((ret = cmd_handler(phy_dev, CMD_SET_LED_TYPE, &val, NULL, NULL, NULL, NULL)))
goto Exit;
Exit:*/
return ret;
}
#endif
static int inter_phy_current_types_2p5g_5g_get(phy_dev_t *phy_dev, uint32_t *types)
{
int rc = 0;
uint16_t data1, data2;
*types = 0;
rc = cmd_handler(phy_dev, CMD_GET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL);
switch(data1)
{
case 0:
*types |= INTER_PHY_TYPE_2P5GIDLE_M;
break;
case 1:
*types |= INTER_PHY_TYPE_2500BASE_X_M;
break;
case 2:
*types |= INTER_PHY_TYPE_2P5GBASE_R_M;
break;
}
switch(data2)
{
case 0:
*types |= INTER_PHY_TYPE_5GIDLE_M;
break;
case 1:
*types |= INTER_PHY_TYPE_5000BASE_X_M;
break;
case 2:
*types |= INTER_PHY_TYPE_5GBASE_R_M;
break;
}
return 0;
}
static int inter_phy_type_usxgmii_get(phy_dev_t *phy_dev)
{
uint16_t data1, data2, data3;
cmd_handler(phy_dev, CMD_GET_USXGMII, &data1, &data2, &data3, NULL, NULL);
return data1 > 0;
}
static int inter_type_max_speed(phy_dev_t *phy_dev);
static inter_phy_type_t _phy_current_inter_phy_type_get(phy_dev_t *phy_dev)
{
uint32_t sw_types, hw_types;
uint32_t types;
phy_dev_configured_inter_phy_types_get(phy_dev, &sw_types);
if (inter_phy_type_usxgmii_get(phy_dev))
{
phy_dev_inter_phy_types_get(phy_dev, INTER_PHY_TYPE_UP, &types);
if (types & INTER_PHY_TYPE_USXGMII_MP_M)
return INTER_PHY_TYPE_USXGMII_MP;
else
return INTER_PHY_TYPE_USXGMII;
}
if (inter_type_max_speed(phy_dev) <= PHY_SPEED_1000 &&
sw_types & INTER_PHY_TYPE_SGMII_M)
return INTER_PHY_TYPE_SGMII;
if (!phy_dev->link)
return INTER_PHY_TYPE_UNKNOWN;
inter_phy_current_types_2p5g_5g_get(phy_dev, &hw_types);
switch(phy_dev->speed)
{
case PHY_SPEED_100:
case PHY_SPEED_1000:
if (sw_types & INTER_PHY_TYPE_SGMII_M)
return INTER_PHY_TYPE_SGMII;
return INTER_PHY_TYPE_UNKNOWN; /* Bug */
case PHY_SPEED_2500:
if (hw_types & INTER_PHY_TYPE_2P5GBASE_R_M)
return INTER_PHY_TYPE_2P5GBASE_R;
if (hw_types & INTER_PHY_TYPE_2500BASE_X_M)
return INTER_PHY_TYPE_2500BASE_X;
if (hw_types & INTER_PHY_TYPE_2P5GIDLE_M)
return INTER_PHY_TYPE_2P5GIDLE;
return INTER_PHY_TYPE_UNKNOWN; /* Bug */
case PHY_SPEED_5000:
if (hw_types & INTER_PHY_TYPE_5GBASE_R_M)
return INTER_PHY_TYPE_5GBASE_R;
if (hw_types & INTER_PHY_TYPE_5000BASE_X_M)
return INTER_PHY_TYPE_5000BASE_X;
if (hw_types & INTER_PHY_TYPE_5GIDLE_M)
return INTER_PHY_TYPE_5GIDLE;
return INTER_PHY_TYPE_UNKNOWN; /* Bug */
case PHY_SPEED_10000:
return INTER_PHY_TYPE_10GBASE_R;
default:
break;
}
return INTER_PHY_TYPE_UNKNOWN; /* Bug */
}
static int inter_type_max_speed(phy_dev_t *phy_dev)
{
uint32_t caps;
phy_dev_caps_get(phy_dev, CAPS_TYPE_SUPPORTED, &caps);
return phy_caps_to_max_speed(caps);
}
static int inter_phy_type_usxgmii_set(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, inter_phy_type_t type)
{
int rc = 0;
uint16_t data1, data2, data3, data4, data5;
phy_speed_t speed;
rc = cmd_handler(phy_dev, CMD_GET_USXGMII, &data1, &data2, &data3, NULL, NULL);
data1 = type == INTER_PHY_TYPE_USXGMII; /* Enable/Disable bit */
data2 = 1; /* AN, only on */
if (data1)
{
switch (phy_dev->usxgmii_m_type)
{
case USXGMII_S:
speed = inter_type_max_speed(phy_dev);
if (speed >= PHY_SPEED_10000)
data3 = 4;
else if (speed >= PHY_SPEED_5000)
data3 = 2;
else
data3 = 1;
break;
/* data sheet values */
/*
case USXGMII_M_10G_Q:
data3 = (1<<8);
break;
case USXGMII_M_10G_D:
data3 = (2<<8);
break;
case USXGMII_M_10G_S:
data3 = (4<<8);
break;
*/
/* PLP script values */
case USXGMII_M_10G_Q:
case USXGMII_M_10G_D:
case USXGMII_M_10G_S:
data3 = 0x124;
data4 = 0; /* 0 = Broadcom mode */
data5 = 0; /* 0 = MAC/PHY frequency is locked without PPM offset */
break;
default:
printk("No supported USXGMII mode: %d\n", phy_dev->usxgmii_m_type);
return -1;
}
}
rc += cmd_handler(phy_dev, CMD_SET_USXGMII, &data1, &data2, &data3, NULL, NULL);
return rc;
}
static int inter_phy_type_2P5G5G_set(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, inter_phy_type_t type)
{
int rc = 0;
uint16_t data1, data2;
rc = cmd_handler(phy_dev, CMD_GET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL);
switch(type)
{
case INTER_PHY_TYPE_2P5GIDLE:
data1 = XFI_MODE_IDLE_STUFFING;
break;
case INTER_PHY_TYPE_2500BASE_X:
data1 = XFI_MODE_BASE_X;
break;
case INTER_PHY_TYPE_2P5GBASE_R:
data1 = XFI_MODE_BASE_R;
break;
case INTER_PHY_TYPE_5GIDLE:
data2 = XFI_MODE_IDLE_STUFFING;
break;
case INTER_PHY_TYPE_5000BASE_X:
data2 = XFI_MODE_BASE_X;
break;
case INTER_PHY_TYPE_5GBASE_R:
data2 = XFI_MODE_BASE_R;
break;
default:
/* do nothing */
break;
}
rc += cmd_handler(phy_dev, CMD_SET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL);
return rc;
}
static int _phy_configured_inter_phy_types_set(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t types)
{
int rc = 0;
inter_phy_type_t best_type;
int disable_usxgmii;
best_type = phy_get_best_inter_phy_configure_type(phy_dev, types, PHY_SPEED_2500);
if (best_type == INTER_PHY_TYPE_USXGMII || best_type == INTER_PHY_TYPE_USXGMII_MP)
{
inter_phy_type_usxgmii_set(phy_dev, if_dir, INTER_PHY_TYPE_USXGMII);
phy_dev->current_inter_phy_type = best_type;
return 0;
}
if (best_type != INTER_PHY_TYPE_UNKNOWN)
{
rc += inter_phy_type_2P5G5G_set(phy_dev, if_dir, best_type);
disable_usxgmii = 1;
}
best_type = phy_get_best_inter_phy_configure_type(phy_dev, types, PHY_SPEED_5000);
if (best_type != INTER_PHY_TYPE_UNKNOWN)
{
rc += inter_phy_type_2P5G5G_set(phy_dev, if_dir, best_type);
disable_usxgmii = 1;
}
if (disable_usxgmii)
rc += inter_phy_type_usxgmii_set(phy_dev, if_dir, best_type);
return rc;
}
static int _phy_force_auto_mdix_set(phy_dev_t *phy_dev, int enable)
{
int ret;
uint16_t val;
PHY_READ(phy_dev, 0x07, 0x902f, &val);
if (enable)
val |= (1 << 9); /* Auto-MDIX enabled */
else
val &= ~(1 << 9); /* Auto-MDIX disabled */
PHY_WRITE(phy_dev, 0x07, 0x902f, val);
Exit:
return ret;
}
static int _phy_force_auto_mdix_get(phy_dev_t *phy_dev, int *enable)
{
int ret;
uint16_t val;
PHY_READ(phy_dev, 0x07, 0x902f, &val);
*enable = val & (1 << 9) ? 1 : 0; /* Force Auto MDIX Enabled */
Exit:
return ret;
}