/
drcbex64.cpp
6972 lines (5926 loc) · 254 KB
/
drcbex64.cpp
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// license:BSD-3-Clause
// copyright-holders:Aaron Giles
/***************************************************************************
drcbex64.c
64-bit x64 back-end for the universal machine language.
****************************************************************************
Future improvements/changes:
* Add support for FP registers
* Optimize to avoid unnecessary reloads
* Identify common pairs and optimize output
* Convert SUB a,0,b to NEG
* Optimize, e.g., and [r5],i0,$FF to use rbx as temporary register
(avoid initial move) if i0 is not needed going forward
****************************************************************************
-------------------------
ABI/conventions (Windows)
-------------------------
Registers:
RAX - volatile, function return value
RBX - non-volatile
RCX - volatile, integer function parameter 1
RDX - volatile, integer function parameter 2
RSI - non-volatile
RDI - non-volatile
RBP - non-volatile
R8 - volatile, integer function parameter 3
R9 - volatile, integer function parameter 4
R10 - volatile
R11 - volatile, scratch immediate storage
R12 - non-volatile
R13 - non-volatile
R14 - non-volatile
R15 - non-volatile
XMM0 - volatile, FP function parameter 1
XMM1 - volatile, FP function parameter 2
XMM2 - volatile, FP function parameter 3
XMM3 - volatile, FP function parameter 4
XMM4 - volatile
XMM5 - volatile
XMM6 - non-volatile
XMM7 - non-volatile
XMM8 - non-volatile
XMM9 - non-volatile
XMM10 - non-volatile
XMM11 - non-volatile
XMM12 - non-volatile
XMM13 - non-volatile
XMM14 - non-volatile
XMM15 - non-volatile
-----------------------------
ABI/conventions (Linux/MacOS)
-----------------------------
Registers:
RAX - volatile, function return value
RBX - non-volatile
RCX - volatile, integer function parameter 4
RDX - volatile, integer function parameter 3
RSI - volatile, integer function parameter 2
RDI - volatile, integer function parameter 1
RBP - non-volatile
R8 - volatile, integer function parameter 5
R9 - volatile, integer function parameter 6
R10 - volatile
R11 - volatile, scratch immediate storage
R12 - non-volatile
R13 - non-volatile
R14 - non-volatile
R15 - non-volatile
XMM0 - volatile, FP function parameter 1
XMM1 - volatile, FP function parameter 2
XMM2 - volatile, FP function parameter 3
XMM3 - volatile, FP function parameter 4
XMM4 - volatile
XMM5 - volatile
XMM6 - volatile
XMM7 - volatile
XMM8 - volatile
XMM9 - volatile
XMM10 - volatile
XMM11 - volatile
XMM12 - volatile
XMM13 - volatile
XMM14 - volatile
XMM15 - volatile
---------------
Execution model
---------------
Registers (Windows):
RAX - scratch register
RBX - maps to I0
RCX - scratch register
RDX - scratch register
RSI - maps to I1
RDI - maps to I2
RBP - pointer to code cache
R8 - scratch register
R9 - scratch register
R10 - scratch register
R11 - scratch register
R12 - maps to I3
R13 - maps to I4
R14 - maps to I5
R15 - maps to I6
Registers (Linux/MacOS):
RAX - scratch register
RBX - maps to I0
RCX - scratch register
RDX - scratch register
RSI - unused
RDI - unused
RBP - pointer to code cache
R8 - scratch register
R9 - scratch register
R10 - scratch register
R11 - scratch register
R12 - maps to I1
R13 - maps to I2
R14 - maps to I3
R15 - maps to I4
Entry point:
Assumes 1 parameter passed, which is the codeptr of the code
to execute once the environment is set up.
Exit point:
Assumes exit value is in RAX.
Entry stack:
[rsp] - return
Runtime stack:
[rsp] - r9 home
[rsp+8] - r8 home
[rsp+16] - rdx home
[rsp+24] - rcx home
[rsp+40] - saved r15
[rsp+48] - saved r14
[rsp+56] - saved r13
[rsp+64] - saved r12
[rsp+72] - saved ebp
[rsp+80] - saved edi
[rsp+88] - saved esi
[rsp+96] - saved ebx
[rsp+104] - ret
***************************************************************************/
#include <cstddef>
#include "emu.h"
#include "debugger.h"
#include "emuopts.h"
#include "drcuml.h"
#include "drcbex64.h"
// This is a trick to make it build on Android where the ARM SDK declares ::REG_Rn
// and the x64 SDK declares ::REG_Exx and ::REG_Rxx
namespace drc {
using namespace uml;
using namespace x64emit;
using x64emit::REG_EAX;
using x64emit::REG_ECX;
using x64emit::REG_EDX;
using x64emit::REG_RAX;
using x64emit::REG_RCX;
using x64emit::REG_RDX;
using x64emit::REG_RBX;
using x64emit::REG_RSP;
using x64emit::REG_RBP;
using x64emit::REG_RSI;
using x64emit::REG_RDI;
using x64emit::REG_R8;
using x64emit::REG_R9;
using x64emit::REG_R10;
using x64emit::REG_R11;
using x64emit::REG_R12;
using x64emit::REG_R13;
using x64emit::REG_R14;
using x64emit::REG_R15;
//**************************************************************************
// DEBUGGING
//**************************************************************************
#define LOG_HASHJMPS (0)
#define USE_RCPSS_FOR_SINGLES (0)
#define USE_RSQRTSS_FOR_SINGLES (0)
#define USE_RCPSS_FOR_DOUBLES (0)
#define USE_RSQRTSS_FOR_DOUBLES (0)
//**************************************************************************
// CONSTANTS
//**************************************************************************
const uint32_t PTYPE_M = 1 << parameter::PTYPE_MEMORY;
const uint32_t PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE;
const uint32_t PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER;
const uint32_t PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER;
//const uint32_t PTYPE_MI = PTYPE_M | PTYPE_I;
//const uint32_t PTYPE_RI = PTYPE_R | PTYPE_I;
const uint32_t PTYPE_MR = PTYPE_M | PTYPE_R;
const uint32_t PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I;
const uint32_t PTYPE_MF = PTYPE_M | PTYPE_F;
#ifdef X64_WINDOWS_ABI
const int REG_PARAM1 = REG_RCX;
const int REG_PARAM2 = REG_RDX;
const int REG_PARAM3 = REG_R8;
const int REG_PARAM4 = REG_R9;
#else
const int REG_PARAM1 = REG_RDI;
const int REG_PARAM2 = REG_RSI;
const int REG_PARAM3 = REG_RDX;
const int REG_PARAM4 = REG_RCX;
#endif
//**************************************************************************
// MACROS
//**************************************************************************
#define X86_CONDITION(condition) (condition_map[condition - uml::COND_Z])
#define X86_NOT_CONDITION(condition) (condition_map[condition - uml::COND_Z] ^ 1)
inline x86_memref drcbe_x64::MABS(const void *ptr)
{
return MBD(REG_BP, offset_from_rbp(ptr));
}
#define assert_no_condition(inst) assert((inst).condition() == uml::COND_ALWAYS)
#define assert_any_condition(inst) assert((inst).condition() == uml::COND_ALWAYS || ((inst).condition() >= uml::COND_Z && (inst).condition() < uml::COND_MAX))
#define assert_no_flags(inst) assert((inst).flags() == 0)
#define assert_flags(inst, valid) assert(((inst).flags() & ~(valid)) == 0)
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
drcbe_x64::opcode_generate_func drcbe_x64::s_opcode_table[OP_MAX];
// size-to-mask table
//static const uint64_t size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, 0xffffffffffffffffU };
// register mapping tables
static const uint8_t int_register_map[REG_I_COUNT] =
{
#ifdef X64_WINDOWS_ABI
REG_RBX, REG_RSI, REG_RDI, REG_R12, REG_R13, REG_R14, REG_R15
#else
REG_RBX, REG_R12, REG_R13, REG_R14, REG_R15
#endif
};
static uint8_t float_register_map[REG_F_COUNT] =
{
#ifdef X64_WINDOWS_ABI
REG_XMM6, REG_XMM7, REG_XMM8, REG_XMM9, REG_XMM10, REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15
#else
// on AMD x64 ABI, XMM0-7 are FP function args. since this code has no args, and we
// save/restore them around CALLC, they should be safe for our use.
REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7
#endif
};
// condition mapping table
static const uint8_t condition_map[uml::COND_MAX - uml::COND_Z] =
{
x64emit::COND_Z, // COND_Z = 0x80, requires Z
x64emit::COND_NZ, // COND_NZ, requires Z
x64emit::COND_S, // COND_S, requires S
x64emit::COND_NS, // COND_NS, requires S
x64emit::COND_C, // COND_C, requires C
x64emit::COND_NC, // COND_NC, requires C
x64emit::COND_O, // COND_V, requires V
x64emit::COND_NO, // COND_NV, requires V
x64emit::COND_P, // COND_U, requires U
x64emit::COND_NP, // COND_NU, requires U
x64emit::COND_A, // COND_A, requires CZ
x64emit::COND_BE, // COND_BE, requires CZ
x64emit::COND_G, // COND_G, requires SVZ
x64emit::COND_LE, // COND_LE, requires SVZ
x64emit::COND_L, // COND_L, requires SV
x64emit::COND_GE, // COND_GE, requires SV
};
#if 0
// rounding mode mapping table
static const uint8_t fprnd_map[4] =
{
FPRND_CHOP, // ROUND_TRUNC, truncate
FPRND_NEAR, // ROUND_ROUND, round
FPRND_UP, // ROUND_CEIL, round up
FPRND_DOWN // ROUND_FLOOR round down
};
#endif
//**************************************************************************
// TABLES
//**************************************************************************
const drcbe_x64::opcode_table_entry drcbe_x64::s_opcode_table_source[] =
{
// Compile-time opcodes
{ uml::OP_HANDLE, &drcbe_x64::op_handle }, // HANDLE handle
{ uml::OP_HASH, &drcbe_x64::op_hash }, // HASH mode,pc
{ uml::OP_LABEL, &drcbe_x64::op_label }, // LABEL imm
{ uml::OP_COMMENT, &drcbe_x64::op_comment }, // COMMENT string
{ uml::OP_MAPVAR, &drcbe_x64::op_mapvar }, // MAPVAR mapvar,value
// Control Flow Operations
{ uml::OP_NOP, &drcbe_x64::op_nop }, // NOP
{ uml::OP_DEBUG, &drcbe_x64::op_debug }, // DEBUG pc
{ uml::OP_EXIT, &drcbe_x64::op_exit }, // EXIT src1[,c]
{ uml::OP_HASHJMP, &drcbe_x64::op_hashjmp }, // HASHJMP mode,pc,handle
{ uml::OP_JMP, &drcbe_x64::op_jmp }, // JMP imm[,c]
{ uml::OP_EXH, &drcbe_x64::op_exh }, // EXH handle,param[,c]
{ uml::OP_CALLH, &drcbe_x64::op_callh }, // CALLH handle[,c]
{ uml::OP_RET, &drcbe_x64::op_ret }, // RET [c]
{ uml::OP_CALLC, &drcbe_x64::op_callc }, // CALLC func,ptr[,c]
{ uml::OP_RECOVER, &drcbe_x64::op_recover }, // RECOVER dst,mapvar
// Internal Register Operations
{ uml::OP_SETFMOD, &drcbe_x64::op_setfmod }, // SETFMOD src
{ uml::OP_GETFMOD, &drcbe_x64::op_getfmod }, // GETFMOD dst
{ uml::OP_GETEXP, &drcbe_x64::op_getexp }, // GETEXP dst
{ uml::OP_GETFLGS, &drcbe_x64::op_getflgs }, // GETFLGS dst[,f]
{ uml::OP_SAVE, &drcbe_x64::op_save }, // SAVE dst
{ uml::OP_RESTORE, &drcbe_x64::op_restore }, // RESTORE dst
// Integer Operations
{ uml::OP_LOAD, &drcbe_x64::op_load }, // LOAD dst,base,index,size
{ uml::OP_LOADS, &drcbe_x64::op_loads }, // LOADS dst,base,index,size
{ uml::OP_STORE, &drcbe_x64::op_store }, // STORE base,index,src,size
{ uml::OP_READ, &drcbe_x64::op_read }, // READ dst,src1,spacesize
{ uml::OP_READM, &drcbe_x64::op_readm }, // READM dst,src1,mask,spacesize
{ uml::OP_WRITE, &drcbe_x64::op_write }, // WRITE dst,src1,spacesize
{ uml::OP_WRITEM, &drcbe_x64::op_writem }, // WRITEM dst,src1,spacesize
{ uml::OP_CARRY, &drcbe_x64::op_carry }, // CARRY src,bitnum
{ uml::OP_SET, &drcbe_x64::op_set }, // SET dst,c
{ uml::OP_MOV, &drcbe_x64::op_mov }, // MOV dst,src[,c]
{ uml::OP_SEXT, &drcbe_x64::op_sext }, // SEXT dst,src
{ uml::OP_ROLAND, &drcbe_x64::op_roland }, // ROLAND dst,src1,src2,src3
{ uml::OP_ROLINS, &drcbe_x64::op_rolins }, // ROLINS dst,src1,src2,src3
{ uml::OP_ADD, &drcbe_x64::op_add }, // ADD dst,src1,src2[,f]
{ uml::OP_ADDC, &drcbe_x64::op_addc }, // ADDC dst,src1,src2[,f]
{ uml::OP_SUB, &drcbe_x64::op_sub }, // SUB dst,src1,src2[,f]
{ uml::OP_SUBB, &drcbe_x64::op_subc }, // SUBB dst,src1,src2[,f]
{ uml::OP_CMP, &drcbe_x64::op_cmp }, // CMP src1,src2[,f]
{ uml::OP_MULU, &drcbe_x64::op_mulu }, // MULU dst,edst,src1,src2[,f]
{ uml::OP_MULS, &drcbe_x64::op_muls }, // MULS dst,edst,src1,src2[,f]
{ uml::OP_DIVU, &drcbe_x64::op_divu }, // DIVU dst,edst,src1,src2[,f]
{ uml::OP_DIVS, &drcbe_x64::op_divs }, // DIVS dst,edst,src1,src2[,f]
{ uml::OP_AND, &drcbe_x64::op_and }, // AND dst,src1,src2[,f]
{ uml::OP_TEST, &drcbe_x64::op_test }, // TEST src1,src2[,f]
{ uml::OP_OR, &drcbe_x64::op_or }, // OR dst,src1,src2[,f]
{ uml::OP_XOR, &drcbe_x64::op_xor }, // XOR dst,src1,src2[,f]
{ uml::OP_LZCNT, &drcbe_x64::op_lzcnt }, // LZCNT dst,src[,f]
{ uml::OP_TZCNT, &drcbe_x64::op_tzcnt }, // TZCNT dst,src[,f]
{ uml::OP_BSWAP, &drcbe_x64::op_bswap }, // BSWAP dst,src
{ uml::OP_SHL, &drcbe_x64::op_shl }, // SHL dst,src,count[,f]
{ uml::OP_SHR, &drcbe_x64::op_shr }, // SHR dst,src,count[,f]
{ uml::OP_SAR, &drcbe_x64::op_sar }, // SAR dst,src,count[,f]
{ uml::OP_ROL, &drcbe_x64::op_rol }, // ROL dst,src,count[,f]
{ uml::OP_ROLC, &drcbe_x64::op_rolc }, // ROLC dst,src,count[,f]
{ uml::OP_ROR, &drcbe_x64::op_ror }, // ROR dst,src,count[,f]
{ uml::OP_RORC, &drcbe_x64::op_rorc }, // RORC dst,src,count[,f]
// Floating Point Operations
{ uml::OP_FLOAD, &drcbe_x64::op_fload }, // FLOAD dst,base,index
{ uml::OP_FSTORE, &drcbe_x64::op_fstore }, // FSTORE base,index,src
{ uml::OP_FREAD, &drcbe_x64::op_fread }, // FREAD dst,space,src1
{ uml::OP_FWRITE, &drcbe_x64::op_fwrite }, // FWRITE space,dst,src1
{ uml::OP_FMOV, &drcbe_x64::op_fmov }, // FMOV dst,src1[,c]
{ uml::OP_FTOINT, &drcbe_x64::op_ftoint }, // FTOINT dst,src1,size,round
{ uml::OP_FFRINT, &drcbe_x64::op_ffrint }, // FFRINT dst,src1,size
{ uml::OP_FFRFLT, &drcbe_x64::op_ffrflt }, // FFRFLT dst,src1,size
{ uml::OP_FRNDS, &drcbe_x64::op_frnds }, // FRNDS dst,src1
{ uml::OP_FADD, &drcbe_x64::op_fadd }, // FADD dst,src1,src2
{ uml::OP_FSUB, &drcbe_x64::op_fsub }, // FSUB dst,src1,src2
{ uml::OP_FCMP, &drcbe_x64::op_fcmp }, // FCMP src1,src2
{ uml::OP_FMUL, &drcbe_x64::op_fmul }, // FMUL dst,src1,src2
{ uml::OP_FDIV, &drcbe_x64::op_fdiv }, // FDIV dst,src1,src2
{ uml::OP_FNEG, &drcbe_x64::op_fneg }, // FNEG dst,src1
{ uml::OP_FABS, &drcbe_x64::op_fabs }, // FABS dst,src1
{ uml::OP_FSQRT, &drcbe_x64::op_fsqrt }, // FSQRT dst,src1
{ uml::OP_FRECIP, &drcbe_x64::op_frecip }, // FRECIP dst,src1
{ uml::OP_FRSQRT, &drcbe_x64::op_frsqrt }, // FRSQRT dst,src1
{ uml::OP_FCOPYI, &drcbe_x64::op_fcopyi }, // FCOPYI dst,src
{ uml::OP_ICOPYF, &drcbe_x64::op_icopyf } // ICOPYF dst,src
};
//**************************************************************************
// INLINE FUNCTIONS
//**************************************************************************
//-------------------------------------------------
// param_normalize - convert a full parameter
// into a reduced set
//-------------------------------------------------
drcbe_x64::be_parameter::be_parameter(drcbe_x64 &drcbe, const parameter ¶m, uint32_t allowed)
{
int regnum;
switch (param.type())
{
// immediates pass through
case parameter::PTYPE_IMMEDIATE:
assert(allowed & PTYPE_I);
*this = param.immediate();
break;
// memory passes through
case parameter::PTYPE_MEMORY:
assert(allowed & PTYPE_M);
*this = make_memory(param.memory());
break;
// if a register maps to a register, keep it as a register; otherwise map it to memory
case parameter::PTYPE_INT_REGISTER:
assert(allowed & PTYPE_R);
assert(allowed & PTYPE_M);
regnum = int_register_map[param.ireg() - REG_I0];
if (regnum != 0)
*this = make_ireg(regnum);
else
*this = make_memory(&drcbe.m_state.r[param.ireg() - REG_I0]);
break;
// if a register maps to a register, keep it as a register; otherwise map it to memory
case parameter::PTYPE_FLOAT_REGISTER:
assert(allowed & PTYPE_F);
assert(allowed & PTYPE_M);
regnum = float_register_map[param.freg() - REG_F0];
if (regnum != 0)
*this = make_freg(regnum);
else
*this = make_memory(&drcbe.m_state.f[param.freg() - REG_F0]);
break;
// everything else is unexpected
default:
fatalerror("Unexpected parameter type\n");
}
}
//-------------------------------------------------
// select_register - select a register to use,
// avoiding conflicts with the optional
// checkparam
//-------------------------------------------------
inline int drcbe_x64::be_parameter::select_register(int defreg) const
{
if (m_type == PTYPE_INT_REGISTER || m_type == PTYPE_FLOAT_REGISTER || m_type == PTYPE_VECTOR_REGISTER)
return m_value;
return defreg;
}
inline int drcbe_x64::be_parameter::select_register(int defreg, const be_parameter &checkparam) const
{
if (*this == checkparam)
return defreg;
return select_register(defreg);
}
inline int drcbe_x64::be_parameter::select_register(int defreg, const be_parameter &checkparam, const be_parameter &checkparam2) const
{
if (*this == checkparam || *this == checkparam2)
return defreg;
return select_register(defreg);
}
//-------------------------------------------------
// select_register - select a register to use,
// avoiding conflicts with the optional
// checkparam
//-------------------------------------------------
inline void drcbe_x64::normalize_commutative(be_parameter &inner, be_parameter &outer)
{
// if the inner parameter is a memory operand, push it to the outer
if (inner.is_memory())
{
be_parameter temp = inner;
inner = outer;
outer = temp;
}
// if the inner parameter is an immediate, push it to the outer
if (inner.is_immediate())
{
be_parameter temp = inner;
inner = outer;
outer = temp;
}
}
//-------------------------------------------------
// offset_from_rbp - return the verified offset
// from rbp
//-------------------------------------------------
inline int32_t drcbe_x64::offset_from_rbp(const void *ptr)
{
const int64_t delta = reinterpret_cast<const uint8_t *>(ptr) - m_rbpvalue;
if (int32_t(delta) != delta)
throw emu_fatalerror("drcbe_x64::offset_from_rbp: delta out of range");
return int32_t(delta);
}
//-------------------------------------------------
// get_base_register_and_offset - determine right
// base register and offset to access the given
// target address
//-------------------------------------------------
inline int drcbe_x64::get_base_register_and_offset(x86code *&dst, void *target, uint8_t reg, int32_t &offset)
{
const int64_t delta = reinterpret_cast<uint8_t *>(target) - m_rbpvalue;
if (short_immediate(delta))
{
offset = delta;
return REG_RBP;
}
else
{
offset = 0;
emit_mov_r64_imm(dst, reg, uintptr_t(target)); // mov reg,target
return reg;
}
}
//-------------------------------------------------
// emit_smart_call_r64 - generate a call either
// directly or via a call through pointer
//-------------------------------------------------
inline void drcbe_x64::emit_smart_call_r64(x86code *&dst, x86code *target, uint8_t reg)
{
const int64_t delta = target - (dst + 5);
if (short_immediate(delta))
emit_call(dst, target); // call target
else
{
emit_mov_r64_imm(dst, reg, uintptr_t(target)); // mov reg,target
emit_call_r64(dst, reg); // call reg
}
}
//-------------------------------------------------
// emit_smart_call_m64 - generate a call either
// directly or via a call through pointer
//-------------------------------------------------
inline void drcbe_x64::emit_smart_call_m64(x86code *&dst, x86code **target)
{
const int64_t delta = *target - (dst + 5);
if (short_immediate(delta))
emit_call(dst, *target); // call *target
else
emit_call_m64(dst, MABS(target)); // call [target]
}
//**************************************************************************
// BACKEND CALLBACKS
//**************************************************************************
//-------------------------------------------------
// drcbe_x64 - constructor
//-------------------------------------------------
drcbe_x64::drcbe_x64(drcuml_state &drcuml, device_t &device, drc_cache &cache, uint32_t flags, int modes, int addrbits, int ignorebits)
: drcbe_interface(drcuml, cache, device),
m_hash(cache, modes, addrbits, ignorebits),
m_map(cache, 0xaaaaaaaa5555),
m_labels(cache),
m_log(nullptr),
m_sse41(false),
m_absmask32((uint32_t *)cache.alloc_near(16*2 + 15)),
m_absmask64(nullptr),
m_rbpvalue(cache.near() + 0x80),
m_entry(nullptr),
m_exit(nullptr),
m_nocode(nullptr),
m_fixup_label(&drcbe_x64::fixup_label, this),
m_fixup_exception(&drcbe_x64::fixup_exception, this),
m_near(*(near_state *)cache.alloc_near(sizeof(m_near)))
{
// build up necessary arrays
static const uint32_t sse_control[4] =
{
0xff80, // ROUND_TRUNC
0x9f80, // ROUND_ROUND
0xdf80, // ROUND_CEIL
0xbf80 // ROUND_FLOOR
};
memcpy(m_near.ssecontrol, sse_control, sizeof(m_near.ssecontrol));
m_near.single1 = 1.0f;
m_near.double1 = 1.0;
// create absolute value masks that are aligned to SSE boundaries
m_absmask32 = (uint32_t *)(((uintptr_t)m_absmask32 + 15) & ~15);
m_absmask32[0] = m_absmask32[1] = m_absmask32[2] = m_absmask32[3] = 0x7fffffff;
m_absmask64 = (uint64_t *)&m_absmask32[4];
m_absmask64[0] = m_absmask64[1] = 0x7fffffffffffffffU;
// get pointers to C functions we need to call
using debugger_hook_func = void (*)(device_debug *, offs_t);
static const debugger_hook_func debugger_inst_hook = [] (device_debug *dbg, offs_t pc) { dbg->instruction_hook(pc); }; // TODO: kill trampoline if possible
m_near.debug_cpu_instruction_hook = (x86code *)debugger_inst_hook;
if (LOG_HASHJMPS)
{
m_near.debug_log_hashjmp = (x86code *)debug_log_hashjmp;
m_near.debug_log_hashjmp_fail = (x86code *)debug_log_hashjmp_fail;
}
m_near.drcmap_get_value = (x86code *)&drc_map_variables::static_get_value;
// build the flags map
for (int entry = 0; entry < ARRAY_LENGTH(m_near.flagsmap); entry++)
{
uint8_t flags = 0;
if (entry & 0x001) flags |= FLAG_C;
if (entry & 0x004) flags |= FLAG_U;
if (entry & 0x040) flags |= FLAG_Z;
if (entry & 0x080) flags |= FLAG_S;
if (entry & 0x800) flags |= FLAG_V;
m_near.flagsmap[entry] = flags;
}
for (int entry = 0; entry < ARRAY_LENGTH(m_near.flagsunmap); entry++)
{
uint64_t flags = 0;
if (entry & FLAG_C) flags |= 0x001;
if (entry & FLAG_U) flags |= 0x004;
if (entry & FLAG_Z) flags |= 0x040;
if (entry & FLAG_S) flags |= 0x080;
if (entry & FLAG_V) flags |= 0x800;
m_near.flagsunmap[entry] = flags;
}
// build the opcode table (static but it doesn't hurt to regenerate it)
for (auto & elem : s_opcode_table_source)
s_opcode_table[elem.opcode] = elem.func;
// create the log
if (device.machine().options().drc_log_native())
{
std::string filename = std::string("drcbex64_").append(device.shortname()).append(".asm");
m_log = x86log_create_context(filename.c_str());
}
}
//-------------------------------------------------
// ~drcbe_x64 - destructor
//-------------------------------------------------
drcbe_x64::~drcbe_x64()
{
// free the log context
if (m_log != nullptr)
x86log_free_context(m_log);
}
//-------------------------------------------------
// reset - reset back-end specific state
//-------------------------------------------------
void drcbe_x64::reset()
{
// output a note to the log
if (m_log != nullptr)
x86log_printf(m_log, "%s", "\n\n===========\nCACHE RESET\n===========\n\n");
// generate a little bit of glue code to set up the environment
drccodeptr *cachetop = m_cache.begin_codegen(500);
if (cachetop == nullptr)
fatalerror("Out of cache space after a reset!\n");
x86code *dst = (x86code *)*cachetop;
// generate a simple CPUID stub
uint32_t (*cpuid_ecx_stub)(void) = (uint32_t (*)(void))dst;
emit_push_r64(dst, REG_RBX); // push rbx
emit_mov_r32_imm(dst, REG_EAX, 1); // mov eax,1
emit_cpuid(dst); // cpuid
emit_mov_r32_r32(dst, REG_EAX, REG_ECX); // mov eax,ecx
emit_pop_r64(dst, REG_RBX); // pop rbx
emit_ret(dst); // ret
// call it to determine if we have SSE4.1 support
m_sse41 = (((*cpuid_ecx_stub)() & 0x80000) != 0);
// generate an entry point
m_entry = (x86_entry_point_func)dst;
emit_push_r64(dst, REG_RBX); // push rbx
emit_push_r64(dst, REG_RSI); // push rsi
emit_push_r64(dst, REG_RDI); // push rdi
emit_push_r64(dst, REG_RBP); // push rbp
emit_push_r64(dst, REG_R12); // push r12
emit_push_r64(dst, REG_R13); // push r13
emit_push_r64(dst, REG_R14); // push r14
emit_push_r64(dst, REG_R15); // push r15
emit_mov_r64_r64(dst, REG_RBP, REG_PARAM1); // mov rbp,param1
emit_sub_r64_imm(dst, REG_RSP, 32); // sub rsp,32
emit_mov_m64_r64(dst, MABS(&m_near.hashstacksave), REG_RSP); // mov [hashstacksave],rsp
emit_sub_r64_imm(dst, REG_RSP, 8); // sub rsp,8
emit_mov_m64_r64(dst, MABS(&m_near.stacksave), REG_RSP); // mov [stacksave],rsp
emit_stmxcsr_m32(dst, MABS(&m_near.ssemode)); // stmxcsr [ssemode]
emit_jmp_r64(dst, REG_PARAM2); // jmp param2
if (m_log != nullptr)
x86log_disasm_code_range(m_log, "entry_point", (x86code *)m_entry, dst);
// generate an exit point
m_exit = dst;
emit_ldmxcsr_m32(dst, MABS(&m_near.ssemode)); // ldmxcsr [ssemode]
emit_mov_r64_m64(dst, REG_RSP, MABS(&m_near.hashstacksave)); // mov rsp,[hashstacksave]
emit_add_r64_imm(dst, REG_RSP, 32); // add rsp,32
emit_pop_r64(dst, REG_R15); // pop r15
emit_pop_r64(dst, REG_R14); // pop r14
emit_pop_r64(dst, REG_R13); // pop r13
emit_pop_r64(dst, REG_R12); // pop r12
emit_pop_r64(dst, REG_RBP); // pop rbp
emit_pop_r64(dst, REG_RDI); // pop rdi
emit_pop_r64(dst, REG_RSI); // pop rsi
emit_pop_r64(dst, REG_RBX); // pop rbx
emit_ret(dst); // ret
if (m_log != nullptr)
x86log_disasm_code_range(m_log, "exit_point", m_exit, dst);
// generate a no code point
m_nocode = dst;
emit_ret(dst); // ret
if (m_log != nullptr)
x86log_disasm_code_range(m_log, "nocode", m_nocode, dst);
// finish up codegen
*cachetop = (drccodeptr)dst;
m_cache.end_codegen();
// reset our hash tables
m_hash.reset();
m_hash.set_default_codeptr(m_nocode);
}
//-------------------------------------------------
// execute - execute a block of code referenced
// by the given handle
//-------------------------------------------------
int drcbe_x64::execute(code_handle &entry)
{
// call our entry point which will jump to the destination
return (*m_entry)(m_rbpvalue, (x86code *)entry.codeptr());
}
//-------------------------------------------------
// drcbex64_generate - generate code
//-------------------------------------------------
void drcbe_x64::generate(drcuml_block &block, const instruction *instlist, uint32_t numinst)
{
// tell all of our utility objects that a block is beginning
m_hash.block_begin(block, instlist, numinst);
m_labels.block_begin(block);
m_map.block_begin(block);
// begin codegen; fail if we can't
drccodeptr *cachetop = m_cache.begin_codegen(numinst * 8 * 4);
if (cachetop == nullptr)
block.abort();
// compute the base by aligning the cache top to a cache line (assumed to be 64 bytes)
x86code *base = (x86code *)(((uintptr_t)*cachetop + 63) & ~63);
x86code *dst = base;
// generate code
const char *blockname = nullptr;
for (int inum = 0; inum < numinst; inum++)
{
const instruction &inst = instlist[inum];
assert(inst.opcode() < ARRAY_LENGTH(s_opcode_table));
// add a comment
if (m_log != nullptr)
{
std::string dasm = inst.disasm(&m_drcuml);
x86log_add_comment(m_log, dst, "%s", dasm.c_str());
}
// extract a blockname
if (blockname == nullptr)
{
if (inst.opcode() == OP_HANDLE)
blockname = inst.param(0).handle().string();
else if (inst.opcode() == OP_HASH)
blockname = string_format("Code: mode=%d PC=%08X", (uint32_t)inst.param(0).immediate(), (offs_t)inst.param(1).immediate()).c_str();
}
// generate code
(this->*s_opcode_table[inst.opcode()])(dst, inst);
}
// complete codegen
*cachetop = (drccodeptr)dst;
m_cache.end_codegen();
// log it
if (m_log != nullptr)
x86log_disasm_code_range(m_log, (blockname == nullptr) ? "Unknown block" : blockname, base, m_cache.top());
// tell all of our utility objects that the block is finished
m_hash.block_end(block);
m_labels.block_end(block);
m_map.block_end(block);
}
//-------------------------------------------------
// hash_exists - return true if the given mode/pc
// exists in the hash table
//-------------------------------------------------
bool drcbe_x64::hash_exists(uint32_t mode, uint32_t pc)
{
return m_hash.code_exists(mode, pc);
}
//-------------------------------------------------
// get_info - return information about the
// back-end implementation
//-------------------------------------------------
void drcbe_x64::get_info(drcbe_info &info)
{
for (info.direct_iregs = 0; info.direct_iregs < REG_I_COUNT; info.direct_iregs++)
if (int_register_map[info.direct_iregs] == 0)
break;
for (info.direct_fregs = 0; info.direct_fregs < REG_F_COUNT; info.direct_fregs++)
if (float_register_map[info.direct_fregs] == 0)
break;
}
/***************************************************************************
EMITTERS FOR 32-BIT OPERATIONS WITH PARAMETERS
***************************************************************************/
//-------------------------------------------------
// emit_mov_r32_p32 - move a 32-bit parameter
// into a register
//-------------------------------------------------
void drcbe_x64::emit_mov_r32_p32(x86code *&dst, uint8_t reg, const be_parameter ¶m)
{
if (param.is_immediate())
{
if (param.immediate() == 0)
emit_xor_r32_r32(dst, reg, reg); // xor reg,reg
else
emit_mov_r32_imm(dst, reg, param.immediate()); // mov reg,param
}
else if (param.is_memory())
emit_mov_r32_m32(dst, reg, MABS(param.memory())); // mov reg,[param]
else if (param.is_int_register())
{
if (reg != param.ireg())
emit_mov_r32_r32(dst, reg, param.ireg()); // mov reg,param
}
}
//-------------------------------------------------
// emit_movsx_r64_p32 - move a 32-bit parameter
// sign-extended into a register
//-------------------------------------------------
void drcbe_x64::emit_movsx_r64_p32(x86code *&dst, uint8_t reg, const be_parameter ¶m)
{
if (param.is_immediate())
{
if (param.immediate() == 0)
emit_xor_r32_r32(dst, reg, reg); // xor reg,reg
else if ((int32_t)param.immediate() >= 0)
emit_mov_r32_imm(dst, reg, param.immediate()); // mov reg,param
else
emit_mov_r64_imm(dst, reg, (int32_t)param.immediate()); // mov reg,param
}
else if (param.is_memory())
emit_movsxd_r64_m32(dst, reg, MABS(param.memory())); // movsxd reg,[param]
else if (param.is_int_register())
emit_movsxd_r64_r32(dst, reg, param.ireg()); // movsdx reg,param
}
//-------------------------------------------------
// emit_mov_r32_p32_keepflags - move a 32-bit
// parameter into a register without affecting
// any flags
//-------------------------------------------------
void drcbe_x64::emit_mov_r32_p32_keepflags(x86code *&dst, uint8_t reg, const be_parameter ¶m)
{
if (param.is_immediate())
emit_mov_r32_imm(dst, reg, param.immediate()); // mov reg,param
else if (param.is_memory())
emit_mov_r32_m32(dst, reg, MABS(param.memory())); // mov reg,[param]
else if (param.is_int_register())
{
if (reg != param.ireg())
emit_mov_r32_r32(dst, reg, param.ireg()); // mov reg,param
}
}
//-------------------------------------------------
// emit_mov_m32_p32 - move a 32-bit parameter
// into a memory location
//-------------------------------------------------
void drcbe_x64::emit_mov_m32_p32(x86code *&dst, x86_memref memref, const be_parameter ¶m)
{
if (param.is_immediate())
emit_mov_m32_imm(dst, memref, param.immediate()); // mov [mem],param
else if (param.is_memory())
{
emit_mov_r32_m32(dst, REG_EAX, MABS(param.memory())); // mov eax,[param]
emit_mov_m32_r32(dst, memref, REG_EAX); // mov [mem],eax
}
else if (param.is_int_register())
emit_mov_m32_r32(dst, memref, param.ireg()); // mov [mem],param
}
//-------------------------------------------------
// emit_mov_p32_r32 - move a register into a
// 32-bit parameter
//-------------------------------------------------
void drcbe_x64::emit_mov_p32_r32(x86code *&dst, const be_parameter ¶m, uint8_t reg)
{
assert(!param.is_immediate());
if (param.is_memory())
emit_mov_m32_r32(dst, MABS(param.memory()), reg); // mov [param],reg
else if (param.is_int_register())
{
if (reg != param.ireg())
emit_mov_r32_r32(dst, param.ireg(), reg); // mov param,reg
}